]> git.proxmox.com Git - mirror_edk2.git/blob - EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/X64/Cpu.asm
Sync all bug fixes between EDK1.04 and EDK1.06 into EdkCompatibilityPkg.
[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Cpu / Pentium / CpuIA32Lib / X64 / Cpu.asm
1 TITLE Cpu.asm: Assembly code for the x64 resources
2
3 ;------------------------------------------------------------------------------
4 ;*
5 ;* Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>
6 ;* This program and the accompanying materials
7 ;* are licensed and made available under the terms and conditions of the BSD License
8 ;* which accompanies this distribution. The full text of the license may be found at
9 ;* http://opensource.org/licenses/bsd-license.php
10 ;*
11 ;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 ;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 ;*
14 ;* Module Name:
15 ;*
16 ;* Cpu.asm
17 ;*
18 ;* Abstract:
19 ;*
20 ;------------------------------------------------------------------------------
21
22 text SEGMENT
23
24
25 ;------------------------------------------------------------------------------
26 ; VOID
27 ; EfiHalt (
28 ; VOID
29 ; )
30 ;------------------------------------------------------------------------------
31 EfiHalt PROC PUBLIC
32 hlt
33 ret
34 EfiHalt ENDP
35
36
37 ;------------------------------------------------------------------------------
38 ; VOID
39 ; EfiWbinvd (
40 ; VOID
41 ; )
42 ;------------------------------------------------------------------------------
43 EfiWbinvd PROC PUBLIC
44 wbinvd
45 ret
46 EfiWbinvd ENDP
47
48
49 ;------------------------------------------------------------------------------
50 ; VOID
51 ; EfiInvd (
52 ; VOID
53 ; )
54 ;------------------------------------------------------------------------------
55 EfiInvd PROC PUBLIC
56 invd
57 ret
58 EfiInvd ENDP
59
60 ;------------------------------------------------------------------------------
61 ; VOID
62 ; EfiCpuid (
63 ; IN UINT32 RegisterInEax, // rcx
64 ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
65 ; )
66 ;------------------------------------------------------------------------------
67 EfiCpuid PROC PUBLIC
68 push rbx
69
70 mov r8, rdx ; r8 = *Reg
71 mov rax, rcx ; RegisterInEax
72 cpuid
73 cmp r8, 0
74 je _Exit
75 mov [r8 + 0], eax ; Reg->RegEax
76 mov [r8 + 4], ebx ; Reg->RegEbx
77 mov [r8 + 8], ecx ; Reg->RegEcx
78 mov [r8 + 12], edx ; Reg->RegEdx
79
80 _Exit:
81 pop rbx
82 ret
83 EfiCpuid ENDP
84
85 ;------------------------------------------------------------------------------
86 ; UINT64
87 ; EfiReadMsr (
88 ; IN UINT32 Index, // rcx
89 ; )
90 ;------------------------------------------------------------------------------
91 EfiReadMsr PROC PUBLIC
92 rdmsr
93 sal rdx, 32 ; edx:eax -> rax
94 or rax, rdx ; rax = edx:eax
95 ret
96 EfiReadMsr ENDP
97
98 ;------------------------------------------------------------------------------
99 ; VOID
100 ; EfiWriteMsr (
101 ; IN UINT32 Index, // rcx
102 ; IN UINT64 Value // rdx
103 ; )
104 ;------------------------------------------------------------------------------
105 EfiWriteMsr PROC PUBLIC
106 mov rax, rdx ; rdx = Value
107 sar rdx, 32 ; convert rdx to edx upper 32-bits
108 wrmsr ; wrmsr[ecx] result = edx:eax
109 ret
110 EfiWriteMsr ENDP
111
112
113 ;------------------------------------------------------------------------------
114 ; UINT64
115 ; EfiReadTsc (
116 ; VOID
117 ; );
118 ;------------------------------------------------------------------------------
119 EfiReadTsc PROC PUBLIC
120 rdtsc
121 shl rax, 32
122 shrd rax, rdx, 32
123 ret
124 EfiReadTsc ENDP
125
126 ;------------------------------------------------------------------------------
127 ; VOID
128 ; EfiDisableCache (
129 ; VOID
130 ; );
131 ;------------------------------------------------------------------------------
132 EfiDisableCache PROC PUBLIC
133 ; added a check to see if cache is already disabled. If it is, then skip.
134 mov rax, cr0
135 and rax, 060000000h
136 cmp rax, 0
137 jne @f
138 mov rax, cr0
139 or rax, 060000000h
140 mov cr0, rax
141 wbinvd
142 @@:
143 ret
144 EfiDisableCache ENDP
145
146 ;------------------------------------------------------------------------------
147 ; VOID
148 ; EfiEnableCache (
149 ; VOID
150 ; );
151 ;------------------------------------------------------------------------------
152 EfiEnableCache PROC PUBLIC
153 wbinvd
154 mov rax, cr0
155 and rax, 09fffffffh
156 mov cr0, rax
157 ret
158 EfiEnableCache ENDP
159
160 ;------------------------------------------------------------------------------
161 ; UINTN
162 ; EfiGetEflags (
163 ; VOID
164 ; );
165 ;------------------------------------------------------------------------------
166 EfiGetEflags PROC PUBLIC
167 pushfq
168 pop rax
169 ret
170 EfiGetEflags ENDP
171
172 ;------------------------------------------------------------------------------
173 ; VOID
174 ; EfiDisableInterrupts (
175 ; VOID
176 ; );
177 ;------------------------------------------------------------------------------
178 EfiDisableInterrupts PROC PUBLIC
179 cli
180 ret
181 EfiDisableInterrupts ENDP
182
183 ;------------------------------------------------------------------------------
184 ; VOID
185 ; EfiEnableInterrupts (
186 ; VOID
187 ; );
188 ;------------------------------------------------------------------------------
189 EfiEnableInterrupts PROC PUBLIC
190 sti
191 ret
192 EfiEnableInterrupts ENDP
193 ;------------------------------------------------------------------------------
194 ; VOID
195 ; EfiCpuidExt (
196 ; IN UINT32 RegisterInEax,
197 ; IN UINT32 CacheLevel,
198 ; OUT EFI_CPUID_REGISTER *Regs
199 ; )
200 ;------------------------------------------------------------------------------
201 EfiCpuidExt PROC PUBLIC
202 push rbx
203 mov rax, rcx ; rax = RegisterInEax
204 mov rcx, rdx ; rcx = CacheLevel
205
206 cpuid
207 mov [r8 + 0 ], eax ; Reg->RegEax
208 mov [r8 + 4 ], ebx ; Reg->RegEbx
209 mov [r8 + 8 ], ecx ; Reg->RegEcx
210 mov [r8 + 12], edx ; Reg->RegEdx
211
212 pop rbx
213 ret
214 EfiCpuidExt ENDP
215 END