EdkCompatibilityPkg/Foundation/Framework/Protocol/SmmCpuState/CpuSaveState.h

   1 /*++
   2
   3 Copyright (c) 2005, Intel Corporation. All rights reserved.<BR>
   4 This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12
  13 Module Name:
  14
  15   CpuSaveState.h
  16
  17 Abstract:
  18
  19   Define data structures used by EFI_SMM_CPU_SAVE_STATE protocol.
  20
  21 Revision History
  22
  23 ++*/
  24
  25 #ifndef _CPUSAVESTATE_H_
  26 #define _CPUSAVESTATE_H_
  27
  28 typedef unsigned char               ASM_UINT8;
  29 typedef ASM_UINT8                   ASM_BOOL;
  30 typedef unsigned short              ASM_UINT16;
  31 typedef unsigned long               ASM_UINT32;
  32
  33 #ifdef _H2INC
  34 typedef double                      ASM_UINT64;
  35 #else
  36 typedef UINT64                      ASM_UINT64;
  37 #endif
  38
  39 #ifndef __GNUC__
  40 #pragma pack (push)
  41 #pragma pack (1)
  42 #endif
  43
  44 typedef struct _EFI_SMM_CPU_STATE32 {
  45   ASM_UINT8                         Reserved1[0xf8];        // fe00h
  46   ASM_UINT32                        SMBASE;                 // fef8h
  47   ASM_UINT32                        SMMRevId;               // fefch
  48   ASM_UINT16                        IORestart;              // ff00h
  49   ASM_UINT16                        AutoHALTRestart;        // ff02h
  50   ASM_UINT32                        IEDBASE;                // ff04h
  51   ASM_UINT8                         Reserved2[0x98];        // ff08h
  52   ASM_UINT32                        IOMemAddr;              // ffa0h
  53   ASM_UINT32                        IOMisc;                 // ffa4h
  54   ASM_UINT32                        _ES;
  55   ASM_UINT32                        _CS;
  56   ASM_UINT32                        _SS;
  57   ASM_UINT32                        _DS;
  58   ASM_UINT32                        _FS;
  59   ASM_UINT32                        _GS;
  60   ASM_UINT32                        _LDTBase;
  61   ASM_UINT32                        _TR;
  62   ASM_UINT32                        _DR7;
  63   ASM_UINT32                        _DR6;
  64   ASM_UINT32                        _EAX;
  65   ASM_UINT32                        _ECX;
  66   ASM_UINT32                        _EDX;
  67   ASM_UINT32                        _EBX;
  68   ASM_UINT32                        _ESP;
  69   ASM_UINT32                        _EBP;
  70   ASM_UINT32                        _ESI;
  71   ASM_UINT32                        _EDI;
  72   ASM_UINT32                        _EIP;
  73   ASM_UINT32                        _EFLAGS;
  74   ASM_UINT32                        _CR3;
  75   ASM_UINT32                        _CR0;
  76 } EFI_SMM_CPU_STATE32;
  77
  78 typedef struct _EFI_SMM_CPU_STATE64 {
  79   ASM_UINT8                         Reserved1[0x1d0];       // fc00h
  80   ASM_UINT32                        GdtBaseHiDword;         // fdd0h
  81   ASM_UINT32                        LdtBaseHiDword;         // fdd4h
  82   ASM_UINT32                        IdtBaseHiDword;         // fdd8h
  83   ASM_UINT8                         Reserved2[0xc];         // fddch
  84   ASM_UINT64                        IO_EIP;                 // fde8h
  85   ASM_UINT8                         Reserved3[0x50];        // fdf0h
  86   ASM_UINT32                        _CR4;                   // fe40h
  87   ASM_UINT8                         Reserved4[0x48];        // fe44h
  88   ASM_UINT32                        GdtBaseLoDword;         // fe8ch
  89   ASM_UINT32                        GdtLimit;               // fe90h
  90   ASM_UINT32                        IdtBaseLoDword;         // fe94h
  91   ASM_UINT32                        IdtLimit;               // fe98h
  92   ASM_UINT32                        LdtBaseLoDword;         // fe9ch
  93   ASM_UINT32                        LdtLimit;               // fea0h
  94   ASM_UINT32                        LdtInfo;                // fea4h
  95   ASM_UINT8                         Reserved5[0x50];        // fea8h
  96   ASM_UINT32                        SMBASE;                 // fef8h
  97   ASM_UINT32                        SMMRevId;               // fefch
  98   ASM_UINT16                        IORestart;              // ff00h
  99   ASM_UINT16                        AutoHALTRestart;        // ff02h
 100   ASM_UINT32                        IEDBASE;                // ff04h
 101   ASM_UINT8                         Reserved6[0x14];        // ff08h
 102   ASM_UINT64                        _R15;                   // ff1ch
 103   ASM_UINT64                        _R14;
 104   ASM_UINT64                        _R13;
 105   ASM_UINT64                        _R12;
 106   ASM_UINT64                        _R11;
 107   ASM_UINT64                        _R10;
 108   ASM_UINT64                        _R9;
 109   ASM_UINT64                        _R8;
 110   ASM_UINT64                        _RAX;                   // ff5ch
 111   ASM_UINT64                        _RCX;
 112   ASM_UINT64                        _RDX;
 113   ASM_UINT64                        _RBX;
 114   ASM_UINT64                        _RSP;
 115   ASM_UINT64                        _RBP;
 116   ASM_UINT64                        _RSI;
 117   ASM_UINT64                        _RDI;
 118   ASM_UINT64                        IOMemAddr;              // ff9ch
 119   ASM_UINT32                        IOMisc;                 // ffa4h
 120   ASM_UINT32                        _ES;                    // ffa8h
 121   ASM_UINT32                        _CS;
 122   ASM_UINT32                        _SS;
 123   ASM_UINT32                        _DS;
 124   ASM_UINT32                        _FS;
 125   ASM_UINT32                        _GS;
 126   ASM_UINT32                        _LDTR;                  // ffc0h
 127   ASM_UINT32                        _TR;
 128   ASM_UINT64                        _DR7;                   // ffc8h
 129   ASM_UINT64                        _DR6;
 130   ASM_UINT64                        _RIP;                   // ffd8h
 131   ASM_UINT64                        IA32_EFER;              // ffe0h
 132   ASM_UINT64                        _RFLAGS;                // ffe8h
 133   ASM_UINT64                        _CR3;                   // fff0h
 134   ASM_UINT64                        _CR0;                   // fff8h
 135 } EFI_SMM_CPU_STATE64;
 136
 137 #ifndef __GNUC__
 138 #pragma warning (push)
 139 #pragma warning (disable: 4201)
 140 #endif
 141
 142
 143 typedef union _EFI_SMM_CPU_STATE {
 144   struct {
 145     ASM_UINT8                       Reserved[0x200];
 146     EFI_SMM_CPU_STATE32             x86;
 147   };
 148   EFI_SMM_CPU_STATE64               x64;
 149 } EFI_SMM_CPU_STATE;
 150
 151 #ifndef __GNUC__
 152 #pragma warning (pop)
 153 #pragma pack (pop)
 154 #endif
 155
 156 #define EFI_SMM_MIN_REV_ID_x64      0x30006
 157
 158 #endif