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Program SD Cards into 4-bit mode (support for this is required in the spec). This...
[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Include / EfiPxe.h
1 /*++
2
3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module name:
13
14 EfiPxe.h
15
16 32/64-bit PXE specification:
17
18 alpha-4, 99-Dec-17
19
20 Abstract:
21
22 This header file contains all of the PXE type definitions,
23 structure prototypes, global variables and constants that
24 are needed for porting PXE to EFI.
25 --*/
26
27 #ifndef _EFIPXE_H
28 #define _EFIPXE_H
29
30 #pragma pack(1)
31
32 #define PXE_INTEL_ORDER 1 // Intel order
33 // #define PXE_NETWORK_ORDER 1 // network order
34 //
35 #define PXE_UINT64_SUPPORT 1 // UINT64 supported
36 #if PXE_UINT64_SUPPORT == 0
37 #define PXE_NO_UINT64_SUPPORT 1
38 #else
39 #define PXE_NO_UINT64_SUPPORT 0
40 #endif
41 //
42 #define PXE_BUSTYPE(a, b, c, d) \
43 ( \
44 (((UINT32) (d) & 0xFF) << 24) | (((UINT32) (c) & 0xFF) << 16) | (((UINT32) (b) & 0xFF) << 8) | \
45 ((UINT32) (a) & 0xFF) \
46 )
47
48 //
49 // UNDI ROM ID and devive ID signature
50 //
51 #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
52
53 //
54 // BUS ROM ID signatures
55 //
56 #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')
57 #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
58 #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')
59 #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')
60
61 #define PXE_SWAP_UINT16(n) ((((UINT16) (n) & 0x00FF) << 8) | (((UINT16) (n) & 0xFF00) >> 8))
62
63 #define PXE_SWAP_UINT32(n) \
64 ((((UINT32)(n) & 0x000000FF) << 24) | \
65 (((UINT32)(n) & 0x0000FF00) << 8) | \
66 (((UINT32)(n) & 0x00FF0000) >> 8) | \
67 (((UINT32)(n) & 0xFF000000) >> 24))
68
69 #if PXE_UINT64_SUPPORT != 0
70 #define PXE_SWAP_UINT64(n) \
71 ((((UINT64)(n) & 0x00000000000000FF) << 56) | \
72 (((UINT64)(n) & 0x000000000000FF00) << 40) | \
73 (((UINT64)(n) & 0x0000000000FF0000) << 24) | \
74 (((UINT64)(n) & 0x00000000FF000000) << 8) | \
75 (((UINT64)(n) & 0x000000FF00000000) >> 8) | \
76 (((UINT64)(n) & 0x0000FF0000000000) >> 24) | \
77 (((UINT64)(n) & 0x00FF000000000000) >> 40) | \
78 (((UINT64)(n) & 0xFF00000000000000) >> 56))
79 #endif // PXE_UINT64_SUPPORT
80 #if PXE_NO_UINT64_SUPPORT != 0
81 #define PXE_SWAP_UINT64(n) { \
82 UINT32 tmp; \
83 tmp = (PXE_UINT64) (n)[1]; \
84 (UINT64) (n)[1] = PXE_SWAP_UINT32 ((UINT64) (n)[0]); \
85 (UINT64) (n)[0] = tmp; \
86 }
87 #endif // PXE_NO_UINT64_SUPPORT
88 #define PXE_CPBSIZE_NOT_USED 0 // zero
89 #define PXE_DBSIZE_NOT_USED 0 // zero
90 #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 // zero
91 #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 // zero
92 #define PXE_CONST const
93
94 #define PXE_VOLATILE volatile
95
96 #if PXE_UINT64_SUPPORT != 0
97 //
98 // typedef unsigned long PXE_UINT64;
99 //
100 typedef UINT64 PXE_UINT64;
101 #endif // PXE_UINT64_SUPPORT
102 #if PXE_NO_UINT64_SUPPORT != 0
103 typedef PXE_UINT32 PXE_UINT64[2];
104 #endif // PXE_NO_UINT64_SUPPORT
105 #define PXE_FALSE 0 // zero
106 #define PXE_TRUE (!PXE_FALSE)
107
108 typedef UINT16 PXE_OPCODE;
109
110 //
111 // Return UNDI operational state.
112 //
113 #define PXE_OPCODE_GET_STATE 0x0000
114
115 //
116 // Change UNDI operational state from Stopped to Started.
117 //
118 #define PXE_OPCODE_START 0x0001
119
120 //
121 // Change UNDI operational state from Started to Stopped.
122 //
123 #define PXE_OPCODE_STOP 0x0002
124
125 //
126 // Get UNDI initialization information.
127 //
128 #define PXE_OPCODE_GET_INIT_INFO 0x0003
129
130 //
131 // Get NIC configuration information.
132 //
133 #define PXE_OPCODE_GET_CONFIG_INFO 0x0004
134
135 //
136 // Changed UNDI operational state from Started to Initialized.
137 //
138 #define PXE_OPCODE_INITIALIZE 0x0005
139
140 //
141 // Re-initialize the NIC H/W.
142 //
143 #define PXE_OPCODE_RESET 0x0006
144
145 //
146 // Change the UNDI operational state from Initialized to Started.
147 //
148 #define PXE_OPCODE_SHUTDOWN 0x0007
149
150 //
151 // Read & change state of external interrupt enables.
152 //
153 #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
154
155 //
156 // Read & change state of packet receive filters.
157 //
158 #define PXE_OPCODE_RECEIVE_FILTERS 0x0009
159
160 //
161 // Read & change station MAC address.
162 //
163 #define PXE_OPCODE_STATION_ADDRESS 0x000A
164
165 //
166 // Read traffic statistics.
167 //
168 #define PXE_OPCODE_STATISTICS 0x000B
169
170 //
171 // Convert multicast IP address to multicast MAC address.
172 //
173 #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
174
175 //
176 // Read or change non-volatile storage on the NIC.
177 //
178 #define PXE_OPCODE_NVDATA 0x000D
179
180 //
181 // Get & clear interrupt status.
182 //
183 #define PXE_OPCODE_GET_STATUS 0x000E
184
185 //
186 // Fill media header in packet for transmit.
187 //
188 #define PXE_OPCODE_FILL_HEADER 0x000F
189
190 //
191 // Transmit packet(s).
192 //
193 #define PXE_OPCODE_TRANSMIT 0x0010
194
195 //
196 // Receive packet.
197 //
198 #define PXE_OPCODE_RECEIVE 0x0011
199
200 //
201 // last valid opcode:
202 //
203 #define PXE_OPCODE_VALID_MAX 0x0011
204
205 //
206 // Last valid PXE UNDI OpCode number.
207 //
208 #define PXE_OPCODE_LAST_VALID 0x0011
209
210 typedef UINT16 PXE_OPFLAGS;
211
212 #define PXE_OPFLAGS_NOT_USED 0x0000
213
214 //
215 // //////////////////////////////////////
216 // UNDI Get State
217 //
218 // No OpFlags
219
220 ////////////////////////////////////////
221 // UNDI Start
222 //
223 // No OpFlags
224
225 ////////////////////////////////////////
226 // UNDI Stop
227 //
228 // No OpFlags
229
230 ////////////////////////////////////////
231 // UNDI Get Init Info
232 //
233 // No Opflags
234
235 ////////////////////////////////////////
236 // UNDI Get Config Info
237 //
238 // No Opflags
239
240 ////////////////////////////////////////
241 // UNDI Initialize
242 //
243 #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
244 #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
245 #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
246
247 //
248 // //////////////////////////////////////
249 // UNDI Reset
250 //
251 #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
252 #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
253
254 //
255 // //////////////////////////////////////
256 // UNDI Shutdown
257 //
258 // No OpFlags
259
260 ////////////////////////////////////////
261 // UNDI Interrupt Enables
262 //
263 //
264 // Select whether to enable or disable external interrupt signals.
265 // Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.
266 //
267 #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
268 #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
269 #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
270 #define PXE_OPFLAGS_INTERRUPT_READ 0x0000
271
272 //
273 // Enable receive interrupts. An external interrupt will be generated
274 // after a complete non-error packet has been received.
275 //
276 #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
277
278 //
279 // Enable transmit interrupts. An external interrupt will be generated
280 // after a complete non-error packet has been transmitted.
281 //
282 #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
283
284 //
285 // Enable command interrupts. An external interrupt will be generated
286 // when command execution stops.
287 //
288 #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
289
290 //
291 // Generate software interrupt. Setting this bit generates an external
292 // interrupt, if it is supported by the hardware.
293 //
294 #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008
295
296 //
297 // //////////////////////////////////////
298 // UNDI Receive Filters
299 //
300 //
301 // Select whether to enable or disable receive filters.
302 // Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.
303 //
304 #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
305 #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
306 #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
307 #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
308
309 //
310 // To reset the contents of the multicast MAC address filter list,
311 // set this OpFlag:
312 //
313 #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
314
315 //
316 // Enable unicast packet receiving. Packets sent to the current station
317 // MAC address will be received.
318 //
319 #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
320
321 //
322 // Enable broadcast packet receiving. Packets sent to the broadcast
323 // MAC address will be received.
324 //
325 #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
326
327 //
328 // Enable filtered multicast packet receiving. Packets sent to any
329 // of the multicast MAC addresses in the multicast MAC address filter
330 // list will be received. If the filter list is empty, no multicast
331 //
332 #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
333
334 //
335 // Enable promiscuous packet receiving. All packets will be received.
336 //
337 #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
338
339 //
340 // Enable promiscuous multicast packet receiving. All multicast
341 // packets will be received.
342 //
343 #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
344
345 //
346 // //////////////////////////////////////
347 // UNDI Station Address
348 //
349 #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
350 #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
351 #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
352
353 //
354 // //////////////////////////////////////
355 // UNDI Statistics
356 //
357 #define PXE_OPFLAGS_STATISTICS_READ 0x0000
358 #define PXE_OPFLAGS_STATISTICS_RESET 0x0001
359
360 //
361 // //////////////////////////////////////
362 // UNDI MCast IP to MAC
363 //
364 //
365 // Identify the type of IP address in the CPB.
366 //
367 #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
368 #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
369 #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
370
371 //
372 // //////////////////////////////////////
373 // UNDI NvData
374 //
375 //
376 // Select the type of non-volatile data operation.
377 //
378 #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
379 #define PXE_OPFLAGS_NVDATA_READ 0x0000
380 #define PXE_OPFLAGS_NVDATA_WRITE 0x0001
381
382 //
383 // //////////////////////////////////////
384 // UNDI Get Status
385 //
386 //
387 // Return current interrupt status. This will also clear any interrupts
388 // that are currently set. This can be used in a polling routine. The
389 // interrupt flags are still set and cleared even when the interrupts
390 // are disabled.
391 //
392 #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
393
394 //
395 // Return list of transmitted buffers for recycling. Transmit buffers
396 // must not be changed or unallocated until they have recycled. After
397 // issuing a transmit command, wait for a transmit complete interrupt.
398 // When a transmit complete interrupt is received, read the transmitted
399 // buffers. Do not plan on getting one buffer per interrupt. Some
400 // NICs and UNDIs may transmit multiple buffers per interrupt.
401 //
402 #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
403
404 //
405 // //////////////////////////////////////
406 // UNDI Fill Header
407 //
408 #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
409 #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
410 #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
411
412 //
413 // //////////////////////////////////////
414 // UNDI Transmit
415 //
416 //
417 // S/W UNDI only. Return after the packet has been transmitted. A
418 // transmit complete interrupt will still be generated and the transmit
419 // buffer will have to be recycled.
420 //
421 #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
422 #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
423 #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
424
425 //
426 //
427 //
428 #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
429 #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
430 #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
431
432 //
433 // //////////////////////////////////////
434 // UNDI Receive
435 //
436 // No OpFlags
437 //
438 typedef UINT16 PXE_STATFLAGS;
439
440 #define PXE_STATFLAGS_INITIALIZE 0x0000
441
442 //
443 // //////////////////////////////////////
444 // Common StatFlags that can be returned by all commands.
445 //
446 //
447 // The COMMAND_COMPLETE and COMMAND_FAILED status flags must be
448 // implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs
449 // that support command queuing.
450 //
451 #define PXE_STATFLAGS_STATUS_MASK 0xC000
452 #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
453 #define PXE_STATFLAGS_COMMAND_FAILED 0x8000
454 #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
455 //
456 // #define PXE_STATFLAGS_INITIALIZE 0x0000
457 //
458 #define PXE_STATFLAGS_DB_WRITE_TRUNCATED 0x2000
459
460 //
461 // //////////////////////////////////////
462 // UNDI Get State
463 //
464 #define PXE_STATFLAGS_GET_STATE_MASK 0x0003
465 #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
466 #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
467 #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
468
469 //
470 // //////////////////////////////////////
471 // UNDI Start
472 //
473 // No additional StatFlags
474
475 ////////////////////////////////////////
476 // UNDI Get Init Info
477 //
478 #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
479 #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
480 #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
481
482 //
483 // //////////////////////////////////////
484 // UNDI Initialize
485 //
486 #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
487
488 //
489 // //////////////////////////////////////
490 // UNDI Reset
491 //
492 #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
493
494 //
495 // //////////////////////////////////////
496 // UNDI Shutdown
497 //
498 // No additional StatFlags
499
500 ////////////////////////////////////////
501 // UNDI Interrupt Enables
502 //
503 //
504 // If set, receive interrupts are enabled.
505 //
506 #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
507
508 //
509 // If set, transmit interrupts are enabled.
510 //
511 #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
512
513 //
514 // If set, command interrupts are enabled.
515 //
516 #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
517
518 //
519 // //////////////////////////////////////
520 // UNDI Receive Filters
521 //
522 //
523 // If set, unicast packets will be received.
524 //
525 #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
526
527 //
528 // If set, broadcast packets will be received.
529 //
530 #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
531
532 //
533 // If set, multicast packets that match up with the multicast address
534 // filter list will be received.
535 //
536 #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
537
538 //
539 // If set, all packets will be received.
540 //
541 #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
542
543 //
544 // If set, all multicast packets will be received.
545 //
546 #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
547
548 //
549 // //////////////////////////////////////
550 // UNDI Station Address
551 //
552 // No additional StatFlags
553
554 ////////////////////////////////////////
555 // UNDI Statistics
556 //
557 // No additional StatFlags
558
559 ////////////////////////////////////////
560 // UNDI MCast IP to MAC
561 //
562 // No additional StatFlags
563
564 ////////////////////////////////////////
565 // UNDI NvData
566 //
567 // No additional StatFlags
568
569
570 ////////////////////////////////////////
571 // UNDI Get Status
572 //
573 //
574 // Use to determine if an interrupt has occurred.
575 //
576 #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
577 #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
578
579 //
580 // If set, at least one receive interrupt occurred.
581 //
582 #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
583
584 //
585 // If set, at least one transmit interrupt occurred.
586 //
587 #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
588
589 //
590 // If set, at least one command interrupt occurred.
591 //
592 #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
593
594 //
595 // If set, at least one software interrupt occurred.
596 //
597 #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
598
599 //
600 // This flag is set if the transmitted buffer queue is empty. This flag
601 // will be set if all transmitted buffer addresses get written into the DB.
602 //
603 #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
604
605 //
606 // This flag is set if no transmitted buffer addresses were written
607 // into the DB. (This could be because DBsize was too small.)
608 //
609 #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
610
611 //
612 // //////////////////////////////////////
613 // UNDI Fill Header
614 //
615 // No additional StatFlags
616
617 ////////////////////////////////////////
618 // UNDI Transmit
619 //
620 // No additional StatFlags.
621
622 ////////////////////////////////////////
623 // UNDI Receive
624 //
625 // No additional StatFlags.
626 //
627 typedef UINT16 PXE_STATCODE;
628
629 #define PXE_STATCODE_INITIALIZE 0x0000
630
631 //
632 // //////////////////////////////////////
633 // Common StatCodes returned by all UNDI commands, UNDI protocol functions
634 // and BC protocol functions.
635 //
636 #define PXE_STATCODE_SUCCESS 0x0000
637
638 #define PXE_STATCODE_INVALID_CDB 0x0001
639 #define PXE_STATCODE_INVALID_CPB 0x0002
640 #define PXE_STATCODE_BUSY 0x0003
641 #define PXE_STATCODE_QUEUE_FULL 0x0004
642 #define PXE_STATCODE_ALREADY_STARTED 0x0005
643 #define PXE_STATCODE_NOT_STARTED 0x0006
644 #define PXE_STATCODE_NOT_SHUTDOWN 0x0007
645 #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
646 #define PXE_STATCODE_NOT_INITIALIZED 0x0009
647 #define PXE_STATCODE_DEVICE_FAILURE 0x000A
648 #define PXE_STATCODE_NVDATA_FAILURE 0x000B
649 #define PXE_STATCODE_UNSUPPORTED 0x000C
650 #define PXE_STATCODE_BUFFER_FULL 0x000D
651 #define PXE_STATCODE_INVALID_PARAMETER 0x000E
652 #define PXE_STATCODE_INVALID_UNDI 0x000F
653 #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
654 #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
655 #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
656 #define PXE_STATCODE_NO_DATA 0x0013
657
658 typedef UINT16 PXE_IFNUM;
659
660 //
661 // This interface number must be passed to the S/W UNDI Start command.
662 //
663 #define PXE_IFNUM_START 0x0000
664
665 //
666 // This interface number is returned by the S/W UNDI Get State and
667 // Start commands if information in the CDB, CPB or DB is invalid.
668 //
669 #define PXE_IFNUM_INVALID 0x0000
670
671 typedef UINT16 PXE_CONTROL;
672
673 //
674 // Setting this flag directs the UNDI to queue this command for later
675 // execution if the UNDI is busy and it supports command queuing.
676 // If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error
677 // is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL
678 // error is returned.
679 //
680 #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
681
682 //
683 // These two bit values are used to determine if there are more UNDI
684 // CDB structures following this one. If the link bit is set, there
685 // must be a CDB structure following this one. Execution will start
686 // on the next CDB structure as soon as this one completes successfully.
687 // If an error is generated by this command, execution will stop.
688 //
689 #define PXE_CONTROL_LINK 0x0001
690 #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
691
692 typedef UINT8 PXE_FRAME_TYPE;
693
694 #define PXE_FRAME_TYPE_NONE 0x00
695 #define PXE_FRAME_TYPE_UNICAST 0x01
696 #define PXE_FRAME_TYPE_BROADCAST 0x02
697 #define PXE_FRAME_TYPE_MULTICAST 0x03
698 #define PXE_FRAME_TYPE_PROMISCUOUS 0x04
699
700 typedef UINT32 PXE_IPV4;
701
702 typedef UINT32 PXE_IPV6[4];
703 #define PXE_MAC_LENGTH 32
704
705 typedef UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];
706
707 typedef UINT8 PXE_IFTYPE;
708 typedef UINT16 PXE_MEDIA_PROTOCOL;
709
710 //
711 // This information is from the ARP section of RFC 1700.
712 //
713 // 1 Ethernet (10Mb) [JBP]
714 // 2 Experimental Ethernet (3Mb) [JBP]
715 // 3 Amateur Radio AX.25 [PXK]
716 // 4 Proteon ProNET Token Ring [JBP]
717 // 5 Chaos [GXP]
718 // 6 IEEE 802 Networks [JBP]
719 // 7 ARCNET [JBP]
720 // 8 Hyperchannel [JBP]
721 // 9 Lanstar [TU]
722 // 10 Autonet Short Address [MXB1]
723 // 11 LocalTalk [JKR1]
724 // 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]
725 // 13 Ultra link [RXD2]
726 // 14 SMDS [GXC1]
727 // 15 Frame Relay [AGM]
728 // 16 Asynchronous Transmission Mode (ATM) [JXB2]
729 // 17 HDLC [JBP]
730 // 18 Fibre Channel [Yakov Rekhter]
731 // 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]
732 // 20 Serial Line [JBP]
733 // 21 Asynchronous Transmission Mode (ATM) [MXB1]
734 //
735 // * Other names and brands may be claimed as the property of others.
736 //
737 #define PXE_IFTYPE_ETHERNET 0x01
738 #define PXE_IFTYPE_TOKENRING 0x04
739 #define PXE_IFTYPE_FIBRE_CHANNEL 0x12
740
741 typedef struct s_pxe_hw_undi {
742 UINT32 Signature; // PXE_ROMID_SIGNATURE
743 UINT8 Len; // sizeof(PXE_HW_UNDI)
744 UINT8 Fudge; // makes 8-bit cksum equal zero
745 UINT8 Rev; // PXE_ROMID_REV
746 UINT8 IFcnt; // physical connector count
747 UINT8 MajorVer; // PXE_ROMID_MAJORVER
748 UINT8 MinorVer; // PXE_ROMID_MINORVER
749 UINT16 reserved; // zero, not used
750 UINT32 Implementation; // implementation flags
751 // reserved // vendor use
752 // UINT32 Status; // status port
753 // UINT32 Command; // command port
754 // UINT64 CDBaddr; // CDB address port
755 //
756 } PXE_HW_UNDI;
757
758 //
759 // Status port bit definitions
760 //
761 //
762 // UNDI operation state
763 //
764 #define PXE_HWSTAT_STATE_MASK 0xC0000000
765 #define PXE_HWSTAT_BUSY 0xC0000000
766 #define PXE_HWSTAT_INITIALIZED 0x80000000
767 #define PXE_HWSTAT_STARTED 0x40000000
768 #define PXE_HWSTAT_STOPPED 0x00000000
769
770 //
771 // If set, last command failed
772 //
773 #define PXE_HWSTAT_COMMAND_FAILED 0x20000000
774
775 //
776 // If set, identifies enabled receive filters
777 //
778 #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
779 #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
780 #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
781 #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
782 #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
783
784 //
785 // If set, identifies enabled external interrupts
786 //
787 #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
788 #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
789 #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
790 #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
791
792 //
793 // If set, identifies pending interrupts
794 //
795 #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
796 #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
797 #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
798 #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
799
800 //
801 // Command port definitions
802 //
803 //
804 // If set, CDB identified in CDBaddr port is given to UNDI.
805 // If not set, other bits in this word will be processed.
806 //
807 #define PXE_HWCMD_ISSUE_COMMAND 0x80000000
808 #define PXE_HWCMD_INTS_AND_FILTS 0x00000000
809
810 //
811 // Use these to enable/disable receive filters.
812 //
813 #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
814 #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
815 #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
816 #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200
817 #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
818
819 //
820 // Use these to enable/disable external interrupts
821 //
822 #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
823 #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
824 #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
825 #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
826
827 //
828 // Use these to clear pending external interrupts
829 //
830 #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
831 #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
832 #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
833 #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
834
835 typedef struct s_pxe_sw_undi {
836 UINT32 Signature; // PXE_ROMID_SIGNATURE
837 UINT8 Len; // sizeof(PXE_SW_UNDI)
838 UINT8 Fudge; // makes 8-bit cksum zero
839 UINT8 Rev; // PXE_ROMID_REV
840 UINT8 IFcnt; // physical connector count
841 UINT8 MajorVer; // PXE_ROMID_MAJORVER
842 UINT8 MinorVer; // PXE_ROMID_MINORVER
843 UINT16 reserved1; // zero, not used
844 UINT32 Implementation; // Implementation flags
845 UINT64 EntryPoint; // API entry point
846 UINT8 reserved2[3]; // zero, not used
847 UINT8 BusCnt; // number of bustypes supported
848 UINT32 BusType[1]; // list of supported bustypes
849 } PXE_SW_UNDI;
850
851 typedef union u_pxe_undi {
852 PXE_HW_UNDI hw;
853 PXE_SW_UNDI sw;
854 } PXE_UNDI;
855
856 //
857 // Signature of !PXE structure
858 //
859 #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
860
861 //
862 // !PXE structure format revision
863 //
864 #define PXE_ROMID_REV 0x02
865
866 //
867 // UNDI command interface revision. These are the values that get sent
868 // in option 94 (Client Network Interface Identifier) in the DHCP Discover
869 // and PXE Boot Server Request packets.
870 //
871 #define PXE_ROMID_MAJORVER 0x03
872 #define PXE_ROMID_MINORVER 0x00
873 #define PXE_ROMID_MINORVER_31 0x10
874
875 //
876 // Implementation flags
877 //
878 #define PXE_ROMID_IMP_HW_UNDI 0x80000000
879 #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
880 #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
881 #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
882 #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
883 #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
884 #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
885 #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
886 #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
887 #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
888 #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
889 #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
890 #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
891 #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
892 #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
893 #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
894 #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
895 #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
896 #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
897 #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
898 #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
899 #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
900
901 typedef struct s_pxe_cdb {
902 PXE_OPCODE OpCode;
903 PXE_OPFLAGS OpFlags;
904 UINT16 CPBsize;
905 UINT16 DBsize;
906 UINT64 CPBaddr;
907 UINT64 DBaddr;
908 PXE_STATCODE StatCode;
909 PXE_STATFLAGS StatFlags;
910 UINT16 IFnum;
911 PXE_CONTROL Control;
912 } PXE_CDB;
913
914 typedef union u_pxe_ip_addr {
915 PXE_IPV6 IPv6;
916 PXE_IPV4 IPv4;
917 } PXE_IP_ADDR;
918
919 typedef union pxe_device {
920 //
921 // PCI and PC Card NICs are both identified using bus, device
922 // and function numbers. For PC Card, this may require PC
923 // Card services to be loaded in the BIOS or preboot
924 // environment.
925 //
926 struct {
927 //
928 // See S/W UNDI ROMID structure definition for PCI and
929 // PCC BusType definitions.
930 //
931 UINT32 BusType;
932
933 //
934 // Bus, device & function numbers that locate this device.
935 //
936 UINT16 Bus;
937 UINT8 Device;
938 UINT8 Function;
939 }
940 PCI, PCC;
941
942 //
943 // %%TBD - More information is needed about enumerating
944 // USB and 1394 devices.
945 //
946 struct {
947 UINT32 BusType;
948 UINT32 tdb;
949 }
950 USB, _1394;
951 } PXE_DEVICE;
952
953 //
954 // cpb and db definitions
955 //
956 #define MAX_PCI_CONFIG_LEN 64 // # of dwords
957 #define MAX_EEPROM_LEN 128 // #of dwords
958 #define MAX_XMIT_BUFFERS 32 // recycling Q length for xmit_done
959 #define MAX_MCAST_ADDRESS_CNT 8
960
961 typedef struct s_pxe_cpb_start {
962 //
963 // PXE_VOID Delay(UINTN microseconds);
964 //
965 // UNDI will never request a delay smaller than 10 microseconds
966 // and will always request delays in increments of 10 microseconds.
967 // The Delay() CallBack routine must delay between n and n + 10
968 // microseconds before returning control to the UNDI.
969 //
970 // This field cannot be set to zero.
971 //
972 UINT64 Delay;
973
974 //
975 // PXE_VOID Block(UINT32 enable);
976 //
977 // UNDI may need to block multi-threaded/multi-processor access to
978 // critical code sections when programming or accessing the network
979 // device. To this end, a blocking service is needed by the UNDI.
980 // When UNDI needs a block, it will call Block() passing a non-zero
981 // value. When UNDI no longer needs a block, it will call Block()
982 // with a zero value. When called, if the Block() is already enabled,
983 // do not return control to the UNDI until the previous Block() is
984 // disabled.
985 //
986 // This field cannot be set to zero.
987 //
988 UINT64 Block;
989
990 //
991 // PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);
992 //
993 // UNDI will pass the virtual address of a buffer and the virtual
994 // address of a 64-bit physical buffer. Convert the virtual address
995 // to a physical address and write the result to the physical address
996 // buffer. If virtual and physical addresses are the same, just
997 // copy the virtual address to the physical address buffer.
998 //
999 // This field can be set to zero if virtual and physical addresses
1000 // are equal.
1001 //
1002 UINT64 Virt2Phys;
1003 //
1004 // PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,
1005 // UINT64 buf_addr);
1006 //
1007 // UNDI will read or write the device io space using this call back
1008 // function. It passes the number of bytes as the len parameter and it
1009 // will be either 1,2,4 or 8.
1010 //
1011 // This field can not be set to zero.
1012 //
1013 UINT64 Mem_IO;
1014 } PXE_CPB_START;
1015
1016 typedef struct s_pxe_cpb_start_31 {
1017 //
1018 // PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);
1019 //
1020 // UNDI will never request a delay smaller than 10 microseconds
1021 // and will always request delays in increments of 10 microseconds.
1022 // The Delay() CallBack routine must delay between n and n + 10
1023 // microseconds before returning control to the UNDI.
1024 //
1025 // This field cannot be set to zero.
1026 //
1027 UINT64 Delay;
1028
1029 //
1030 // PXE_VOID Block(UINT64 unq_id, UINT32 enable);
1031 //
1032 // UNDI may need to block multi-threaded/multi-processor access to
1033 // critical code sections when programming or accessing the network
1034 // device. To this end, a blocking service is needed by the UNDI.
1035 // When UNDI needs a block, it will call Block() passing a non-zero
1036 // value. When UNDI no longer needs a block, it will call Block()
1037 // with a zero value. When called, if the Block() is already enabled,
1038 // do not return control to the UNDI until the previous Block() is
1039 // disabled.
1040 //
1041 // This field cannot be set to zero.
1042 //
1043 UINT64 Block;
1044
1045 //
1046 // PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);
1047 //
1048 // UNDI will pass the virtual address of a buffer and the virtual
1049 // address of a 64-bit physical buffer. Convert the virtual address
1050 // to a physical address and write the result to the physical address
1051 // buffer. If virtual and physical addresses are the same, just
1052 // copy the virtual address to the physical address buffer.
1053 //
1054 // This field can be set to zero if virtual and physical addresses
1055 // are equal.
1056 //
1057 UINT64 Virt2Phys;
1058 //
1059 // PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,
1060 // UINT64 buf_addr);
1061 //
1062 // UNDI will read or write the device io space using this call back
1063 // function. It passes the number of bytes as the len parameter and it
1064 // will be either 1,2,4 or 8.
1065 //
1066 // This field can not be set to zero.
1067 //
1068 UINT64 Mem_IO;
1069 //
1070 // PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1071 // UINT32 Direction, UINT64 mapped_addr);
1072 //
1073 // UNDI will pass the virtual address of a buffer, direction of the data
1074 // flow from/to the mapped buffer (the constants are defined below)
1075 // and a place holder (pointer) for the mapped address.
1076 // This call will Map the given address to a physical DMA address and write
1077 // the result to the mapped_addr pointer. If there is no need to
1078 // map the given address to a lower address (i.e. the given address is
1079 // associated with a physical address that is already compatible to be
1080 // used with the DMA, it converts the given virtual address to it's
1081 // physical address and write that in the mapped address pointer.
1082 //
1083 // This field can be set to zero if there is no mapping service available
1084 //
1085 UINT64 Map_Mem;
1086
1087 //
1088 // PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1089 // UINT32 Direction, UINT64 mapped_addr);
1090 //
1091 // UNDI will pass the virtual and mapped addresses of a buffer
1092 // This call will un map the given address
1093 //
1094 // This field can be set to zero if there is no unmapping service available
1095 //
1096 UINT64 UnMap_Mem;
1097
1098 //
1099 // PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,
1100 // UINT32 size, UINT32 Direction, UINT64 mapped_addr);
1101 //
1102 // UNDI will pass the virtual and mapped addresses of a buffer
1103 // This call will synchronize the contents of both the virtual and mapped
1104 // buffers for the given Direction.
1105 //
1106 // This field can be set to zero if there is no service available
1107 //
1108 UINT64 Sync_Mem;
1109
1110 //
1111 // protocol driver can provide anything for this Unique_ID, UNDI remembers
1112 // that as just a 64bit value assocaited to the interface specified by
1113 // the ifnum and gives it back as a parameter to all the call-back routines
1114 // when calling for that interface!
1115 //
1116 UINT64 Unique_ID;
1117 //
1118 } PXE_CPB_START_31;
1119
1120 #define TO_AND_FROM_DEVICE 0
1121 #define FROM_DEVICE 1
1122 #define TO_DEVICE 2
1123
1124 #define PXE_DELAY_MILLISECOND 1000
1125 #define PXE_DELAY_SECOND 1000000
1126 #define PXE_IO_READ 0
1127 #define PXE_IO_WRITE 1
1128 #define PXE_MEM_READ 2
1129 #define PXE_MEM_WRITE 4
1130
1131 typedef struct s_pxe_db_get_init_info {
1132 //
1133 // Minimum length of locked memory buffer that must be given to
1134 // the Initialize command. Giving UNDI more memory will generally
1135 // give better performance.
1136 //
1137 // If MemoryRequired is zero, the UNDI does not need and will not
1138 // use system memory to receive and transmit packets.
1139 //
1140 UINT32 MemoryRequired;
1141
1142 //
1143 // Maximum frame data length for Tx/Rx excluding the media header.
1144 //
1145 UINT32 FrameDataLen;
1146
1147 //
1148 // Supported link speeds are in units of mega bits. Common ethernet
1149 // values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero
1150 // filled.
1151 //
1152 UINT32 LinkSpeeds[4];
1153
1154 //
1155 // Number of non-volatile storage items.
1156 //
1157 UINT32 NvCount;
1158
1159 //
1160 // Width of non-volatile storage item in bytes. 0, 1, 2 or 4
1161 //
1162 UINT16 NvWidth;
1163
1164 //
1165 // Media header length. This is the typical media header length for
1166 // this UNDI. This information is needed when allocating receive
1167 // and transmit buffers.
1168 //
1169 UINT16 MediaHeaderLen;
1170
1171 //
1172 // Number of bytes in the NIC hardware (MAC) address.
1173 //
1174 UINT16 HWaddrLen;
1175
1176 //
1177 // Maximum number of multicast MAC addresses in the multicast
1178 // MAC address filter list.
1179 //
1180 UINT16 MCastFilterCnt;
1181
1182 //
1183 // Default number and size of transmit and receive buffers that will
1184 // be allocated by the UNDI. If MemoryRequired is non-zero, this
1185 // allocation will come out of the memory buffer given to the Initialize
1186 // command. If MemoryRequired is zero, this allocation will come out of
1187 // memory on the NIC.
1188 //
1189 UINT16 TxBufCnt;
1190 UINT16 TxBufSize;
1191 UINT16 RxBufCnt;
1192 UINT16 RxBufSize;
1193
1194 //
1195 // Hardware interface types defined in the Assigned Numbers RFC
1196 // and used in DHCP and ARP packets.
1197 // See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.
1198 //
1199 UINT8 IFtype;
1200
1201 //
1202 // Supported duplex. See PXE_DUPLEX_xxxxx #defines below.
1203 //
1204 UINT8 Duplex;
1205
1206 //
1207 // Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.
1208 //
1209 UINT8 LoopBack;
1210 } PXE_DB_GET_INIT_INFO;
1211
1212 #define PXE_MAX_TXRX_UNIT_ETHER 1500
1213
1214 #define PXE_HWADDR_LEN_ETHER 0x0006
1215 #define PXE_MAC_HEADER_LEN_ETHER 0x000E
1216
1217 #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
1218 #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
1219
1220 #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
1221 #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
1222
1223 typedef struct s_pxe_pci_config_info {
1224 //
1225 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1226 // For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
1227 //
1228 UINT32 BusType;
1229
1230 //
1231 // This identifies the PCI network device that this UNDI interface
1232 // is bound to.
1233 //
1234 UINT16 Bus;
1235 UINT8 Device;
1236 UINT8 Function;
1237
1238 //
1239 // This is a copy of the PCI configuration space for this
1240 // network device.
1241 //
1242 union {
1243 UINT8 Byte[256];
1244 UINT16 Word[128];
1245 UINT32 Dword[64];
1246 } Config;
1247 } PXE_PCI_CONFIG_INFO;
1248
1249 typedef struct s_pxe_pcc_config_info {
1250 //
1251 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1252 // For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.
1253 //
1254 UINT32 BusType;
1255
1256 //
1257 // This identifies the PCC network device that this UNDI interface
1258 // is bound to.
1259 //
1260 UINT16 Bus;
1261 UINT8 Device;
1262 UINT8 Function;
1263
1264 //
1265 // This is a copy of the PCC configuration space for this
1266 // network device.
1267 //
1268 union {
1269 UINT8 Byte[256];
1270 UINT16 Word[128];
1271 UINT32 Dword[64];
1272 } Config;
1273 } PXE_PCC_CONFIG_INFO;
1274
1275 typedef struct s_pxe_usb_config_info {
1276 UINT32 BusType;
1277 //
1278 // %%TBD What should we return here...
1279 //
1280 } PXE_USB_CONFIG_INFO;
1281
1282 typedef struct s_pxe_1394_config_info {
1283 UINT32 BusType;
1284 //
1285 // %%TBD What should we return here...
1286 //
1287 } PXE_1394_CONFIG_INFO;
1288
1289 typedef union u_pxe_db_get_config_info {
1290 PXE_PCI_CONFIG_INFO pci;
1291 PXE_PCC_CONFIG_INFO pcc;
1292 PXE_USB_CONFIG_INFO usb;
1293 PXE_1394_CONFIG_INFO _1394;
1294 } PXE_DB_GET_CONFIG_INFO;
1295
1296 typedef struct s_pxe_cpb_initialize {
1297 //
1298 // Address of first (lowest) byte of the memory buffer. This buffer must
1299 // be in contiguous physical memory and cannot be swapped out. The UNDI
1300 // will be using this for transmit and receive buffering.
1301 //
1302 UINT64 MemoryAddr;
1303
1304 //
1305 // MemoryLength must be greater than or equal to MemoryRequired
1306 // returned by the Get Init Info command.
1307 //
1308 UINT32 MemoryLength;
1309
1310 //
1311 // Desired link speed in Mbit/sec. Common ethernet values are 10, 100
1312 // and 1000. Setting a value of zero will auto-detect and/or use the
1313 // default link speed (operation depends on UNDI/NIC functionality).
1314 //
1315 UINT32 LinkSpeed;
1316
1317 //
1318 // Suggested number and size of receive and transmit buffers to
1319 // allocate. If MemoryAddr and MemoryLength are non-zero, this
1320 // allocation comes out of the supplied memory buffer. If MemoryAddr
1321 // and MemoryLength are zero, this allocation comes out of memory
1322 // on the NIC.
1323 //
1324 // If these fields are set to zero, the UNDI will allocate buffer
1325 // counts and sizes as it sees fit.
1326 //
1327 UINT16 TxBufCnt;
1328 UINT16 TxBufSize;
1329 UINT16 RxBufCnt;
1330 UINT16 RxBufSize;
1331
1332 //
1333 // The following configuration parameters are optional and must be zero
1334 // to use the default values.
1335 //
1336 UINT8 Duplex;
1337
1338 UINT8 LoopBack;
1339 } PXE_CPB_INITIALIZE;
1340
1341 #define PXE_DUPLEX_DEFAULT 0x00
1342 #define PXE_FORCE_FULL_DUPLEX 0x01
1343 #define PXE_ENABLE_FULL_DUPLEX 0x02
1344 #define PXE_FORCE_HALF_DUPLEX 0x04
1345 #define PXE_DISABLE_FULL_DUPLEX 0x08
1346
1347 #define LOOPBACK_NORMAL 0
1348 #define LOOPBACK_INTERNAL 1
1349 #define LOOPBACK_EXTERNAL 2
1350
1351 typedef struct s_pxe_db_initialize {
1352 //
1353 // Actual amount of memory used from the supplied memory buffer. This
1354 // may be less that the amount of memory suppllied and may be zero if
1355 // the UNDI and network device do not use external memory buffers.
1356 //
1357 // Memory used by the UNDI and network device is allocated from the
1358 // lowest memory buffer address.
1359 //
1360 UINT32 MemoryUsed;
1361
1362 //
1363 // Actual number and size of receive and transmit buffers that were
1364 // allocated.
1365 //
1366 UINT16 TxBufCnt;
1367 UINT16 TxBufSize;
1368 UINT16 RxBufCnt;
1369 UINT16 RxBufSize;
1370 } PXE_DB_INITIALIZE;
1371
1372 typedef struct s_pxe_cpb_receive_filters {
1373 //
1374 // List of multicast MAC addresses. This list, if present, will
1375 // replace the existing multicast MAC address filter list.
1376 //
1377 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1378 } PXE_CPB_RECEIVE_FILTERS;
1379
1380 typedef struct s_pxe_db_receive_filters {
1381 //
1382 // Filtered multicast MAC address list.
1383 //
1384 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1385 } PXE_DB_RECEIVE_FILTERS;
1386
1387 typedef struct s_pxe_cpb_station_address {
1388 //
1389 // If supplied and supported, the current station MAC address
1390 // will be changed.
1391 //
1392 PXE_MAC_ADDR StationAddr;
1393 } PXE_CPB_STATION_ADDRESS;
1394
1395 typedef struct s_pxe_dpb_station_address {
1396 //
1397 // Current station MAC address.
1398 //
1399 PXE_MAC_ADDR StationAddr;
1400
1401 //
1402 // Station broadcast MAC address.
1403 //
1404 PXE_MAC_ADDR BroadcastAddr;
1405
1406 //
1407 // Permanent station MAC address.
1408 //
1409 PXE_MAC_ADDR PermanentAddr;
1410 } PXE_DB_STATION_ADDRESS;
1411
1412 typedef struct s_pxe_db_statistics {
1413 //
1414 // Bit field identifying what statistic data is collected by the
1415 // UNDI/NIC.
1416 // If bit 0x00 is set, Data[0x00] is collected.
1417 // If bit 0x01 is set, Data[0x01] is collected.
1418 // If bit 0x20 is set, Data[0x20] is collected.
1419 // If bit 0x21 is set, Data[0x21] is collected.
1420 // Etc.
1421 //
1422 UINT64 Supported;
1423
1424 //
1425 // Statistic data.
1426 //
1427 UINT64 Data[64];
1428 } PXE_DB_STATISTICS;
1429
1430 //
1431 // Total number of frames received. Includes frames with errors and
1432 // dropped frames.
1433 //
1434 #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
1435
1436 //
1437 // Number of valid frames received and copied into receive buffers.
1438 //
1439 #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
1440
1441 //
1442 // Number of frames below the minimum length for the media.
1443 // This would be <64 for ethernet.
1444 //
1445 #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
1446
1447 //
1448 // Number of frames longer than the maxminum length for the
1449 // media. This would be >1500 for ethernet.
1450 //
1451 #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
1452
1453 //
1454 // Valid frames that were dropped because receive buffers were full.
1455 //
1456 #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
1457
1458 //
1459 // Number of valid unicast frames received and not dropped.
1460 //
1461 #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
1462
1463 //
1464 // Number of valid broadcast frames received and not dropped.
1465 //
1466 #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
1467
1468 //
1469 // Number of valid mutlicast frames received and not dropped.
1470 //
1471 #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
1472
1473 //
1474 // Number of frames w/ CRC or alignment errors.
1475 //
1476 #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
1477
1478 //
1479 // Total number of bytes received. Includes frames with errors
1480 // and dropped frames.
1481 //
1482 #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
1483
1484 //
1485 // Transmit statistics.
1486 //
1487 #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
1488 #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
1489 #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
1490 #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
1491 #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
1492 #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
1493 #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
1494 #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
1495 #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
1496 #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
1497
1498 //
1499 // Number of collisions detection on this subnet.
1500 //
1501 #define PXE_STATISTICS_COLLISIONS 0x14
1502
1503 //
1504 // Number of frames destined for unsupported protocol.
1505 //
1506 #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
1507
1508 typedef struct s_pxe_cpb_mcast_ip_to_mac {
1509 //
1510 // Multicast IP address to be converted to multicast MAC address.
1511 //
1512 PXE_IP_ADDR IP;
1513 } PXE_CPB_MCAST_IP_TO_MAC;
1514
1515 typedef struct s_pxe_db_mcast_ip_to_mac {
1516 //
1517 // Multicast MAC address.
1518 //
1519 PXE_MAC_ADDR MAC;
1520 } PXE_DB_MCAST_IP_TO_MAC;
1521
1522 typedef struct s_pxe_cpb_nvdata_sparse {
1523 //
1524 // NvData item list. Only items in this list will be updated.
1525 //
1526 struct {
1527 //
1528 // Non-volatile storage address to be changed.
1529 //
1530 UINT32 Addr;
1531
1532 //
1533 // Data item to write into above storage address.
1534 //
1535 union {
1536 UINT8 Byte;
1537 UINT16 Word;
1538 UINT32 Dword;
1539 } Data;
1540 } Item[MAX_EEPROM_LEN];
1541 }
1542 PXE_CPB_NVDATA_SPARSE;
1543
1544 //
1545 // When using bulk update, the size of the CPB structure must be
1546 // the same size as the non-volatile NIC storage.
1547 //
1548 typedef union u_pxe_cpb_nvdata_bulk {
1549 //
1550 // Array of byte-wide data items.
1551 //
1552 UINT8 Byte[MAX_EEPROM_LEN << 2];
1553
1554 //
1555 // Array of word-wide data items.
1556 //
1557 UINT16 Word[MAX_EEPROM_LEN << 1];
1558
1559 //
1560 // Array of dword-wide data items.
1561 //
1562 UINT32 Dword[MAX_EEPROM_LEN];
1563 } PXE_CPB_NVDATA_BULK;
1564
1565 typedef struct s_pxe_db_nvdata {
1566 //
1567 // Arrays of data items from non-volatile storage.
1568 //
1569 union {
1570 //
1571 // Array of byte-wide data items.
1572 //
1573 UINT8 Byte[MAX_EEPROM_LEN << 2];
1574
1575 //
1576 // Array of word-wide data items.
1577 //
1578 UINT16 Word[MAX_EEPROM_LEN << 1];
1579
1580 //
1581 // Array of dword-wide data items.
1582 //
1583 UINT32 Dword[MAX_EEPROM_LEN];
1584 } Data;
1585 } PXE_DB_NVDATA;
1586
1587 typedef struct s_pxe_db_get_status {
1588 //
1589 // Length of next receive frame (header + data). If this is zero,
1590 // there is no next receive frame available.
1591 //
1592 UINT32 RxFrameLen;
1593
1594 //
1595 // Reserved, set to zero.
1596 //
1597 UINT32 reserved;
1598
1599 //
1600 // Addresses of transmitted buffers that need to be recycled.
1601 //
1602 UINT64 TxBuffer[MAX_XMIT_BUFFERS];
1603 } PXE_DB_GET_STATUS;
1604
1605 typedef struct s_pxe_cpb_fill_header {
1606 //
1607 // Source and destination MAC addresses. These will be copied into
1608 // the media header without doing byte swapping.
1609 //
1610 PXE_MAC_ADDR SrcAddr;
1611 PXE_MAC_ADDR DestAddr;
1612
1613 //
1614 // Address of first byte of media header. The first byte of packet data
1615 // follows the last byte of the media header.
1616 //
1617 UINT64 MediaHeader;
1618
1619 //
1620 // Length of packet data in bytes (not including the media header).
1621 //
1622 UINT32 PacketLen;
1623
1624 //
1625 // Protocol type. This will be copied into the media header without
1626 // doing byte swapping. Protocol type numbers can be obtained from
1627 // the Assigned Numbers RFC 1700.
1628 //
1629 UINT16 Protocol;
1630
1631 //
1632 // Length of the media header in bytes.
1633 //
1634 UINT16 MediaHeaderLen;
1635 } PXE_CPB_FILL_HEADER;
1636
1637 #define PXE_PROTOCOL_ETHERNET_IP 0x0800
1638 #define PXE_PROTOCOL_ETHERNET_ARP 0x0806
1639 #define MAX_XMIT_FRAGMENTS 16
1640
1641 typedef struct s_pxe_cpb_fill_header_fragmented {
1642 //
1643 // Source and destination MAC addresses. These will be copied into
1644 // the media header without doing byte swapping.
1645 //
1646 PXE_MAC_ADDR SrcAddr;
1647 PXE_MAC_ADDR DestAddr;
1648
1649 //
1650 // Length of packet data in bytes (not including the media header).
1651 //
1652 UINT32 PacketLen;
1653
1654 //
1655 // Protocol type. This will be copied into the media header without
1656 // doing byte swapping. Protocol type numbers can be obtained from
1657 // the Assigned Numbers RFC 1700.
1658 //
1659 PXE_MEDIA_PROTOCOL Protocol;
1660
1661 //
1662 // Length of the media header in bytes.
1663 //
1664 UINT16 MediaHeaderLen;
1665
1666 //
1667 // Number of packet fragment descriptors.
1668 //
1669 UINT16 FragCnt;
1670
1671 //
1672 // Reserved, must be set to zero.
1673 //
1674 UINT16 reserved;
1675
1676 //
1677 // Array of packet fragment descriptors. The first byte of the media
1678 // header is the first byte of the first fragment.
1679 //
1680 struct {
1681 //
1682 // Address of this packet fragment.
1683 //
1684 UINT64 FragAddr;
1685
1686 //
1687 // Length of this packet fragment.
1688 //
1689 UINT32 FragLen;
1690
1691 //
1692 // Reserved, must be set to zero.
1693 //
1694 UINT32 reserved;
1695 } FragDesc[MAX_XMIT_FRAGMENTS];
1696 }
1697 PXE_CPB_FILL_HEADER_FRAGMENTED;
1698
1699 typedef struct s_pxe_cpb_transmit {
1700 //
1701 // Address of first byte of frame buffer. This is also the first byte
1702 // of the media header.
1703 //
1704 UINT64 FrameAddr;
1705
1706 //
1707 // Length of the data portion of the frame buffer in bytes. Do not
1708 // include the length of the media header.
1709 //
1710 UINT32 DataLen;
1711
1712 //
1713 // Length of the media header in bytes.
1714 //
1715 UINT16 MediaheaderLen;
1716
1717 //
1718 // Reserved, must be zero.
1719 //
1720 UINT16 reserved;
1721 } PXE_CPB_TRANSMIT;
1722
1723 typedef struct s_pxe_cpb_transmit_fragments {
1724 //
1725 // Length of packet data in bytes (not including the media header).
1726 //
1727 UINT32 FrameLen;
1728
1729 //
1730 // Length of the media header in bytes.
1731 //
1732 UINT16 MediaheaderLen;
1733
1734 //
1735 // Number of packet fragment descriptors.
1736 //
1737 UINT16 FragCnt;
1738
1739 //
1740 // Array of frame fragment descriptors. The first byte of the first
1741 // fragment is also the first byte of the media header.
1742 //
1743 struct {
1744 //
1745 // Address of this frame fragment.
1746 //
1747 UINT64 FragAddr;
1748
1749 //
1750 // Length of this frame fragment.
1751 //
1752 UINT32 FragLen;
1753
1754 //
1755 // Reserved, must be set to zero.
1756 //
1757 UINT32 reserved;
1758 } FragDesc[MAX_XMIT_FRAGMENTS];
1759 }
1760 PXE_CPB_TRANSMIT_FRAGMENTS;
1761
1762 typedef struct s_pxe_cpb_receive {
1763 //
1764 // Address of first byte of receive buffer. This is also the first byte
1765 // of the frame header.
1766 //
1767 UINT64 BufferAddr;
1768
1769 //
1770 // Length of receive buffer. This must be large enough to hold the
1771 // received frame (media header + data). If the length of smaller than
1772 // the received frame, data will be lost.
1773 //
1774 UINT32 BufferLen;
1775
1776 //
1777 // Reserved, must be set to zero.
1778 //
1779 UINT32 reserved;
1780 } PXE_CPB_RECEIVE;
1781
1782 typedef struct s_pxe_db_receive {
1783 //
1784 // Source and destination MAC addresses from media header.
1785 //
1786 PXE_MAC_ADDR SrcAddr;
1787 PXE_MAC_ADDR DestAddr;
1788
1789 //
1790 // Length of received frame. May be larger than receive buffer size.
1791 // The receive buffer will not be overwritten. This is how to tell
1792 // if data was lost because the receive buffer was too small.
1793 //
1794 UINT32 FrameLen;
1795
1796 //
1797 // Protocol type from media header.
1798 //
1799 PXE_MEDIA_PROTOCOL Protocol;
1800
1801 //
1802 // Length of media header in received frame.
1803 //
1804 UINT16 MediaHeaderLen;
1805
1806 //
1807 // Type of receive frame.
1808 //
1809 PXE_FRAME_TYPE Type;
1810
1811 //
1812 // Reserved, must be zero.
1813 //
1814 UINT8 reserved[7];
1815
1816 } PXE_DB_RECEIVE;
1817
1818 #pragma pack()
1819
1820 #endif
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