EdkCompatibilityPkg/Foundation/Library/Dxe/Include/EfiRegTableLib.h

   1 /*++
   2
   3 Copyright (c) 2004, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14   EfiRegTableLib.h
  15
  16 Abstract:
  17
  18   Definitions and macros for building register tables for chipset
  19   initialization..
  20
  21   Components linking this lib must include CpuIo, PciRootBridgeIo, and
  22   BootScriptSave protocols in their DPX.
  23
  24 Revision History:
  25
  26 --*/
  27
  28 #ifndef EFI_REG_TABLE_H
  29 #define EFI_REG_TABLE_H
  30
  31 #include "Tiano.h"
  32 #include "EfiScriptLib.h"
  33 #include EFI_PROTOCOL_CONSUMER (CpuIo)
  34 #include EFI_PROTOCOL_CONSUMER (PciRootBridgeIo)
  35
  36 //
  37 // RegTable OpCodes are encoded as follows:
  38 //
  39 //  |31----------------------------16|15---------8|7-------0|
  40 //                                 \             \         \
  41 //                                 \             \         \
  42 //  31:16 defined by Base OpCode---+             \         \
  43 //                                Opcode Flags---+         \
  44 //                                           Base OpCode---+
  45 //
  46 #define OPCODE_BASE(OpCode)       ((UINT8)((OpCode) & 0xFF))
  47 #define OPCODE_FLAGS(OpCode)      ((UINT8)(((OpCode) >> 8) & 0xFF))
  48 #define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))
  49
  50 //
  51 // RegTable Base OpCodes
  52 //
  53 #define OP_TERMINATE_TABLE                0
  54 #define OP_MEM_WRITE                      1
  55 #define OP_MEM_READ_MODIFY_WRITE          2
  56 #define OP_IO_WRITE                       3
  57 #define OP_IO_READ_MODIFY_WRITE           4
  58 #define OP_PCI_WRITE                      5
  59 #define OP_PCI_READ_MODIFY_WRITE          6
  60 #define OP_STALL                          7
  61
  62 //
  63 // RegTable OpCode Flags
  64 //
  65 #define OPCODE_FLAG_S3SAVE                1
  66
  67
  68 #define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }
  69
  70
  71 //
  72 // REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode
  73 // as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values
  74 //
  75 typedef struct {
  76   UINT32                                OpCode;
  77   UINT32                                PciAddress;
  78   UINT32                                Data;
  79 } EFI_REG_TABLE_PCI_WRITE;
  80
  81 #define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag)                    \
  82   {                                                                           \
  83     (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)),              \
  84     (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))),                  \
  85     (UINT32) (Data),                                                          \
  86     (UINT32) (0)                                                              \
  87   }
  88
  89 typedef struct {
  90   UINT32                                OpCode;
  91   UINT32                                PciAddress;
  92   UINT32                                OrMask;
  93   UINT32                                AndMask;
  94 } EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;
  95
  96 #define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag)  \
  97   {                                                                           \
  98     (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)),  \
  99     (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))),                  \
 100     (UINT32) (OrMask),                                                        \
 101     (UINT32) (AndMask)                                                        \
 102   }
 103
 104 typedef struct {
 105   UINT32                                OpCode;
 106   UINT32                                MemAddress;
 107   UINT32                                OrMask;
 108   UINT32                                AndMask;
 109 } EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;
 110
 111 #define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag)  \
 112   {                                                                           \
 113     (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)),  \
 114     (UINT32) (Address),                  \
 115     (UINT32) (OrMask),                                                        \
 116     (UINT32) (AndMask)                                                        \
 117   }
 118
 119 typedef struct {
 120   UINT32                                OpCode;
 121   UINT32                                Field2;
 122   UINT32                                Field3;
 123   UINT32                                Field4;
 124 } EFI_REG_TABLE_GENERIC;
 125
 126 typedef union {
 127   EFI_REG_TABLE_GENERIC                 Generic;
 128   EFI_REG_TABLE_PCI_WRITE               PciWrite;
 129   EFI_REG_TABLE_PCI_READ_MODIFY_WRITE   PciReadModifyWrite;
 130   EFI_REG_TABLE_MEM_READ_MODIFY_WRITE   MemReadModifyWrite;
 131 } EFI_REG_TABLE;
 132
 133 VOID
 134 ProcessRegTablePci (
 135   EFI_REG_TABLE                   * RegTableEntry,
 136   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,
 137   EFI_CPU_IO_PROTOCOL             * CpuIo
 138   )
 139 /*++
 140
 141 Routine Description:
 142   Processes register table assuming which may contain PCI, IO, MEM, and STALL
 143   entries.
 144
 145   No parameter checking is done so the caller must be careful about omitting
 146   values for PciRootBridgeIo or CpuIo parameters.  If the regtable does
 147   not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
 148   NULL).  If the regtable does not contain any IO or Mem entries, it is safe to
 149   omit the CpuIo (supply NULL).
 150
 151   The RegTableEntry parameter is not checked, but is required.
 152
 153   gBS is assumed to have been defined and is used when processing stalls.
 154
 155   The function processes each entry sequentially until an OP_TERMINATE_TABLE
 156   entry is encountered.
 157
 158 Arguments:
 159   RegTableEntry - A pointer to the register table to process
 160
 161   PciRootBridgeIo - A pointer to the instance of PciRootBridgeIo that is used
 162                   when processing PCI table entries
 163
 164   CpuIo - A pointer to the instance of CpuIo that is used when processing IO and
 165                   MEM table entries
 166
 167 Returns:
 168   Nothing.
 169
 170 --*/
 171 ;
 172
 173 VOID
 174 ProcessRegTableCpu (
 175   EFI_REG_TABLE                   * RegTableEntry,
 176   EFI_CPU_IO_PROTOCOL             * CpuIo
 177   )
 178 /*++
 179
 180 Routine Description:
 181   Processes register table assuming which may contain IO, MEM, and STALL
 182   entries, but must NOT contain any PCI entries.  Any PCI entries cause an
 183   ASSERT in a DEBUG build and are skipped in a free build.
 184
 185   No parameter checking is done.  Both RegTableEntry and CpuIo parameters are
 186   required.
 187
 188   gBS is assumed to have been defined and is used when processing stalls.
 189
 190   The function processes each entry sequentially until an OP_TERMINATE_TABLE
 191   entry is encountered.
 192
 193 Arguments:
 194   RegTableEntry - A pointer to the register table to process
 195
 196   CpuIo - A pointer to the instance of CpuIo that is used when processing IO and
 197                   MEM table entries
 198
 199 Returns:
 200   Nothing.
 201
 202 --*/
 203 ;
 204
 205 #endif