EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/EdkIIGlueCacheMaintenanceLib.h

   1 /*++
   2
   3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
   4 This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12
  13 Module Name:
  14
  15   EdkIIGlueCacheMaintenanceLib.h
  16
  17 Abstract:
  18
  19   Cache Maintenance Functions
  20
  21 --*/
  22
  23 #ifndef __EDKII_GLUE_CACHE_MAINTENANCE_LIB_H__
  24 #define __EDKII_GLUE_CACHE_MAINTENANCE_LIB_H__
  25
  26
  27 #define InvalidateInstructionCache() GlueInvalidateInstructionCache()
  28
  29
  30 /**
  31   Invalidates the entire instruction cache in cache coherency domain of the
  32   calling CPU.
  33
  34   Invalidates the entire instruction cache in cache coherency domain of the
  35   calling CPU.
  36
  37 **/
  38 VOID
  39 EFIAPI
  40 GlueInvalidateInstructionCache (
  41   VOID
  42   );
  43
  44 /**
  45   Invalidates a range of instruction cache lines in the cache coherency domain
  46   of the calling CPU.
  47
  48   Invalidates the instruction cache lines specified by Address and Length. If
  49   Address is not aligned on a cache line boundary, then entire instruction
  50   cache line containing Address is invalidated. If Address + Length is not
  51   aligned on a cache line boundary, then the entire instruction cache line
  52   containing Address + Length -1 is invalidated. This function may choose to
  53   invalidate the entire instruction cache if that is more efficient than
  54   invalidating the specified range. If Length is 0, the no instruction cache
  55   lines are invalidated. Address is returned.
  56
  57   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  58
  59   @param  Address The base address of the instruction cache lines to
  60                   invalidate. If the CPU is in a physical addressing mode, then
  61                   Address is a physical address. If the CPU is in a virtual
  62                   addressing mode, then Address is a virtual address.
  63
  64   @param  Length  The number of bytes to invalidate from the instruction cache.
  65
  66   @return Address
  67
  68 **/
  69 VOID *
  70 EFIAPI
  71 InvalidateInstructionCacheRange (
  72   IN      VOID                      *Address,
  73   IN      UINTN                     Length
  74   );
  75
  76 /**
  77   Writes Back and Invalidates the entire data cache in cache coherency domain
  78   of the calling CPU.
  79
  80   Writes Back and Invalidates the entire data cache in cache coherency domain
  81   of the calling CPU. This function guarantees that all dirty cache lines are
  82   written back to system memory, and also invalidates all the data cache lines
  83   in the cache coherency domain of the calling CPU.
  84
  85 **/
  86 VOID
  87 EFIAPI
  88 WriteBackInvalidateDataCache (
  89   VOID
  90   );
  91
  92 /**
  93   Writes Back and Invalidates a range of data cache lines in the cache
  94   coherency domain of the calling CPU.
  95
  96   Writes Back and Invalidate the data cache lines specified by Address and
  97   Length. If Address is not aligned on a cache line boundary, then entire data
  98   cache line containing Address is written back and invalidated. If Address +
  99   Length is not aligned on a cache line boundary, then the entire data cache
 100   line containing Address + Length -1 is written back and invalidated. This
 101   function may choose to write back and invalidate the entire data cache if
 102   that is more efficient than writing back and invalidating the specified
 103   range. If Length is 0, the no data cache lines are written back and
 104   invalidated. Address is returned.
 105
 106   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 107
 108   @param  Address The base address of the data cache lines to write back and
 109                   invalidate. If the CPU is in a physical addressing mode, then
 110                   Address is a physical address. If the CPU is in a virtual
 111                   addressing mode, then Address is a virtual address.
 112   @param  Length  The number of bytes to write back and invalidate from the
 113                   data cache.
 114
 115   @return Address
 116
 117 **/
 118 VOID *
 119 EFIAPI
 120 WriteBackInvalidateDataCacheRange (
 121   IN      VOID                      *Address,
 122   IN      UINTN                     Length
 123   );
 124
 125 /**
 126   Writes Back the entire data cache in cache coherency domain of the calling
 127   CPU.
 128
 129   Writes Back the entire data cache in cache coherency domain of the calling
 130   CPU. This function guarantees that all dirty cache lines are written back to
 131   system memory. This function may also invalidate all the data cache lines in
 132   the cache coherency domain of the calling CPU.
 133
 134 **/
 135 VOID
 136 EFIAPI
 137 WriteBackDataCache (
 138   VOID
 139   );
 140
 141 /**
 142   Writes Back a range of data cache lines in the cache coherency domain of the
 143   calling CPU.
 144
 145   Writes Back the data cache lines specified by Address and Length. If Address
 146   is not aligned on a cache line boundary, then entire data cache line
 147   containing Address is written back. If Address + Length is not aligned on a
 148   cache line boundary, then the entire data cache line containing Address +
 149   Length -1 is written back. This function may choose to write back the entire
 150   data cache if that is more efficient than writing back the specified range.
 151   If Length is 0, the no data cache lines are written back. This function may
 152   also invalidate all the data cache lines in the specified range of the cache
 153   coherency domain of the calling CPU. Address is returned.
 154
 155   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 156
 157   @param  Address The base address of the data cache lines to write back. If
 158                   the CPU is in a physical addressing mode, then Address is a
 159                   physical address. If the CPU is in a virtual addressing
 160                   mode, then Address is a virtual address.
 161   @param  Length  The number of bytes to write back from the data cache.
 162
 163   @return Address
 164
 165 **/
 166 VOID *
 167 EFIAPI
 168 WriteBackDataCacheRange (
 169   IN      VOID                      *Address,
 170   IN      UINTN                     Length
 171   );
 172
 173 /**
 174   Invalidates the entire data cache in cache coherency domain of the calling
 175   CPU.
 176
 177   Invalidates the entire data cache in cache coherency domain of the calling
 178   CPU. This function must be used with care because dirty cache lines are not
 179   written back to system memory. It is typically used for cache diagnostics. If
 180   the CPU does not support invalidation of the entire data cache, then a write
 181   back and invalidate operation should be performed on the entire data cache.
 182
 183 **/
 184 VOID
 185 EFIAPI
 186 InvalidateDataCache (
 187   VOID
 188   );
 189
 190 /**
 191   Invalidates a range of data cache lines in the cache coherency domain of the
 192   calling CPU.
 193
 194   Invalidates the data cache lines specified by Address and Length. If Address
 195   is not aligned on a cache line boundary, then entire data cache line
 196   containing Address is invalidated. If Address + Length is not aligned on a
 197   cache line boundary, then the entire data cache line containing Address +
 198   Length -1 is invalidated. This function must never invalidate any cache lines
 199   outside the specified range. If Length is 0, the no data cache lines are
 200   invalidated. Address is returned. This function must be used with care
 201   because dirty cache lines are not written back to system memory. It is
 202   typically used for cache diagnostics. If the CPU does not support
 203   invalidation of a data cache range, then a write back and invalidate
 204   operation should be performed on the data cache range.
 205
 206   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 207
 208   @param  Address The base address of the data cache lines to invalidate. If
 209                   the CPU is in a physical addressing mode, then Address is a
 210                   physical address. If the CPU is in a virtual addressing mode,
 211                   then Address is a virtual address.
 212   @param  Length  The number of bytes to invalidate from the data cache.
 213
 214   @return Address
 215
 216 **/
 217 VOID *
 218 EFIAPI
 219 InvalidateDataCacheRange (
 220   IN      VOID                      *Address,
 221   IN      UINTN                     Length
 222   );
 223
 224 #endif