EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/EdkIIGluePciLib.h

   1 /*++
   2
   3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
   4 This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12
  13 Module Name:
  14
  15   EdkIIGluePciLib.h
  16
  17 Abstract:
  18
  19   Public header file for Pci Lib
  20
  21 --*/
  22
  23 #ifndef __EDKII_GLUE_PCI_LIB_H__
  24 #define __EDKII_GLUE_PCI_LIB_H__
  25
  26 /**
  27   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  28   address that can be passed to the PCI Library functions.
  29
  30   @param  Bus       PCI Bus number. Range 0..255.
  31   @param  Device    PCI Device number. Range 0..31.
  32   @param  Function  PCI Function number. Range 0..7.
  33   @param  Register  PCI Register number. Range 0..255 for PCI. Range 0..4095
  34                     for PCI Express.
  35
  36   @return The encoded PCI address.
  37
  38 **/
  39 #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset)   \
  40   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  41
  42 /**
  43   Reads an 8-bit PCI configuration register.
  44
  45   Reads and returns the 8-bit PCI configuration register specified by Address.
  46   This function must guarantee that all PCI read and write operations are
  47   serialized.
  48
  49   If Address > 0x0FFFFFFF, then ASSERT().
  50
  51   @param  Address Address that encodes the PCI Bus, Device, Function and
  52                   Register.
  53
  54   @return The read value from the PCI configuration register.
  55
  56 **/
  57 UINT8
  58 EFIAPI
  59 PciRead8 (
  60   IN      UINTN                     Address
  61   );
  62
  63 /**
  64   Writes an 8-bit PCI configuration register.
  65
  66   Writes the 8-bit PCI configuration register specified by Address with the
  67   value specified by Value. Value is returned. This function must guarantee
  68   that all PCI read and write operations are serialized.
  69
  70   If Address > 0x0FFFFFFF, then ASSERT().
  71
  72   @param  Address Address that encodes the PCI Bus, Device, Function and
  73                   Register.
  74   @param  Value   The value to write.
  75
  76   @return The value written to the PCI configuration register.
  77
  78 **/
  79 UINT8
  80 EFIAPI
  81 PciWrite8 (
  82   IN      UINTN                     Address,
  83   IN      UINT8                     Data
  84   );
  85
  86 /**
  87   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  88   an 8-bit value.
  89
  90   Reads the 8-bit PCI configuration register specified by Address, performs a
  91   bitwise inclusive OR between the read result and the value specified by
  92   OrData, and writes the result to the 8-bit PCI configuration register
  93   specified by Address. The value written to the PCI configuration register is
  94   returned. This function must guarantee that all PCI read and write operations
  95   are serialized.
  96
  97   If Address > 0x0FFFFFFF, then ASSERT().
  98
  99   @param  Address Address that encodes the PCI Bus, Device, Function and
 100                   Register.
 101   @param  OrData  The value to OR with the PCI configuration register.
 102
 103   @return The value written back to the PCI configuration register.
 104
 105 **/
 106 UINT8
 107 EFIAPI
 108 PciOr8 (
 109   IN      UINTN                     Address,
 110   IN      UINT8                     OrData
 111   );
 112
 113 /**
 114   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 115   value.
 116
 117   Reads the 8-bit PCI configuration register specified by Address, performs a
 118   bitwise AND between the read result and the value specified by AndData, and
 119   writes the result to the 8-bit PCI configuration register specified by
 120   Address. The value written to the PCI configuration register is returned.
 121   This function must guarantee that all PCI read and write operations are
 122   serialized.
 123
 124   If Address > 0x0FFFFFFF, then ASSERT().
 125
 126   @param  Address Address that encodes the PCI Bus, Device, Function and
 127                   Register.
 128   @param  AndData The value to AND with the PCI configuration register.
 129
 130   @return The value written back to the PCI configuration register.
 131
 132 **/
 133 UINT8
 134 EFIAPI
 135 PciAnd8 (
 136   IN      UINTN                     Address,
 137   IN      UINT8                     AndData
 138   );
 139
 140 /**
 141   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 142   value, followed a  bitwise inclusive OR with another 8-bit value.
 143
 144   Reads the 8-bit PCI configuration register specified by Address, performs a
 145   bitwise AND between the read result and the value specified by AndData,
 146   performs a bitwise inclusive OR between the result of the AND operation and
 147   the value specified by OrData, and writes the result to the 8-bit PCI
 148   configuration register specified by Address. The value written to the PCI
 149   configuration register is returned. This function must guarantee that all PCI
 150   read and write operations are serialized.
 151
 152   If Address > 0x0FFFFFFF, then ASSERT().
 153
 154   @param  Address Address that encodes the PCI Bus, Device, Function and
 155                   Register.
 156   @param  AndData The value to AND with the PCI configuration register.
 157   @param  OrData  The value to OR with the result of the AND operation.
 158
 159   @return The value written back to the PCI configuration register.
 160
 161 **/
 162 UINT8
 163 EFIAPI
 164 PciAndThenOr8 (
 165   IN      UINTN                     Address,
 166   IN      UINT8                     AndData,
 167   IN      UINT8                     OrData
 168   );
 169
 170 /**
 171   Reads a bit field of a PCI configuration register.
 172
 173   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 174   specified by the StartBit and the EndBit. The value of the bit field is
 175   returned.
 176
 177   If Address > 0x0FFFFFFF, then ASSERT().
 178   If StartBit is greater than 7, then ASSERT().
 179   If EndBit is greater than 7, then ASSERT().
 180   If EndBit is less than StartBit, then ASSERT().
 181
 182   @param  Address   PCI configuration register to read.
 183   @param  StartBit  The ordinal of the least significant bit in the bit field.
 184                     Range 0..7.
 185   @param  EndBit    The ordinal of the most significant bit in the bit field.
 186                     Range 0..7.
 187
 188   @return The value of the bit field read from the PCI configuration register.
 189
 190 **/
 191 UINT8
 192 EFIAPI
 193 PciBitFieldRead8 (
 194   IN      UINTN                     Address,
 195   IN      UINTN                     StartBit,
 196   IN      UINTN                     EndBit
 197   );
 198
 199 /**
 200   Writes a bit field to a PCI configuration register.
 201
 202   Writes Value to the bit field of the PCI configuration register. The bit
 203   field is specified by the StartBit and the EndBit. All other bits in the
 204   destination PCI configuration register are preserved. The new value of the
 205   8-bit register is returned.
 206
 207   If Address > 0x0FFFFFFF, then ASSERT().
 208   If StartBit is greater than 7, then ASSERT().
 209   If EndBit is greater than 7, then ASSERT().
 210   If EndBit is less than StartBit, then ASSERT().
 211
 212   @param  Address   PCI configuration register to write.
 213   @param  StartBit  The ordinal of the least significant bit in the bit field.
 214                     Range 0..7.
 215   @param  EndBit    The ordinal of the most significant bit in the bit field.
 216                     Range 0..7.
 217   @param  Value     New value of the bit field.
 218
 219   @return The value written back to the PCI configuration register.
 220
 221 **/
 222 UINT8
 223 EFIAPI
 224 PciBitFieldWrite8 (
 225   IN      UINTN                     Address,
 226   IN      UINTN                     StartBit,
 227   IN      UINTN                     EndBit,
 228   IN      UINT8                     Value
 229   );
 230
 231 /**
 232   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 233   writes the result back to the bit field in the 8-bit port.
 234
 235   Reads the 8-bit PCI configuration register specified by Address, performs a
 236   bitwise inclusive OR between the read result and the value specified by
 237   OrData, and writes the result to the 8-bit PCI configuration register
 238   specified by Address. The value written to the PCI configuration register is
 239   returned. This function must guarantee that all PCI read and write operations
 240   are serialized. Extra left bits in OrData are stripped.
 241
 242   If Address > 0x0FFFFFFF, then ASSERT().
 243   If StartBit is greater than 7, then ASSERT().
 244   If EndBit is greater than 7, then ASSERT().
 245   If EndBit is less than StartBit, then ASSERT().
 246
 247   @param  Address   PCI configuration register to write.
 248   @param  StartBit  The ordinal of the least significant bit in the bit field.
 249                     Range 0..7.
 250   @param  EndBit    The ordinal of the most significant bit in the bit field.
 251                     Range 0..7.
 252   @param  OrData    The value to OR with the PCI configuration register.
 253
 254   @return The value written back to the PCI configuration register.
 255
 256 **/
 257 UINT8
 258 EFIAPI
 259 PciBitFieldOr8 (
 260   IN      UINTN                     Address,
 261   IN      UINTN                     StartBit,
 262   IN      UINTN                     EndBit,
 263   IN      UINT8                     OrData
 264   );
 265
 266 /**
 267   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 268   AND, and writes the result back to the bit field in the 8-bit register.
 269
 270   Reads the 8-bit PCI configuration register specified by Address, performs a
 271   bitwise AND between the read result and the value specified by AndData, and
 272   writes the result to the 8-bit PCI configuration register specified by
 273   Address. The value written to the PCI configuration register is returned.
 274   This function must guarantee that all PCI read and write operations are
 275   serialized. Extra left bits in AndData are stripped.
 276
 277   If Address > 0x0FFFFFFF, then ASSERT().
 278   If StartBit is greater than 7, then ASSERT().
 279   If EndBit is greater than 7, then ASSERT().
 280   If EndBit is less than StartBit, then ASSERT().
 281
 282   @param  Address   PCI configuration register to write.
 283   @param  StartBit  The ordinal of the least significant bit in the bit field.
 284                     Range 0..7.
 285   @param  EndBit    The ordinal of the most significant bit in the bit field.
 286                     Range 0..7.
 287   @param  AndData   The value to AND with the PCI configuration register.
 288
 289   @return The value written back to the PCI configuration register.
 290
 291 **/
 292 UINT8
 293 EFIAPI
 294 PciBitFieldAnd8 (
 295   IN      UINTN                     Address,
 296   IN      UINTN                     StartBit,
 297   IN      UINTN                     EndBit,
 298   IN      UINT8                     AndData
 299   );
 300
 301 /**
 302   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 303   bitwise inclusive OR, and writes the result back to the bit field in the
 304   8-bit port.
 305
 306   Reads the 8-bit PCI configuration register specified by Address, performs a
 307   bitwise AND followed by a bitwise inclusive OR between the read result and
 308   the value specified by AndData, and writes the result to the 8-bit PCI
 309   configuration register specified by Address. The value written to the PCI
 310   configuration register is returned. This function must guarantee that all PCI
 311   read and write operations are serialized. Extra left bits in both AndData and
 312   OrData are stripped.
 313
 314   If Address > 0x0FFFFFFF, then ASSERT().
 315   If StartBit is greater than 7, then ASSERT().
 316   If EndBit is greater than 7, then ASSERT().
 317   If EndBit is less than StartBit, then ASSERT().
 318
 319   @param  Address   PCI configuration register to write.
 320   @param  StartBit  The ordinal of the least significant bit in the bit field.
 321                     Range 0..7.
 322   @param  EndBit    The ordinal of the most significant bit in the bit field.
 323                     Range 0..7.
 324   @param  AndData   The value to AND with the PCI configuration register.
 325   @param  OrData    The value to OR with the result of the AND operation.
 326
 327   @return The value written back to the PCI configuration register.
 328
 329 **/
 330 UINT8
 331 EFIAPI
 332 PciBitFieldAndThenOr8 (
 333   IN      UINTN                     Address,
 334   IN      UINTN                     StartBit,
 335   IN      UINTN                     EndBit,
 336   IN      UINT8                     AndData,
 337   IN      UINT8                     OrData
 338   );
 339
 340 /**
 341   Reads a 16-bit PCI configuration register.
 342
 343   Reads and returns the 16-bit PCI configuration register specified by Address.
 344   This function must guarantee that all PCI read and write operations are
 345   serialized.
 346
 347   If Address > 0x0FFFFFFF, then ASSERT().
 348   If Address is not aligned on a 16-bit boundary, then ASSERT().
 349
 350   @param  Address Address that encodes the PCI Bus, Device, Function and
 351                   Register.
 352
 353   @return The read value from the PCI configuration register.
 354
 355 **/
 356 UINT16
 357 EFIAPI
 358 PciRead16 (
 359   IN      UINTN                     Address
 360   );
 361
 362 /**
 363   Writes a 16-bit PCI configuration register.
 364
 365   Writes the 16-bit PCI configuration register specified by Address with the
 366   value specified by Value. Value is returned. This function must guarantee
 367   that all PCI read and write operations are serialized.
 368
 369   If Address > 0x0FFFFFFF, then ASSERT().
 370   If Address is not aligned on a 16-bit boundary, then ASSERT().
 371
 372   @param  Address Address that encodes the PCI Bus, Device, Function and
 373                   Register.
 374   @param  Value   The value to write.
 375
 376   @return The value written to the PCI configuration register.
 377
 378 **/
 379 UINT16
 380 EFIAPI
 381 PciWrite16 (
 382   IN      UINTN                     Address,
 383   IN      UINT16                    Data
 384   );
 385
 386 /**
 387   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 388   a 16-bit value.
 389
 390   Reads the 16-bit PCI configuration register specified by Address, performs a
 391   bitwise inclusive OR between the read result and the value specified by
 392   OrData, and writes the result to the 16-bit PCI configuration register
 393   specified by Address. The value written to the PCI configuration register is
 394   returned. This function must guarantee that all PCI read and write operations
 395   are serialized.
 396
 397   If Address > 0x0FFFFFFF, then ASSERT().
 398   If Address is not aligned on a 16-bit boundary, then ASSERT().
 399
 400   @param  Address Address that encodes the PCI Bus, Device, Function and
 401                   Register.
 402   @param  OrData  The value to OR with the PCI configuration register.
 403
 404   @return The value written back to the PCI configuration register.
 405
 406 **/
 407 UINT16
 408 EFIAPI
 409 PciOr16 (
 410   IN      UINTN                     Address,
 411   IN      UINT16                    OrData
 412   );
 413
 414 /**
 415   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 416   value.
 417
 418   Reads the 16-bit PCI configuration register specified by Address, performs a
 419   bitwise AND between the read result and the value specified by AndData, and
 420   writes the result to the 16-bit PCI configuration register specified by
 421   Address. The value written to the PCI configuration register is returned.
 422   This function must guarantee that all PCI read and write operations are
 423   serialized.
 424
 425   If Address > 0x0FFFFFFF, then ASSERT().
 426   If Address is not aligned on a 16-bit boundary, then ASSERT().
 427
 428   @param  Address Address that encodes the PCI Bus, Device, Function and
 429                   Register.
 430   @param  AndData The value to AND with the PCI configuration register.
 431
 432   @return The value written back to the PCI configuration register.
 433
 434 **/
 435 UINT16
 436 EFIAPI
 437 PciAnd16 (
 438   IN      UINTN                     Address,
 439   IN      UINT16                    AndData
 440   );
 441
 442 /**
 443   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 444   value, followed a  bitwise inclusive OR with another 16-bit value.
 445
 446   Reads the 16-bit PCI configuration register specified by Address, performs a
 447   bitwise AND between the read result and the value specified by AndData,
 448   performs a bitwise inclusive OR between the result of the AND operation and
 449   the value specified by OrData, and writes the result to the 16-bit PCI
 450   configuration register specified by Address. The value written to the PCI
 451   configuration register is returned. This function must guarantee that all PCI
 452   read and write operations are serialized.
 453
 454   If Address > 0x0FFFFFFF, then ASSERT().
 455   If Address is not aligned on a 16-bit boundary, then ASSERT().
 456
 457   @param  Address Address that encodes the PCI Bus, Device, Function and
 458                   Register.
 459   @param  AndData The value to AND with the PCI configuration register.
 460   @param  OrData  The value to OR with the result of the AND operation.
 461
 462   @return The value written back to the PCI configuration register.
 463
 464 **/
 465 UINT16
 466 EFIAPI
 467 PciAndThenOr16 (
 468   IN      UINTN                     Address,
 469   IN      UINT16                    AndData,
 470   IN      UINT16                    OrData
 471   );
 472
 473 /**
 474   Reads a bit field of a PCI configuration register.
 475
 476   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 477   specified by the StartBit and the EndBit. The value of the bit field is
 478   returned.
 479
 480   If Address > 0x0FFFFFFF, then ASSERT().
 481   If Address is not aligned on a 16-bit boundary, then ASSERT().
 482   If StartBit is greater than 15, then ASSERT().
 483   If EndBit is greater than 15, then ASSERT().
 484   If EndBit is less than StartBit, then ASSERT().
 485
 486   @param  Address   PCI configuration register to read.
 487   @param  StartBit  The ordinal of the least significant bit in the bit field.
 488                     Range 0..15.
 489   @param  EndBit    The ordinal of the most significant bit in the bit field.
 490                     Range 0..15.
 491
 492   @return The value of the bit field read from the PCI configuration register.
 493
 494 **/
 495 UINT16
 496 EFIAPI
 497 PciBitFieldRead16 (
 498   IN      UINTN                     Address,
 499   IN      UINTN                     StartBit,
 500   IN      UINTN                     EndBit
 501   );
 502
 503 /**
 504   Writes a bit field to a PCI configuration register.
 505
 506   Writes Value to the bit field of the PCI configuration register. The bit
 507   field is specified by the StartBit and the EndBit. All other bits in the
 508   destination PCI configuration register are preserved. The new value of the
 509   16-bit register is returned.
 510
 511   If Address > 0x0FFFFFFF, then ASSERT().
 512   If Address is not aligned on a 16-bit boundary, then ASSERT().
 513   If StartBit is greater than 15, then ASSERT().
 514   If EndBit is greater than 15, then ASSERT().
 515   If EndBit is less than StartBit, then ASSERT().
 516
 517   @param  Address   PCI configuration register to write.
 518   @param  StartBit  The ordinal of the least significant bit in the bit field.
 519                     Range 0..15.
 520   @param  EndBit    The ordinal of the most significant bit in the bit field.
 521                     Range 0..15.
 522   @param  Value     New value of the bit field.
 523
 524   @return The value written back to the PCI configuration register.
 525
 526 **/
 527 UINT16
 528 EFIAPI
 529 PciBitFieldWrite16 (
 530   IN      UINTN                     Address,
 531   IN      UINTN                     StartBit,
 532   IN      UINTN                     EndBit,
 533   IN      UINT16                    Value
 534   );
 535
 536 /**
 537   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 538   writes the result back to the bit field in the 16-bit port.
 539
 540   Reads the 16-bit PCI configuration register specified by Address, performs a
 541   bitwise inclusive OR between the read result and the value specified by
 542   OrData, and writes the result to the 16-bit PCI configuration register
 543   specified by Address. The value written to the PCI configuration register is
 544   returned. This function must guarantee that all PCI read and write operations
 545   are serialized. Extra left bits in OrData are stripped.
 546
 547   If Address > 0x0FFFFFFF, then ASSERT().
 548   If Address is not aligned on a 16-bit boundary, then ASSERT().
 549   If StartBit is greater than 15, then ASSERT().
 550   If EndBit is greater than 15, then ASSERT().
 551   If EndBit is less than StartBit, then ASSERT().
 552
 553   @param  Address   PCI configuration register to write.
 554   @param  StartBit  The ordinal of the least significant bit in the bit field.
 555                     Range 0..15.
 556   @param  EndBit    The ordinal of the most significant bit in the bit field.
 557                     Range 0..15.
 558   @param  OrData    The value to OR with the PCI configuration register.
 559
 560   @return The value written back to the PCI configuration register.
 561
 562 **/
 563 UINT16
 564 EFIAPI
 565 PciBitFieldOr16 (
 566   IN      UINTN                     Address,
 567   IN      UINTN                     StartBit,
 568   IN      UINTN                     EndBit,
 569   IN      UINT16                    OrData
 570   );
 571
 572 /**
 573   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 574   AND, and writes the result back to the bit field in the 16-bit register.
 575
 576   Reads the 16-bit PCI configuration register specified by Address, performs a
 577   bitwise AND between the read result and the value specified by AndData, and
 578   writes the result to the 16-bit PCI configuration register specified by
 579   Address. The value written to the PCI configuration register is returned.
 580   This function must guarantee that all PCI read and write operations are
 581   serialized. Extra left bits in AndData are stripped.
 582
 583   If Address > 0x0FFFFFFF, then ASSERT().
 584   If Address is not aligned on a 16-bit boundary, then ASSERT().
 585   If StartBit is greater than 15, then ASSERT().
 586   If EndBit is greater than 15, then ASSERT().
 587   If EndBit is less than StartBit, then ASSERT().
 588
 589   @param  Address   PCI configuration register to write.
 590   @param  StartBit  The ordinal of the least significant bit in the bit field.
 591                     Range 0..15.
 592   @param  EndBit    The ordinal of the most significant bit in the bit field.
 593                     Range 0..15.
 594   @param  AndData   The value to AND with the PCI configuration register.
 595
 596   @return The value written back to the PCI configuration register.
 597
 598 **/
 599 UINT16
 600 EFIAPI
 601 PciBitFieldAnd16 (
 602   IN      UINTN                     Address,
 603   IN      UINTN                     StartBit,
 604   IN      UINTN                     EndBit,
 605   IN      UINT16                    AndData
 606   );
 607
 608 /**
 609   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 610   bitwise inclusive OR, and writes the result back to the bit field in the
 611   16-bit port.
 612
 613   Reads the 16-bit PCI configuration register specified by Address, performs a
 614   bitwise AND followed by a bitwise inclusive OR between the read result and
 615   the value specified by AndData, and writes the result to the 16-bit PCI
 616   configuration register specified by Address. The value written to the PCI
 617   configuration register is returned. This function must guarantee that all PCI
 618   read and write operations are serialized. Extra left bits in both AndData and
 619   OrData are stripped.
 620
 621   If Address > 0x0FFFFFFF, then ASSERT().
 622   If Address is not aligned on a 16-bit boundary, then ASSERT().
 623   If StartBit is greater than 15, then ASSERT().
 624   If EndBit is greater than 15, then ASSERT().
 625   If EndBit is less than StartBit, then ASSERT().
 626
 627   @param  Address   PCI configuration register to write.
 628   @param  StartBit  The ordinal of the least significant bit in the bit field.
 629                     Range 0..15.
 630   @param  EndBit    The ordinal of the most significant bit in the bit field.
 631                     Range 0..15.
 632   @param  AndData   The value to AND with the PCI configuration register.
 633   @param  OrData    The value to OR with the result of the AND operation.
 634
 635   @return The value written back to the PCI configuration register.
 636
 637 **/
 638 UINT16
 639 EFIAPI
 640 PciBitFieldAndThenOr16 (
 641   IN      UINTN                     Address,
 642   IN      UINTN                     StartBit,
 643   IN      UINTN                     EndBit,
 644   IN      UINT16                    AndData,
 645   IN      UINT16                    OrData
 646   );
 647
 648 /**
 649   Reads a 32-bit PCI configuration register.
 650
 651   Reads and returns the 32-bit PCI configuration register specified by Address.
 652   This function must guarantee that all PCI read and write operations are
 653   serialized.
 654
 655   If Address > 0x0FFFFFFF, then ASSERT().
 656   If Address is not aligned on a 32-bit boundary, then ASSERT().
 657
 658   @param  Address Address that encodes the PCI Bus, Device, Function and
 659                   Register.
 660
 661   @return The read value from the PCI configuration register.
 662
 663 **/
 664 UINT32
 665 EFIAPI
 666 PciRead32 (
 667   IN      UINTN                     Address
 668   );
 669
 670 /**
 671   Writes a 32-bit PCI configuration register.
 672
 673   Writes the 32-bit PCI configuration register specified by Address with the
 674   value specified by Value. Value is returned. This function must guarantee
 675   that all PCI read and write operations are serialized.
 676
 677   If Address > 0x0FFFFFFF, then ASSERT().
 678   If Address is not aligned on a 32-bit boundary, then ASSERT().
 679
 680   @param  Address Address that encodes the PCI Bus, Device, Function and
 681                   Register.
 682   @param  Value   The value to write.
 683
 684   @return The value written to the PCI configuration register.
 685
 686 **/
 687 UINT32
 688 EFIAPI
 689 PciWrite32 (
 690   IN      UINTN                     Address,
 691   IN      UINT32                    Data
 692   );
 693
 694 /**
 695   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 696   a 32-bit value.
 697
 698   Reads the 32-bit PCI configuration register specified by Address, performs a
 699   bitwise inclusive OR between the read result and the value specified by
 700   OrData, and writes the result to the 32-bit PCI configuration register
 701   specified by Address. The value written to the PCI configuration register is
 702   returned. This function must guarantee that all PCI read and write operations
 703   are serialized.
 704
 705   If Address > 0x0FFFFFFF, then ASSERT().
 706   If Address is not aligned on a 32-bit boundary, then ASSERT().
 707
 708   @param  Address Address that encodes the PCI Bus, Device, Function and
 709                   Register.
 710   @param  OrData  The value to OR with the PCI configuration register.
 711
 712   @return The value written back to the PCI configuration register.
 713
 714 **/
 715 UINT32
 716 EFIAPI
 717 PciOr32 (
 718   IN      UINTN                     Address,
 719   IN      UINT32                    OrData
 720   );
 721
 722 /**
 723   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 724   value.
 725
 726   Reads the 32-bit PCI configuration register specified by Address, performs a
 727   bitwise AND between the read result and the value specified by AndData, and
 728   writes the result to the 32-bit PCI configuration register specified by
 729   Address. The value written to the PCI configuration register is returned.
 730   This function must guarantee that all PCI read and write operations are
 731   serialized.
 732
 733   If Address > 0x0FFFFFFF, then ASSERT().
 734   If Address is not aligned on a 32-bit boundary, then ASSERT().
 735
 736   @param  Address Address that encodes the PCI Bus, Device, Function and
 737                   Register.
 738   @param  AndData The value to AND with the PCI configuration register.
 739
 740   @return The value written back to the PCI configuration register.
 741
 742 **/
 743 UINT32
 744 EFIAPI
 745 PciAnd32 (
 746   IN      UINTN                     Address,
 747   IN      UINT32                    AndData
 748   );
 749
 750 /**
 751   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 752   value, followed a  bitwise inclusive OR with another 32-bit value.
 753
 754   Reads the 32-bit PCI configuration register specified by Address, performs a
 755   bitwise AND between the read result and the value specified by AndData,
 756   performs a bitwise inclusive OR between the result of the AND operation and
 757   the value specified by OrData, and writes the result to the 32-bit PCI
 758   configuration register specified by Address. The value written to the PCI
 759   configuration register is returned. This function must guarantee that all PCI
 760   read and write operations are serialized.
 761
 762   If Address > 0x0FFFFFFF, then ASSERT().
 763   If Address is not aligned on a 32-bit boundary, then ASSERT().
 764
 765   @param  Address Address that encodes the PCI Bus, Device, Function and
 766                   Register.
 767   @param  AndData The value to AND with the PCI configuration register.
 768   @param  OrData  The value to OR with the result of the AND operation.
 769
 770   @return The value written back to the PCI configuration register.
 771
 772 **/
 773 UINT32
 774 EFIAPI
 775 PciAndThenOr32 (
 776   IN      UINTN                     Address,
 777   IN      UINT32                    AndData,
 778   IN      UINT32                    OrData
 779   );
 780
 781 /**
 782   Reads a bit field of a PCI configuration register.
 783
 784   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 785   specified by the StartBit and the EndBit. The value of the bit field is
 786   returned.
 787
 788   If Address > 0x0FFFFFFF, then ASSERT().
 789   If Address is not aligned on a 32-bit boundary, then ASSERT().
 790   If StartBit is greater than 31, then ASSERT().
 791   If EndBit is greater than 31, then ASSERT().
 792   If EndBit is less than StartBit, then ASSERT().
 793
 794   @param  Address   PCI configuration register to read.
 795   @param  StartBit  The ordinal of the least significant bit in the bit field.
 796                     Range 0..31.
 797   @param  EndBit    The ordinal of the most significant bit in the bit field.
 798                     Range 0..31.
 799
 800   @return The value of the bit field read from the PCI configuration register.
 801
 802 **/
 803 UINT32
 804 EFIAPI
 805 PciBitFieldRead32 (
 806   IN      UINTN                     Address,
 807   IN      UINTN                     StartBit,
 808   IN      UINTN                     EndBit
 809   );
 810
 811 /**
 812   Writes a bit field to a PCI configuration register.
 813
 814   Writes Value to the bit field of the PCI configuration register. The bit
 815   field is specified by the StartBit and the EndBit. All other bits in the
 816   destination PCI configuration register are preserved. The new value of the
 817   32-bit register is returned.
 818
 819   If Address > 0x0FFFFFFF, then ASSERT().
 820   If Address is not aligned on a 32-bit boundary, then ASSERT().
 821   If StartBit is greater than 31, then ASSERT().
 822   If EndBit is greater than 31, then ASSERT().
 823   If EndBit is less than StartBit, then ASSERT().
 824
 825   @param  Address   PCI configuration register to write.
 826   @param  StartBit  The ordinal of the least significant bit in the bit field.
 827                     Range 0..31.
 828   @param  EndBit    The ordinal of the most significant bit in the bit field.
 829                     Range 0..31.
 830   @param  Value     New value of the bit field.
 831
 832   @return The value written back to the PCI configuration register.
 833
 834 **/
 835 UINT32
 836 EFIAPI
 837 PciBitFieldWrite32 (
 838   IN      UINTN                     Address,
 839   IN      UINTN                     StartBit,
 840   IN      UINTN                     EndBit,
 841   IN      UINT32                    Value
 842   );
 843
 844 /**
 845   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 846   writes the result back to the bit field in the 32-bit port.
 847
 848   Reads the 32-bit PCI configuration register specified by Address, performs a
 849   bitwise inclusive OR between the read result and the value specified by
 850   OrData, and writes the result to the 32-bit PCI configuration register
 851   specified by Address. The value written to the PCI configuration register is
 852   returned. This function must guarantee that all PCI read and write operations
 853   are serialized. Extra left bits in OrData are stripped.
 854
 855   If Address > 0x0FFFFFFF, then ASSERT().
 856   If Address is not aligned on a 32-bit boundary, then ASSERT().
 857   If StartBit is greater than 31, then ASSERT().
 858   If EndBit is greater than 31, then ASSERT().
 859   If EndBit is less than StartBit, then ASSERT().
 860
 861   @param  Address   PCI configuration register to write.
 862   @param  StartBit  The ordinal of the least significant bit in the bit field.
 863                     Range 0..31.
 864   @param  EndBit    The ordinal of the most significant bit in the bit field.
 865                     Range 0..31.
 866   @param  OrData    The value to OR with the PCI configuration register.
 867
 868   @return The value written back to the PCI configuration register.
 869
 870 **/
 871 UINT32
 872 EFIAPI
 873 PciBitFieldOr32 (
 874   IN      UINTN                     Address,
 875   IN      UINTN                     StartBit,
 876   IN      UINTN                     EndBit,
 877   IN      UINT32                    OrData
 878   );
 879
 880 /**
 881   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 882   AND, and writes the result back to the bit field in the 32-bit register.
 883
 884   Reads the 32-bit PCI configuration register specified by Address, performs a
 885   bitwise AND between the read result and the value specified by AndData, and
 886   writes the result to the 32-bit PCI configuration register specified by
 887   Address. The value written to the PCI configuration register is returned.
 888   This function must guarantee that all PCI read and write operations are
 889   serialized. Extra left bits in AndData are stripped.
 890
 891   If Address > 0x0FFFFFFF, then ASSERT().
 892   If Address is not aligned on a 32-bit boundary, then ASSERT().
 893   If StartBit is greater than 31, then ASSERT().
 894   If EndBit is greater than 31, then ASSERT().
 895   If EndBit is less than StartBit, then ASSERT().
 896
 897   @param  Address   PCI configuration register to write.
 898   @param  StartBit  The ordinal of the least significant bit in the bit field.
 899                     Range 0..31.
 900   @param  EndBit    The ordinal of the most significant bit in the bit field.
 901                     Range 0..31.
 902   @param  AndData   The value to AND with the PCI configuration register.
 903
 904   @return The value written back to the PCI configuration register.
 905
 906 **/
 907 UINT32
 908 EFIAPI
 909 PciBitFieldAnd32 (
 910   IN      UINTN                     Address,
 911   IN      UINTN                     StartBit,
 912   IN      UINTN                     EndBit,
 913   IN      UINT32                    AndData
 914   );
 915
 916 /**
 917   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 918   bitwise inclusive OR, and writes the result back to the bit field in the
 919   32-bit port.
 920
 921   Reads the 32-bit PCI configuration register specified by Address, performs a
 922   bitwise AND followed by a bitwise inclusive OR between the read result and
 923   the value specified by AndData, and writes the result to the 32-bit PCI
 924   configuration register specified by Address. The value written to the PCI
 925   configuration register is returned. This function must guarantee that all PCI
 926   read and write operations are serialized. Extra left bits in both AndData and
 927   OrData are stripped.
 928
 929   If Address > 0x0FFFFFFF, then ASSERT().
 930   If Address is not aligned on a 32-bit boundary, then ASSERT().
 931   If StartBit is greater than 31, then ASSERT().
 932   If EndBit is greater than 31, then ASSERT().
 933   If EndBit is less than StartBit, then ASSERT().
 934
 935   @param  Address   PCI configuration register to write.
 936   @param  StartBit  The ordinal of the least significant bit in the bit field.
 937                     Range 0..31.
 938   @param  EndBit    The ordinal of the most significant bit in the bit field.
 939                     Range 0..31.
 940   @param  AndData   The value to AND with the PCI configuration register.
 941   @param  OrData    The value to OR with the result of the AND operation.
 942
 943   @return The value written back to the PCI configuration register.
 944
 945 **/
 946 UINT32
 947 EFIAPI
 948 PciBitFieldAndThenOr32 (
 949   IN      UINTN                     Address,
 950   IN      UINTN                     StartBit,
 951   IN      UINTN                     EndBit,
 952   IN      UINT32                    AndData,
 953   IN      UINT32                    OrData
 954   );
 955
 956 /**
 957   Reads a range of PCI configuration registers into a caller supplied buffer.
 958
 959   Reads the range of PCI configuration registers specified by StartAddress and
 960   Size into the buffer specified by Buffer. This function only allows the PCI
 961   configuration registers from a single PCI function to be read. Size is
 962   returned. When possible 32-bit PCI configuration read cycles are used to read
 963   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 964   and 16-bit PCI configuration read cycles may be used at the beginning and the
 965   end of the range.
 966
 967   If StartAddress > 0x0FFFFFFF, then ASSERT().
 968   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 969   If Size > 0 and Buffer is NULL, then ASSERT().
 970
 971   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 972                         Function and Register.
 973   @param  Size          Size in bytes of the transfer.
 974   @param  Buffer        Pointer to a buffer receiving the data read.
 975
 976   @return Size
 977
 978 **/
 979 UINTN
 980 EFIAPI
 981 PciReadBuffer (
 982   IN      UINTN                     StartAddress,
 983   IN      UINTN                     Size,
 984   OUT     VOID                      *Buffer
 985   );
 986
 987 /**
 988   Copies the data in a caller supplied buffer to a specified range of PCI
 989   configuration space.
 990
 991   Writes the range of PCI configuration registers specified by StartAddress and
 992   Size from the buffer specified by Buffer. This function only allows the PCI
 993   configuration registers from a single PCI function to be written. Size is
 994   returned. When possible 32-bit PCI configuration write cycles are used to
 995   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
 996   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
 997   and the end of the range.
 998
 999   If StartAddress > 0x0FFFFFFF, then ASSERT().
1000   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1001   If Size > 0 and Buffer is NULL, then ASSERT().
1002
1003   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1004                         Function and Register.
1005   @param  Size          Size in bytes of the transfer.
1006   @param  Buffer        Pointer to a buffer containing the data to write.
1007
1008   @return Size
1009
1010 **/
1011 UINTN
1012 EFIAPI
1013 PciWriteBuffer (
1014   IN      UINTN                     StartAddress,
1015   IN      UINTN                     Size,
1016   IN      VOID                      *Buffer
1017   );
1018
1019 #endif