EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/EbcCache.c

   1 /*++
   2
   3 Copyright (c) 2004 - 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12
  13 Module Name:
  14
  15   x86Cache.c
  16
  17 Abstract:
  18
  19   Cache Maintenance Functions.
  20
  21 --*/
  22
  23 #include "EdkIIGlueBase.h"
  24
  25 /**
  26   Invalidates the entire instruction cache in cache coherency domain of the
  27   calling CPU.
  28
  29   Invalidates the entire instruction cache in cache coherency domain of the
  30   calling CPU.
  31
  32 **/
  33 VOID
  34 EFIAPI
  35 GlueInvalidateInstructionCache (
  36   VOID
  37   )
  38 {
  39 }
  40
  41 /**
  42   Invalidates a range of instruction cache lines in the cache coherency domain
  43   of the calling CPU.
  44
  45   Invalidates the instruction cache lines specified by Address and Length. If
  46   Address is not aligned on a cache line boundary, then entire instruction
  47   cache line containing Address is invalidated. If Address + Length is not
  48   aligned on a cache line boundary, then the entire instruction cache line
  49   containing Address + Length -1 is invalidated. This function may choose to
  50   invalidate the entire instruction cache if that is more efficient than
  51   invalidating the specified range. If Length is 0, the no instruction cache
  52   lines are invalidated. Address is returned.
  53
  54   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  55
  56   @param  Address The base address of the instruction cache lines to
  57                   invalidate. If the CPU is in a physical addressing mode, then
  58                   Address is a physical address. If the CPU is in a virtual
  59                   addressing mode, then Address is a virtual address.
  60
  61   @param  Length  The number of bytes to invalidate from the instruction cache.
  62
  63   @return Address
  64
  65 **/
  66 VOID *
  67 EFIAPI
  68 InvalidateInstructionCacheRange (
  69   IN      VOID                      *Address,
  70   IN      UINTN                     Length
  71   )
  72 {
  73   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  74   return Address;
  75 }
  76
  77 /**
  78   Writes Back and Invalidates the entire data cache in cache coherency domain
  79   of the calling CPU.
  80
  81   Writes Back and Invalidates the entire data cache in cache coherency domain
  82   of the calling CPU. This function guarantees that all dirty cache lines are
  83   written back to system memory, and also invalidates all the data cache lines
  84   in the cache coherency domain of the calling CPU.
  85
  86 **/
  87 VOID
  88 EFIAPI
  89 WriteBackInvalidateDataCache (
  90   VOID
  91   )
  92 {
  93 }
  94
  95 /**
  96   Writes Back and Invalidates a range of data cache lines in the cache
  97   coherency domain of the calling CPU.
  98
  99   Writes Back and Invalidate the data cache lines specified by Address and
 100   Length. If Address is not aligned on a cache line boundary, then entire data
 101   cache line containing Address is written back and invalidated. If Address +
 102   Length is not aligned on a cache line boundary, then the entire data cache
 103   line containing Address + Length -1 is written back and invalidated. This
 104   function may choose to write back and invalidate the entire data cache if
 105   that is more efficient than writing back and invalidating the specified
 106   range. If Length is 0, the no data cache lines are written back and
 107   invalidated. Address is returned.
 108
 109   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 110
 111   @param  Address The base address of the data cache lines to write back and
 112                   invalidate. If the CPU is in a physical addressing mode, then
 113                   Address is a physical address. If the CPU is in a virtual
 114                   addressing mode, then Address is a virtual address.
 115   @param  Length  The number of bytes to write back and invalidate from the
 116                   data cache.
 117
 118   @return Address
 119
 120 **/
 121 VOID *
 122 EFIAPI
 123 WriteBackInvalidateDataCacheRange (
 124   IN      VOID                      *Address,
 125   IN      UINTN                     Length
 126   )
 127 {
 128   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 129   return Address;
 130 }
 131
 132 /**
 133   Writes Back the entire data cache in cache coherency domain of the calling
 134   CPU.
 135
 136   Writes Back the entire data cache in cache coherency domain of the calling
 137   CPU. This function guarantees that all dirty cache lines are written back to
 138   system memory. This function may also invalidate all the data cache lines in
 139   the cache coherency domain of the calling CPU.
 140
 141 **/
 142 VOID
 143 EFIAPI
 144 WriteBackDataCache (
 145   VOID
 146   )
 147 {
 148 }
 149
 150 /**
 151   Writes Back a range of data cache lines in the cache coherency domain of the
 152   calling CPU.
 153
 154   Writes Back the data cache lines specified by Address and Length. If Address
 155   is not aligned on a cache line boundary, then entire data cache line
 156   containing Address is written back. If Address + Length is not aligned on a
 157   cache line boundary, then the entire data cache line containing Address +
 158   Length -1 is written back. This function may choose to write back the entire
 159   data cache if that is more efficient than writing back the specified range.
 160   If Length is 0, the no data cache lines are written back. This function may
 161   also invalidate all the data cache lines in the specified range of the cache
 162   coherency domain of the calling CPU. Address is returned.
 163
 164   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 165
 166   @param  Address The base address of the data cache lines to write back. If
 167                   the CPU is in a physical addressing mode, then Address is a
 168                   physical address. If the CPU is in a virtual addressing
 169                   mode, then Address is a virtual address.
 170   @param  Length  The number of bytes to write back from the data cache.
 171
 172   @return Address
 173
 174 **/
 175 VOID *
 176 EFIAPI
 177 WriteBackDataCacheRange (
 178   IN      VOID                      *Address,
 179   IN      UINTN                     Length
 180   )
 181 {
 182   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 183   return Address;
 184 }
 185
 186 /**
 187   Invalidates the entire data cache in cache coherency domain of the calling
 188   CPU.
 189
 190   Invalidates the entire data cache in cache coherency domain of the calling
 191   CPU. This function must be used with care because dirty cache lines are not
 192   written back to system memory. It is typically used for cache diagnostics. If
 193   the CPU does not support invalidation of the entire data cache, then a write
 194   back and invalidate operation should be performed on the entire data cache.
 195
 196 **/
 197 VOID
 198 EFIAPI
 199 InvalidateDataCache (
 200   VOID
 201   )
 202 {
 203 }
 204
 205 /**
 206   Invalidates a range of data cache lines in the cache coherency domain of the
 207   calling CPU.
 208
 209   Invalidates the data cache lines specified by Address and Length. If Address
 210   is not aligned on a cache line boundary, then entire data cache line
 211   containing Address is invalidated. If Address + Length is not aligned on a
 212   cache line boundary, then the entire data cache line containing Address +
 213   Length -1 is invalidated. This function must never invalidate any cache lines
 214   outside the specified range. If Length is 0, the no data cache lines are
 215   invalidated. Address is returned. This function must be used with care
 216   because dirty cache lines are not written back to system memory. It is
 217   typically used for cache diagnostics. If the CPU does not support
 218   invalidation of a data cache range, then a write back and invalidate
 219   operation should be performed on the data cache range.
 220
 221   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 222
 223   @param  Address The base address of the data cache lines to invalidate. If
 224                   the CPU is in a physical addressing mode, then Address is a
 225                   physical address. If the CPU is in a virtual addressing mode,
 226                   then Address is a virtual address.
 227   @param  Length  The number of bytes to invalidate from the data cache.
 228
 229   @return Address
 230
 231 **/
 232 VOID *
 233 EFIAPI
 234 InvalidateDataCacheRange (
 235   IN      VOID                      *Address,
 236   IN      UINTN                     Length
 237   )
 238 {
 239   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 240   return Address;
 241 }