EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/X86Cache.c

   1 /*++
   2
   3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
   4 This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12
  13 Module Name:
  14
  15   x86Cache.c
  16
  17 Abstract:
  18
  19   Cache Maintenance Functions.
  20
  21 --*/
  22
  23 #include "EdkIIGlueBase.h"
  24
  25 //
  26 // This size must be at or below the smallest cache size possible among all
  27 // supported processors
  28 //
  29 #define CACHE_LINE_SIZE             0x20
  30
  31 /**
  32   Invalidates the entire instruction cache in cache coherency domain of the
  33   calling CPU.
  34
  35   Invalidates the entire instruction cache in cache coherency domain of the
  36   calling CPU.
  37
  38 **/
  39 VOID
  40 EFIAPI
  41 GlueInvalidateInstructionCache (
  42   VOID
  43   )
  44 {
  45 }
  46
  47 /**
  48   Invalidates a range of instruction cache lines in the cache coherency domain
  49   of the calling CPU.
  50
  51   Invalidates the instruction cache lines specified by Address and Length. If
  52   Address is not aligned on a cache line boundary, then entire instruction
  53   cache line containing Address is invalidated. If Address + Length is not
  54   aligned on a cache line boundary, then the entire instruction cache line
  55   containing Address + Length -1 is invalidated. This function may choose to
  56   invalidate the entire instruction cache if that is more efficient than
  57   invalidating the specified range. If Length is 0, the no instruction cache
  58   lines are invalidated. Address is returned.
  59
  60   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  61
  62   @param  Address The base address of the instruction cache lines to
  63                   invalidate. If the CPU is in a physical addressing mode, then
  64                   Address is a physical address. If the CPU is in a virtual
  65                   addressing mode, then Address is a virtual address.
  66
  67   @param  Length  The number of bytes to invalidate from the instruction cache.
  68
  69   @return Address
  70
  71 **/
  72 VOID *
  73 EFIAPI
  74 InvalidateInstructionCacheRange (
  75   IN      VOID                      *Address,
  76   IN      UINTN                     Length
  77   )
  78 {
  79   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  80   return Address;
  81 }
  82
  83 /**
  84   Writes Back and Invalidates the entire data cache in cache coherency domain
  85   of the calling CPU.
  86
  87   Writes Back and Invalidates the entire data cache in cache coherency domain
  88   of the calling CPU. This function guarantees that all dirty cache lines are
  89   written back to system memory, and also invalidates all the data cache lines
  90   in the cache coherency domain of the calling CPU.
  91
  92 **/
  93 VOID
  94 EFIAPI
  95 WriteBackInvalidateDataCache (
  96   VOID
  97   )
  98 {
  99   AsmWbinvd ();
 100 }
 101
 102 /**
 103   Writes Back and Invalidates a range of data cache lines in the cache
 104   coherency domain of the calling CPU.
 105
 106   Writes Back and Invalidate the data cache lines specified by Address and
 107   Length. If Address is not aligned on a cache line boundary, then entire data
 108   cache line containing Address is written back and invalidated. If Address +
 109   Length is not aligned on a cache line boundary, then the entire data cache
 110   line containing Address + Length -1 is written back and invalidated. This
 111   function may choose to write back and invalidate the entire data cache if
 112   that is more efficient than writing back and invalidating the specified
 113   range. If Length is 0, the no data cache lines are written back and
 114   invalidated. Address is returned.
 115
 116   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 117
 118   @param  Address The base address of the data cache lines to write back and
 119                   invalidate. If the CPU is in a physical addressing mode, then
 120                   Address is a physical address. If the CPU is in a virtual
 121                   addressing mode, then Address is a virtual address.
 122   @param  Length  The number of bytes to write back and invalidate from the
 123                   data cache.
 124
 125   @return Address
 126
 127 **/
 128 VOID *
 129 EFIAPI
 130 WriteBackInvalidateDataCacheRange (
 131   IN      VOID                      *Address,
 132   IN      UINTN                     Length
 133   )
 134 {
 135   UINTN                             Start, End;
 136
 137   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 138
 139   if (Length == 0) {
 140     return Address;
 141   }
 142
 143   Start = (UINTN)Address;
 144   End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
 145   Start &= ~(CACHE_LINE_SIZE - 1);
 146
 147   do {
 148     Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
 149   } while (Start != End);
 150   return Address;
 151 }
 152
 153 /**
 154   Writes Back the entire data cache in cache coherency domain of the calling
 155   CPU.
 156
 157   Writes Back the entire data cache in cache coherency domain of the calling
 158   CPU. This function guarantees that all dirty cache lines are written back to
 159   system memory. This function may also invalidate all the data cache lines in
 160   the cache coherency domain of the calling CPU.
 161
 162 **/
 163 VOID
 164 EFIAPI
 165 WriteBackDataCache (
 166   VOID
 167   )
 168 {
 169   WriteBackInvalidateDataCache ();
 170 }
 171
 172 /**
 173   Writes Back a range of data cache lines in the cache coherency domain of the
 174   calling CPU.
 175
 176   Writes Back the data cache lines specified by Address and Length. If Address
 177   is not aligned on a cache line boundary, then entire data cache line
 178   containing Address is written back. If Address + Length is not aligned on a
 179   cache line boundary, then the entire data cache line containing Address +
 180   Length -1 is written back. This function may choose to write back the entire
 181   data cache if that is more efficient than writing back the specified range.
 182   If Length is 0, the no data cache lines are written back. This function may
 183   also invalidate all the data cache lines in the specified range of the cache
 184   coherency domain of the calling CPU. Address is returned.
 185
 186   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 187
 188   @param  Address The base address of the data cache lines to write back. If
 189                   the CPU is in a physical addressing mode, then Address is a
 190                   physical address. If the CPU is in a virtual addressing
 191                   mode, then Address is a virtual address.
 192   @param  Length  The number of bytes to write back from the data cache.
 193
 194   @return Address
 195
 196 **/
 197 VOID *
 198 EFIAPI
 199 WriteBackDataCacheRange (
 200   IN      VOID                      *Address,
 201   IN      UINTN                     Length
 202   )
 203 {
 204   return WriteBackInvalidateDataCacheRange (Address, Length);
 205 }
 206
 207 /**
 208   Invalidates the entire data cache in cache coherency domain of the calling
 209   CPU.
 210
 211   Invalidates the entire data cache in cache coherency domain of the calling
 212   CPU. This function must be used with care because dirty cache lines are not
 213   written back to system memory. It is typically used for cache diagnostics. If
 214   the CPU does not support invalidation of the entire data cache, then a write
 215   back and invalidate operation should be performed on the entire data cache.
 216
 217 **/
 218 VOID
 219 EFIAPI
 220 InvalidateDataCache (
 221   VOID
 222   )
 223 {
 224   AsmInvd ();
 225 }
 226
 227 /**
 228   Invalidates a range of data cache lines in the cache coherency domain of the
 229   calling CPU.
 230
 231   Invalidates the data cache lines specified by Address and Length. If Address
 232   is not aligned on a cache line boundary, then entire data cache line
 233   containing Address is invalidated. If Address + Length is not aligned on a
 234   cache line boundary, then the entire data cache line containing Address +
 235   Length -1 is invalidated. This function must never invalidate any cache lines
 236   outside the specified range. If Length is 0, the no data cache lines are
 237   invalidated. Address is returned. This function must be used with care
 238   because dirty cache lines are not written back to system memory. It is
 239   typically used for cache diagnostics. If the CPU does not support
 240   invalidation of a data cache range, then a write back and invalidate
 241   operation should be performed on the data cache range.
 242
 243   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 244
 245   @param  Address The base address of the data cache lines to invalidate. If
 246                   the CPU is in a physical addressing mode, then Address is a
 247                   physical address. If the CPU is in a virtual addressing mode,
 248                   then Address is a virtual address.
 249   @param  Length  The number of bytes to invalidate from the data cache.
 250
 251   @return Address
 252
 253 **/
 254 VOID *
 255 EFIAPI
 256 InvalidateDataCacheRange (
 257   IN      VOID                      *Address,
 258   IN      UINTN                     Length
 259   )
 260 {
 261   return WriteBackInvalidateDataCacheRange (Address, Length);
 262 }