]>
git.proxmox.com Git - mirror_edk2.git/blob - EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/PciLib.c
3 Copyright (c) 2004 - 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 Functions in this library instance make use of MMIO functions in IoLib to
21 access memory mapped PCI configuration space.
23 All assertions for I/O operations are handled in MMIO functions in the IoLib
28 #include "EdkIIGlueBase.h"
31 Assert the validity of a PCI address. A valid PCI address should contain 1's
32 only in the low 28 bits.
34 @param A The address to validate.
37 #define ASSERT_INVALID_PCI_ADDRESS(A) \
38 ASSERT (((A) & ~0xfffffff) == 0)
42 Gets the base address of PCI Express.
44 This internal functions retrieves PCI Express Base Address via a PCD entry
45 PcdPciExpressBaseAddress.
47 @return The base address of PCI Express.
52 GetPciExpressBaseAddress (
56 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
60 Reads an 8-bit PCI configuration register.
62 Reads and returns the 8-bit PCI configuration register specified by Address.
63 This function must guarantee that all PCI read and write operations are
66 If Address > 0x0FFFFFFF, then ASSERT().
68 @param Address Address that encodes the PCI Bus, Device, Function and
71 @return The read value from the PCI configuration register.
80 ASSERT_INVALID_PCI_ADDRESS (Address
);
81 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
85 Writes an 8-bit PCI configuration register.
87 Writes the 8-bit PCI configuration register specified by Address with the
88 value specified by Value. Value is returned. This function must guarantee
89 that all PCI read and write operations are serialized.
91 If Address > 0x0FFFFFFF, then ASSERT().
93 @param Address Address that encodes the PCI Bus, Device, Function and
95 @param Value The value to write.
97 @return The value written to the PCI configuration register.
107 ASSERT_INVALID_PCI_ADDRESS (Address
);
108 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
112 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
115 Reads the 8-bit PCI configuration register specified by Address, performs a
116 bitwise inclusive OR between the read result and the value specified by
117 OrData, and writes the result to the 8-bit PCI configuration register
118 specified by Address. The value written to the PCI configuration register is
119 returned. This function must guarantee that all PCI read and write operations
122 If Address > 0x0FFFFFFF, then ASSERT().
124 @param Address Address that encodes the PCI Bus, Device, Function and
126 @param OrData The value to OR with the PCI configuration register.
128 @return The value written back to the PCI configuration register.
138 ASSERT_INVALID_PCI_ADDRESS (Address
);
139 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
143 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
146 Reads the 8-bit PCI configuration register specified by Address, performs a
147 bitwise AND between the read result and the value specified by AndData, and
148 writes the result to the 8-bit PCI configuration register specified by
149 Address. The value written to the PCI configuration register is returned.
150 This function must guarantee that all PCI read and write operations are
153 If Address > 0x0FFFFFFF, then ASSERT().
155 @param Address Address that encodes the PCI Bus, Device, Function and
157 @param AndData The value to AND with the PCI configuration register.
159 @return The value written back to the PCI configuration register.
169 ASSERT_INVALID_PCI_ADDRESS (Address
);
170 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
174 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
175 value, followed a bitwise inclusive OR with another 8-bit value.
177 Reads the 8-bit PCI configuration register specified by Address, performs a
178 bitwise AND between the read result and the value specified by AndData,
179 performs a bitwise inclusive OR between the result of the AND operation and
180 the value specified by OrData, and writes the result to the 8-bit PCI
181 configuration register specified by Address. The value written to the PCI
182 configuration register is returned. This function must guarantee that all PCI
183 read and write operations are serialized.
185 If Address > 0x0FFFFFFF, then ASSERT().
187 @param Address Address that encodes the PCI Bus, Device, Function and
189 @param AndData The value to AND with the PCI configuration register.
190 @param OrData The value to OR with the result of the AND operation.
192 @return The value written back to the PCI configuration register.
197 PciExpressAndThenOr8 (
203 ASSERT_INVALID_PCI_ADDRESS (Address
);
204 return MmioAndThenOr8 (
205 (UINTN
) GetPciExpressBaseAddress () + Address
,
212 Reads a bit field of a PCI configuration register.
214 Reads the bit field in an 8-bit PCI configuration register. The bit field is
215 specified by the StartBit and the EndBit. The value of the bit field is
218 If Address > 0x0FFFFFFF, then ASSERT().
219 If StartBit is greater than 7, then ASSERT().
220 If EndBit is greater than 7, then ASSERT().
221 If EndBit is less than StartBit, then ASSERT().
223 @param Address PCI configuration register to read.
224 @param StartBit The ordinal of the least significant bit in the bit field.
226 @param EndBit The ordinal of the most significant bit in the bit field.
229 @return The value of the bit field read from the PCI configuration register.
234 PciExpressBitFieldRead8 (
240 ASSERT_INVALID_PCI_ADDRESS (Address
);
241 return MmioBitFieldRead8 (
242 (UINTN
) GetPciExpressBaseAddress () + Address
,
249 Writes a bit field to a PCI configuration register.
251 Writes Value to the bit field of the PCI configuration register. The bit
252 field is specified by the StartBit and the EndBit. All other bits in the
253 destination PCI configuration register are preserved. The new value of the
254 8-bit register is returned.
256 If Address > 0x0FFFFFFF, then ASSERT().
257 If StartBit is greater than 7, then ASSERT().
258 If EndBit is greater than 7, then ASSERT().
259 If EndBit is less than StartBit, then ASSERT().
261 @param Address PCI configuration register to write.
262 @param StartBit The ordinal of the least significant bit in the bit field.
264 @param EndBit The ordinal of the most significant bit in the bit field.
266 @param Value New value of the bit field.
268 @return The value written back to the PCI configuration register.
273 PciExpressBitFieldWrite8 (
280 ASSERT_INVALID_PCI_ADDRESS (Address
);
281 return MmioBitFieldWrite8 (
282 (UINTN
) GetPciExpressBaseAddress () + Address
,
290 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
291 writes the result back to the bit field in the 8-bit port.
293 Reads the 8-bit PCI configuration register specified by Address, performs a
294 bitwise inclusive OR between the read result and the value specified by
295 OrData, and writes the result to the 8-bit PCI configuration register
296 specified by Address. The value written to the PCI configuration register is
297 returned. This function must guarantee that all PCI read and write operations
298 are serialized. Extra left bits in OrData are stripped.
300 If Address > 0x0FFFFFFF, then ASSERT().
301 If StartBit is greater than 7, then ASSERT().
302 If EndBit is greater than 7, then ASSERT().
303 If EndBit is less than StartBit, then ASSERT().
305 @param Address PCI configuration register to write.
306 @param StartBit The ordinal of the least significant bit in the bit field.
308 @param EndBit The ordinal of the most significant bit in the bit field.
310 @param OrData The value to OR with the PCI configuration register.
312 @return The value written back to the PCI configuration register.
317 PciExpressBitFieldOr8 (
324 ASSERT_INVALID_PCI_ADDRESS (Address
);
325 return MmioBitFieldOr8 (
326 (UINTN
) GetPciExpressBaseAddress () + Address
,
334 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
335 AND, and writes the result back to the bit field in the 8-bit register.
337 Reads the 8-bit PCI configuration register specified by Address, performs a
338 bitwise AND between the read result and the value specified by AndData, and
339 writes the result to the 8-bit PCI configuration register specified by
340 Address. The value written to the PCI configuration register is returned.
341 This function must guarantee that all PCI read and write operations are
342 serialized. Extra left bits in AndData are stripped.
344 If Address > 0x0FFFFFFF, then ASSERT().
345 If StartBit is greater than 7, then ASSERT().
346 If EndBit is greater than 7, then ASSERT().
347 If EndBit is less than StartBit, then ASSERT().
349 @param Address PCI configuration register to write.
350 @param StartBit The ordinal of the least significant bit in the bit field.
352 @param EndBit The ordinal of the most significant bit in the bit field.
354 @param AndData The value to AND with the PCI configuration register.
356 @return The value written back to the PCI configuration register.
361 PciExpressBitFieldAnd8 (
368 ASSERT_INVALID_PCI_ADDRESS (Address
);
369 return MmioBitFieldAnd8 (
370 (UINTN
) GetPciExpressBaseAddress () + Address
,
378 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
379 bitwise inclusive OR, and writes the result back to the bit field in the
382 Reads the 8-bit PCI configuration register specified by Address, performs a
383 bitwise AND followed by a bitwise inclusive OR between the read result and
384 the value specified by AndData, and writes the result to the 8-bit PCI
385 configuration register specified by Address. The value written to the PCI
386 configuration register is returned. This function must guarantee that all PCI
387 read and write operations are serialized. Extra left bits in both AndData and
390 If Address > 0x0FFFFFFF, then ASSERT().
391 If StartBit is greater than 7, then ASSERT().
392 If EndBit is greater than 7, then ASSERT().
393 If EndBit is less than StartBit, then ASSERT().
395 @param Address PCI configuration register to write.
396 @param StartBit The ordinal of the least significant bit in the bit field.
398 @param EndBit The ordinal of the most significant bit in the bit field.
400 @param AndData The value to AND with the PCI configuration register.
401 @param OrData The value to OR with the result of the AND operation.
403 @return The value written back to the PCI configuration register.
408 PciExpressBitFieldAndThenOr8 (
416 ASSERT_INVALID_PCI_ADDRESS (Address
);
417 return MmioBitFieldAndThenOr8 (
418 (UINTN
) GetPciExpressBaseAddress () + Address
,
427 Reads a 16-bit PCI configuration register.
429 Reads and returns the 16-bit PCI configuration register specified by Address.
430 This function must guarantee that all PCI read and write operations are
433 If Address > 0x0FFFFFFF, then ASSERT().
434 If Address is not aligned on a 16-bit boundary, then ASSERT().
436 @param Address Address that encodes the PCI Bus, Device, Function and
439 @return The read value from the PCI configuration register.
448 ASSERT_INVALID_PCI_ADDRESS (Address
);
449 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
453 Writes a 16-bit PCI configuration register.
455 Writes the 16-bit PCI configuration register specified by Address with the
456 value specified by Value. Value is returned. This function must guarantee
457 that all PCI read and write operations are serialized.
459 If Address > 0x0FFFFFFF, then ASSERT().
460 If Address is not aligned on a 16-bit boundary, then ASSERT().
462 @param Address Address that encodes the PCI Bus, Device, Function and
464 @param Value The value to write.
466 @return The value written to the PCI configuration register.
476 ASSERT_INVALID_PCI_ADDRESS (Address
);
477 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
481 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
484 Reads the 16-bit PCI configuration register specified by Address, performs a
485 bitwise inclusive OR between the read result and the value specified by
486 OrData, and writes the result to the 16-bit PCI configuration register
487 specified by Address. The value written to the PCI configuration register is
488 returned. This function must guarantee that all PCI read and write operations
491 If Address > 0x0FFFFFFF, then ASSERT().
492 If Address is not aligned on a 16-bit boundary, then ASSERT().
494 @param Address Address that encodes the PCI Bus, Device, Function and
496 @param OrData The value to OR with the PCI configuration register.
498 @return The value written back to the PCI configuration register.
508 ASSERT_INVALID_PCI_ADDRESS (Address
);
509 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
513 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
516 Reads the 16-bit PCI configuration register specified by Address, performs a
517 bitwise AND between the read result and the value specified by AndData, and
518 writes the result to the 16-bit PCI configuration register specified by
519 Address. The value written to the PCI configuration register is returned.
520 This function must guarantee that all PCI read and write operations are
523 If Address > 0x0FFFFFFF, then ASSERT().
524 If Address is not aligned on a 16-bit boundary, then ASSERT().
526 @param Address Address that encodes the PCI Bus, Device, Function and
528 @param AndData The value to AND with the PCI configuration register.
530 @return The value written back to the PCI configuration register.
540 ASSERT_INVALID_PCI_ADDRESS (Address
);
541 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
545 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
546 value, followed a bitwise inclusive OR with another 16-bit value.
548 Reads the 16-bit PCI configuration register specified by Address, performs a
549 bitwise AND between the read result and the value specified by AndData,
550 performs a bitwise inclusive OR between the result of the AND operation and
551 the value specified by OrData, and writes the result to the 16-bit PCI
552 configuration register specified by Address. The value written to the PCI
553 configuration register is returned. This function must guarantee that all PCI
554 read and write operations are serialized.
556 If Address > 0x0FFFFFFF, then ASSERT().
557 If Address is not aligned on a 16-bit boundary, then ASSERT().
559 @param Address Address that encodes the PCI Bus, Device, Function and
561 @param AndData The value to AND with the PCI configuration register.
562 @param OrData The value to OR with the result of the AND operation.
564 @return The value written back to the PCI configuration register.
569 PciExpressAndThenOr16 (
575 ASSERT_INVALID_PCI_ADDRESS (Address
);
576 return MmioAndThenOr16 (
577 (UINTN
) GetPciExpressBaseAddress () + Address
,
584 Reads a bit field of a PCI configuration register.
586 Reads the bit field in a 16-bit PCI configuration register. The bit field is
587 specified by the StartBit and the EndBit. The value of the bit field is
590 If Address > 0x0FFFFFFF, then ASSERT().
591 If Address is not aligned on a 16-bit boundary, then ASSERT().
592 If StartBit is greater than 15, then ASSERT().
593 If EndBit is greater than 15, then ASSERT().
594 If EndBit is less than StartBit, then ASSERT().
596 @param Address PCI configuration register to read.
597 @param StartBit The ordinal of the least significant bit in the bit field.
599 @param EndBit The ordinal of the most significant bit in the bit field.
602 @return The value of the bit field read from the PCI configuration register.
607 PciExpressBitFieldRead16 (
613 ASSERT_INVALID_PCI_ADDRESS (Address
);
614 return MmioBitFieldRead16 (
615 (UINTN
) GetPciExpressBaseAddress () + Address
,
622 Writes a bit field to a PCI configuration register.
624 Writes Value to the bit field of the PCI configuration register. The bit
625 field is specified by the StartBit and the EndBit. All other bits in the
626 destination PCI configuration register are preserved. The new value of the
627 16-bit register is returned.
629 If Address > 0x0FFFFFFF, then ASSERT().
630 If Address is not aligned on a 16-bit boundary, then ASSERT().
631 If StartBit is greater than 15, then ASSERT().
632 If EndBit is greater than 15, then ASSERT().
633 If EndBit is less than StartBit, then ASSERT().
635 @param Address PCI configuration register to write.
636 @param StartBit The ordinal of the least significant bit in the bit field.
638 @param EndBit The ordinal of the most significant bit in the bit field.
640 @param Value New value of the bit field.
642 @return The value written back to the PCI configuration register.
647 PciExpressBitFieldWrite16 (
654 ASSERT_INVALID_PCI_ADDRESS (Address
);
655 return MmioBitFieldWrite16 (
656 (UINTN
) GetPciExpressBaseAddress () + Address
,
664 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
665 writes the result back to the bit field in the 16-bit port.
667 Reads the 16-bit PCI configuration register specified by Address, performs a
668 bitwise inclusive OR between the read result and the value specified by
669 OrData, and writes the result to the 16-bit PCI configuration register
670 specified by Address. The value written to the PCI configuration register is
671 returned. This function must guarantee that all PCI read and write operations
672 are serialized. Extra left bits in OrData are stripped.
674 If Address > 0x0FFFFFFF, then ASSERT().
675 If Address is not aligned on a 16-bit boundary, then ASSERT().
676 If StartBit is greater than 15, then ASSERT().
677 If EndBit is greater than 15, then ASSERT().
678 If EndBit is less than StartBit, then ASSERT().
680 @param Address PCI configuration register to write.
681 @param StartBit The ordinal of the least significant bit in the bit field.
683 @param EndBit The ordinal of the most significant bit in the bit field.
685 @param OrData The value to OR with the PCI configuration register.
687 @return The value written back to the PCI configuration register.
692 PciExpressBitFieldOr16 (
699 ASSERT_INVALID_PCI_ADDRESS (Address
);
700 return MmioBitFieldOr16 (
701 (UINTN
) GetPciExpressBaseAddress () + Address
,
709 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
710 AND, and writes the result back to the bit field in the 16-bit register.
712 Reads the 16-bit PCI configuration register specified by Address, performs a
713 bitwise AND between the read result and the value specified by AndData, and
714 writes the result to the 16-bit PCI configuration register specified by
715 Address. The value written to the PCI configuration register is returned.
716 This function must guarantee that all PCI read and write operations are
717 serialized. Extra left bits in AndData are stripped.
719 If Address > 0x0FFFFFFF, then ASSERT().
720 If Address is not aligned on a 16-bit boundary, then ASSERT().
721 If StartBit is greater than 15, then ASSERT().
722 If EndBit is greater than 15, then ASSERT().
723 If EndBit is less than StartBit, then ASSERT().
725 @param Address PCI configuration register to write.
726 @param StartBit The ordinal of the least significant bit in the bit field.
728 @param EndBit The ordinal of the most significant bit in the bit field.
730 @param AndData The value to AND with the PCI configuration register.
732 @return The value written back to the PCI configuration register.
737 PciExpressBitFieldAnd16 (
744 ASSERT_INVALID_PCI_ADDRESS (Address
);
745 return MmioBitFieldAnd16 (
746 (UINTN
) GetPciExpressBaseAddress () + Address
,
754 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
755 bitwise inclusive OR, and writes the result back to the bit field in the
758 Reads the 16-bit PCI configuration register specified by Address, performs a
759 bitwise AND followed by a bitwise inclusive OR between the read result and
760 the value specified by AndData, and writes the result to the 16-bit PCI
761 configuration register specified by Address. The value written to the PCI
762 configuration register is returned. This function must guarantee that all PCI
763 read and write operations are serialized. Extra left bits in both AndData and
766 If Address > 0x0FFFFFFF, then ASSERT().
767 If Address is not aligned on a 16-bit boundary, then ASSERT().
768 If StartBit is greater than 15, then ASSERT().
769 If EndBit is greater than 15, then ASSERT().
770 If EndBit is less than StartBit, then ASSERT().
772 @param Address PCI configuration register to write.
773 @param StartBit The ordinal of the least significant bit in the bit field.
775 @param EndBit The ordinal of the most significant bit in the bit field.
777 @param AndData The value to AND with the PCI configuration register.
778 @param OrData The value to OR with the result of the AND operation.
780 @return The value written back to the PCI configuration register.
785 PciExpressBitFieldAndThenOr16 (
793 ASSERT_INVALID_PCI_ADDRESS (Address
);
794 return MmioBitFieldAndThenOr16 (
795 (UINTN
) GetPciExpressBaseAddress () + Address
,
804 Reads a 32-bit PCI configuration register.
806 Reads and returns the 32-bit PCI configuration register specified by Address.
807 This function must guarantee that all PCI read and write operations are
810 If Address > 0x0FFFFFFF, then ASSERT().
811 If Address is not aligned on a 32-bit boundary, then ASSERT().
813 @param Address Address that encodes the PCI Bus, Device, Function and
816 @return The read value from the PCI configuration register.
825 ASSERT_INVALID_PCI_ADDRESS (Address
);
826 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
830 Writes a 32-bit PCI configuration register.
832 Writes the 32-bit PCI configuration register specified by Address with the
833 value specified by Value. Value is returned. This function must guarantee
834 that all PCI read and write operations are serialized.
836 If Address > 0x0FFFFFFF, then ASSERT().
837 If Address is not aligned on a 32-bit boundary, then ASSERT().
839 @param Address Address that encodes the PCI Bus, Device, Function and
841 @param Value The value to write.
843 @return The value written to the PCI configuration register.
853 ASSERT_INVALID_PCI_ADDRESS (Address
);
854 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
858 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
861 Reads the 32-bit PCI configuration register specified by Address, performs a
862 bitwise inclusive OR between the read result and the value specified by
863 OrData, and writes the result to the 32-bit PCI configuration register
864 specified by Address. The value written to the PCI configuration register is
865 returned. This function must guarantee that all PCI read and write operations
868 If Address > 0x0FFFFFFF, then ASSERT().
869 If Address is not aligned on a 32-bit boundary, then ASSERT().
871 @param Address Address that encodes the PCI Bus, Device, Function and
873 @param OrData The value to OR with the PCI configuration register.
875 @return The value written back to the PCI configuration register.
885 ASSERT_INVALID_PCI_ADDRESS (Address
);
886 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
890 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
893 Reads the 32-bit PCI configuration register specified by Address, performs a
894 bitwise AND between the read result and the value specified by AndData, and
895 writes the result to the 32-bit PCI configuration register specified by
896 Address. The value written to the PCI configuration register is returned.
897 This function must guarantee that all PCI read and write operations are
900 If Address > 0x0FFFFFFF, then ASSERT().
901 If Address is not aligned on a 32-bit boundary, then ASSERT().
903 @param Address Address that encodes the PCI Bus, Device, Function and
905 @param AndData The value to AND with the PCI configuration register.
907 @return The value written back to the PCI configuration register.
917 ASSERT_INVALID_PCI_ADDRESS (Address
);
918 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
922 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
923 value, followed a bitwise inclusive OR with another 32-bit value.
925 Reads the 32-bit PCI configuration register specified by Address, performs a
926 bitwise AND between the read result and the value specified by AndData,
927 performs a bitwise inclusive OR between the result of the AND operation and
928 the value specified by OrData, and writes the result to the 32-bit PCI
929 configuration register specified by Address. The value written to the PCI
930 configuration register is returned. This function must guarantee that all PCI
931 read and write operations are serialized.
933 If Address > 0x0FFFFFFF, then ASSERT().
934 If Address is not aligned on a 32-bit boundary, then ASSERT().
936 @param Address Address that encodes the PCI Bus, Device, Function and
938 @param AndData The value to AND with the PCI configuration register.
939 @param OrData The value to OR with the result of the AND operation.
941 @return The value written back to the PCI configuration register.
946 PciExpressAndThenOr32 (
952 ASSERT_INVALID_PCI_ADDRESS (Address
);
953 return MmioAndThenOr32 (
954 (UINTN
) GetPciExpressBaseAddress () + Address
,
961 Reads a bit field of a PCI configuration register.
963 Reads the bit field in a 32-bit PCI configuration register. The bit field is
964 specified by the StartBit and the EndBit. The value of the bit field is
967 If Address > 0x0FFFFFFF, then ASSERT().
968 If Address is not aligned on a 32-bit boundary, then ASSERT().
969 If StartBit is greater than 31, then ASSERT().
970 If EndBit is greater than 31, then ASSERT().
971 If EndBit is less than StartBit, then ASSERT().
973 @param Address PCI configuration register to read.
974 @param StartBit The ordinal of the least significant bit in the bit field.
976 @param EndBit The ordinal of the most significant bit in the bit field.
979 @return The value of the bit field read from the PCI configuration register.
984 PciExpressBitFieldRead32 (
990 ASSERT_INVALID_PCI_ADDRESS (Address
);
991 return MmioBitFieldRead32 (
992 (UINTN
) GetPciExpressBaseAddress () + Address
,
999 Writes a bit field to a PCI configuration register.
1001 Writes Value to the bit field of the PCI configuration register. The bit
1002 field is specified by the StartBit and the EndBit. All other bits in the
1003 destination PCI configuration register are preserved. The new value of the
1004 32-bit register is returned.
1006 If Address > 0x0FFFFFFF, then ASSERT().
1007 If Address is not aligned on a 32-bit boundary, then ASSERT().
1008 If StartBit is greater than 31, then ASSERT().
1009 If EndBit is greater than 31, then ASSERT().
1010 If EndBit is less than StartBit, then ASSERT().
1012 @param Address PCI configuration register to write.
1013 @param StartBit The ordinal of the least significant bit in the bit field.
1015 @param EndBit The ordinal of the most significant bit in the bit field.
1017 @param Value New value of the bit field.
1019 @return The value written back to the PCI configuration register.
1024 PciExpressBitFieldWrite32 (
1031 ASSERT_INVALID_PCI_ADDRESS (Address
);
1032 return MmioBitFieldWrite32 (
1033 (UINTN
) GetPciExpressBaseAddress () + Address
,
1041 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1042 writes the result back to the bit field in the 32-bit port.
1044 Reads the 32-bit PCI configuration register specified by Address, performs a
1045 bitwise inclusive OR between the read result and the value specified by
1046 OrData, and writes the result to the 32-bit PCI configuration register
1047 specified by Address. The value written to the PCI configuration register is
1048 returned. This function must guarantee that all PCI read and write operations
1049 are serialized. Extra left bits in OrData are stripped.
1051 If Address > 0x0FFFFFFF, then ASSERT().
1052 If Address is not aligned on a 32-bit boundary, then ASSERT().
1053 If StartBit is greater than 31, then ASSERT().
1054 If EndBit is greater than 31, then ASSERT().
1055 If EndBit is less than StartBit, then ASSERT().
1057 @param Address PCI configuration register to write.
1058 @param StartBit The ordinal of the least significant bit in the bit field.
1060 @param EndBit The ordinal of the most significant bit in the bit field.
1062 @param OrData The value to OR with the PCI configuration register.
1064 @return The value written back to the PCI configuration register.
1069 PciExpressBitFieldOr32 (
1076 ASSERT_INVALID_PCI_ADDRESS (Address
);
1077 return MmioBitFieldOr32 (
1078 (UINTN
) GetPciExpressBaseAddress () + Address
,
1086 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1087 AND, and writes the result back to the bit field in the 32-bit register.
1089 Reads the 32-bit PCI configuration register specified by Address, performs a
1090 bitwise AND between the read result and the value specified by AndData, and
1091 writes the result to the 32-bit PCI configuration register specified by
1092 Address. The value written to the PCI configuration register is returned.
1093 This function must guarantee that all PCI read and write operations are
1094 serialized. Extra left bits in AndData are stripped.
1096 If Address > 0x0FFFFFFF, then ASSERT().
1097 If Address is not aligned on a 32-bit boundary, then ASSERT().
1098 If StartBit is greater than 31, then ASSERT().
1099 If EndBit is greater than 31, then ASSERT().
1100 If EndBit is less than StartBit, then ASSERT().
1102 @param Address PCI configuration register to write.
1103 @param StartBit The ordinal of the least significant bit in the bit field.
1105 @param EndBit The ordinal of the most significant bit in the bit field.
1107 @param AndData The value to AND with the PCI configuration register.
1109 @return The value written back to the PCI configuration register.
1114 PciExpressBitFieldAnd32 (
1121 ASSERT_INVALID_PCI_ADDRESS (Address
);
1122 return MmioBitFieldAnd32 (
1123 (UINTN
) GetPciExpressBaseAddress () + Address
,
1131 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1132 bitwise inclusive OR, and writes the result back to the bit field in the
1135 Reads the 32-bit PCI configuration register specified by Address, performs a
1136 bitwise AND followed by a bitwise inclusive OR between the read result and
1137 the value specified by AndData, and writes the result to the 32-bit PCI
1138 configuration register specified by Address. The value written to the PCI
1139 configuration register is returned. This function must guarantee that all PCI
1140 read and write operations are serialized. Extra left bits in both AndData and
1141 OrData are stripped.
1143 If Address > 0x0FFFFFFF, then ASSERT().
1144 If Address is not aligned on a 32-bit boundary, then ASSERT().
1145 If StartBit is greater than 31, then ASSERT().
1146 If EndBit is greater than 31, then ASSERT().
1147 If EndBit is less than StartBit, then ASSERT().
1149 @param Address PCI configuration register to write.
1150 @param StartBit The ordinal of the least significant bit in the bit field.
1152 @param EndBit The ordinal of the most significant bit in the bit field.
1154 @param AndData The value to AND with the PCI configuration register.
1155 @param OrData The value to OR with the result of the AND operation.
1157 @return The value written back to the PCI configuration register.
1162 PciExpressBitFieldAndThenOr32 (
1170 ASSERT_INVALID_PCI_ADDRESS (Address
);
1171 return MmioBitFieldAndThenOr32 (
1172 (UINTN
) GetPciExpressBaseAddress () + Address
,
1181 Reads a range of PCI configuration registers into a caller supplied buffer.
1183 Reads the range of PCI configuration registers specified by StartAddress and
1184 Size into the buffer specified by Buffer. This function only allows the PCI
1185 configuration registers from a single PCI function to be read. Size is
1186 returned. When possible 32-bit PCI configuration read cycles are used to read
1187 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1188 and 16-bit PCI configuration read cycles may be used at the beginning and the
1191 If StartAddress > 0x0FFFFFFF, then ASSERT().
1192 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1193 If Size > 0 and Buffer is NULL, then ASSERT().
1195 @param StartAddress Starting address that encodes the PCI Bus, Device,
1196 Function and Register.
1197 @param Size Size in bytes of the transfer.
1198 @param Buffer Pointer to a buffer receiving the data read.
1205 PciExpressReadBuffer (
1206 IN UINTN StartAddress
,
1213 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1214 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1220 ASSERT (Buffer
!= NULL
);
1223 // Save Size for return
1227 if ((StartAddress
& 1) != 0) {
1229 // Read a byte if StartAddress is byte aligned
1231 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1232 StartAddress
+= sizeof (UINT8
);
1233 Size
-= sizeof (UINT8
);
1234 Buffer
= (UINT8
*)Buffer
+ 1;
1237 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1239 // Read a word if StartAddress is word aligned
1241 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1242 StartAddress
+= sizeof (UINT16
);
1243 Size
-= sizeof (UINT16
);
1244 Buffer
= (UINT16
*)Buffer
+ 1;
1247 while (Size
>= sizeof (UINT32
)) {
1249 // Read as many double words as possible
1251 *(volatile UINT32
*)Buffer
= PciExpressRead32 (StartAddress
);
1252 StartAddress
+= sizeof (UINT32
);
1253 Size
-= sizeof (UINT32
);
1254 Buffer
= (UINT32
*)Buffer
+ 1;
1257 if (Size
>= sizeof (UINT16
)) {
1259 // Read the last remaining word if exist
1261 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1262 StartAddress
+= sizeof (UINT16
);
1263 Size
-= sizeof (UINT16
);
1264 Buffer
= (UINT16
*)Buffer
+ 1;
1267 if (Size
>= sizeof (UINT8
)) {
1269 // Read the last remaining byte if exist
1271 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1278 Copies the data in a caller supplied buffer to a specified range of PCI
1279 configuration space.
1281 Writes the range of PCI configuration registers specified by StartAddress and
1282 Size from the buffer specified by Buffer. This function only allows the PCI
1283 configuration registers from a single PCI function to be written. Size is
1284 returned. When possible 32-bit PCI configuration write cycles are used to
1285 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1286 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1287 and the end of the range.
1289 If StartAddress > 0x0FFFFFFF, then ASSERT().
1290 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1291 If Size > 0 and Buffer is NULL, then ASSERT().
1293 @param StartAddress Starting address that encodes the PCI Bus, Device,
1294 Function and Register.
1295 @param Size Size in bytes of the transfer.
1296 @param Buffer Pointer to a buffer containing the data to write.
1303 PciExpressWriteBuffer (
1304 IN UINTN StartAddress
,
1311 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1312 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1318 ASSERT (Buffer
!= NULL
);
1321 // Save Size for return
1325 if ((StartAddress
& 1) != 0) {
1327 // Write a byte if StartAddress is byte aligned
1329 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1330 StartAddress
+= sizeof (UINT8
);
1331 Size
-= sizeof (UINT8
);
1332 Buffer
= (UINT8
*)Buffer
+ 1;
1335 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1337 // Write a word if StartAddress is word aligned
1339 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1340 StartAddress
+= sizeof (UINT16
);
1341 Size
-= sizeof (UINT16
);
1342 Buffer
= (UINT16
*)Buffer
+ 1;
1345 while (Size
>= sizeof (UINT32
)) {
1347 // Write as many double words as possible
1349 PciExpressWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1350 StartAddress
+= sizeof (UINT32
);
1351 Size
-= sizeof (UINT32
);
1352 Buffer
= (UINT32
*)Buffer
+ 1;
1355 if (Size
>= sizeof (UINT16
)) {
1357 // Write the last remaining word if exist
1359 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1360 StartAddress
+= sizeof (UINT16
);
1361 Size
-= sizeof (UINT16
);
1362 Buffer
= (UINT16
*)Buffer
+ 1;
1365 if (Size
>= sizeof (UINT8
)) {
1367 // Write the last remaining byte if exist
1369 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);