EdkCompatibilityPkg/Sample/Tools/Source/GenPage/VirtualMemory.h

   1 /*++
   2
   3 Copyright 2006 - 2007, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13   VirtualMemory.h
  14
  15 Abstract:
  16
  17   x64 Long Mode Virtual Memory Management Definitions
  18
  19   References:
  20     1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
  21     2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
  22     3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
  23     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
  24 --*/
  25
  26 #ifndef _VIRTUAL_MEMORY_H_
  27 #define _VIRTUAL_MEMORY_H_
  28
  29 #include "Tiano.h"
  30
  31 #pragma pack(1)
  32
  33 //
  34 // Page-Map Level-4 Offset (PML4) and
  35 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  36 //
  37
  38 typedef union {
  39   struct {
  40     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  41     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  42     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  43     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  44     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  45     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  46     UINT64  Reserved:1;               // Reserved
  47     UINT64  MustBeZero:2;             // Must Be Zero
  48     UINT64  Available:3;              // Available for use by system software
  49     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  50     UINT64  AvabilableHigh:11;        // Available for use by system software
  51     UINT64  Nx:1;                     // No Execute bit
  52   } Bits;
  53   UINT64    Uint64;
  54 } X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;
  55
  56 //
  57 // Page-Directory Offset 4K
  58 //
  59 typedef union {
  60   struct {
  61     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  62     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  63     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  64     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  65     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  66     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  67     UINT64  Reserved:1;               // Reserved
  68     UINT64  MustBeZero:1;             // Must Be Zero
  69     UINT64  Reserved2:1;              // Reserved
  70     UINT64  Available:3;              // Available for use by system software
  71     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  72     UINT64  AvabilableHigh:11;        // Available for use by system software
  73     UINT64  Nx:1;                     // No Execute bit
  74   } Bits;
  75   UINT64    Uint64;
  76 } X64_PAGE_DIRECTORY_ENTRY_4K;
  77
  78 //
  79 // Page Table Entry 4K
  80 //
  81 typedef union {
  82   struct {
  83     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  84     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  85     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  86     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  87     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  88     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  89     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  90     UINT64  PAT:1;                    // 0 = Ignore Page Attribute Table
  91     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  92     UINT64  Available:3;              // Available for use by system software
  93     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  94     UINT64  AvabilableHigh:11;        // Available for use by system software
  95     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  96   } Bits;
  97   UINT64    Uint64;
  98 } X64_PAGE_TABLE_ENTRY_4K;
  99
 100
 101 //
 102 // Page Table Entry 2MB
 103 //
 104 typedef union {
 105   struct {
 106     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 107     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 108     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 109     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 110     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 111     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 112     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 113     UINT64  MustBe1:1;                // Must be 1
 114     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 115     UINT64  Available:3;              // Available for use by system software
 116     UINT64  PAT:1;                    //
 117     UINT64  MustBeZero:8;             // Must be zero;
 118     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
 119     UINT64  AvabilableHigh:11;        // Available for use by system software
 120     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 121   } Bits;
 122   UINT64    Uint64;
 123 } X64_PAGE_TABLE_ENTRY_2M;
 124
 125 #pragma pack()
 126
 127 #endif