remove ifdef for debuglevel
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Ehci / Dxe / Ehci.h
1 /*++
2
3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module Name:
13
14 Ehci.h
15
16 Abstract:
17
18
19 Revision History
20 --*/
21
22 #ifndef _EHCI_H
23 #define _EHCI_H
24
25 //
26 // Universal Host Controller Interface data structures and defines
27 //
28 #include <IndustryStandard/pci22.h>
29
30 extern UINTN gEHCDebugLevel;
31 extern UINTN gEHCErrorLevel;
32
33 #define STALL_1_MACRO_SECOND 1
34 #define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND
35 #define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND
36
37 #define SETUP_PACKET_PID_CODE 0x02
38 #define INPUT_PACKET_PID_CODE 0x01
39 #define OUTPUT_PACKET_PID_CODE 0x0
40
41 #define ITD_SELECT_TYPE 0x0
42 #define QH_SELECT_TYPE 0x01
43 #define SITD_SELECT_TYPE 0x02
44 #define FSTN_SELECT_TYPE 0x03
45
46 #define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND
47 #define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND
48 #define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND
49 #define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND
50 #define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND
51 #define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND
52
53 #define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */
54
55 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1
56
57 #define EHCI_MIN_PACKET_SIZE 8
58 #define EHCI_MAX_PACKET_SIZE 1024
59 #define EHCI_MAX_FRAME_LIST_LENGTH 1024
60 #define EHCI_BLOCK_SIZE_WITH_TT 64
61 #define EHCI_BLOCK_SIZE 512
62 #define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)
63
64 #define NAK_COUNT_RELOAD 3
65 #define QTD_ERROR_COUNTER 1
66 #define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1
67
68 #define QTD_STATUS_ACTIVE 0x80
69 #define QTD_STATUS_HALTED 0x40
70 #define QTD_STATUS_BUFFER_ERR 0x20
71 #define QTD_STATUS_BABBLE_ERR 0x10
72 #define QTD_STATUS_TRANSACTION_ERR 0x08
73 #define QTD_STATUS_DO_STOP_SPLIT 0x02
74 #define QTD_STATUS_DO_START_SPLIT 0
75 #define QTD_STATUS_DO_PING 0x01
76 #define QTD_STATUS_DO_OUT 0
77
78 #define DATA0 0
79 #define DATA1 1
80
81 #define MICRO_FRAME_0_CHANNEL 0x01
82 #define MICRO_FRAME_1_CHANNEL 0x02
83 #define MICRO_FRAME_2_CHANNEL 0x04
84 #define MICRO_FRAME_3_CHANNEL 0x08
85 #define MICRO_FRAME_4_CHANNEL 0x10
86 #define MICRO_FRAME_5_CHANNEL 0x20
87 #define MICRO_FRAME_6_CHANNEL 0x40
88 #define MICRO_FRAME_7_CHANNEL 0x80
89
90 #define CONTROL_TRANSFER 0x01
91 #define BULK_TRANSFER 0x02
92 #define SYNC_INTERRUPT_TRANSFER 0x04
93 #define ASYNC_INTERRUPT_TRANSFER 0x08
94 #define SYNC_ISOCHRONOUS_TRANSFER 0x10
95 #define ASYNC_ISOCHRONOUS_TRANSFER 0x20
96
97
98 //
99 // Enhanced Host Controller Registers definitions
100 //
101 extern UINT32 mUsbCapabilityLen;
102 extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;
103 extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;
104
105 #define USBCMD 0x0 /* Command Register Offset 00-03h */
106 #define USBCMD_RS 0x01 /* Run / Stop */
107 #define USBCMD_HCRESET 0x02 /* Host controller reset */
108 #define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */
109 #define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */
110 #define USBCMD_PSE 0x10 /* Periodic schedule enable */
111 #define USBCMD_ASE 0x20 /* Asynchronous schedule enable */
112 #define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */
113
114 #define USBSTS 0x04 /* Statue Register Offset 04-07h */
115 #define USBSTS_HSE 0x10 /* Host system error */
116 #define USBSTS_IAA 0x20 /* Interrupt on async advance */
117 #define USBSTS_HCH 0x1000 /* Host controller halted */
118 #define USBSTS_PSS 0x4000 /* Periodic schedule status */
119 #define USBSTS_ASS 0x8000 /* Asynchronous schedule status */
120
121 #define USBINTR 0x08 /* Command Register Offset 08-0bh */
122
123 #define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */
124
125 #define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */
126
127 #define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */
128
129 #define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */
130
131 #define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */
132 #define CONFIGFLAG_CF 0x01 /* Configure Flag */
133
134 #define PORTSC 0x44 /* Port Status/Control Offset 44-47h */
135 #define PORTSC_CCS 0x01 /* Current Connect Status*/
136 #define PORTSC_CSC 0x02 /* Connect Status Change */
137 #define PORTSC_PED 0x04 /* Port Enable / Disable */
138 #define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */
139 #define PORTSC_OCA 0x10 /* Over current Active */
140 #define PORTSC_OCC 0x20 /* Over current Change */
141 #define PORTSC_FPR 0x40 /* Force Port Resume */
142 #define PORTSC_SUSP 0x80 /* Port Suspend State */
143 #define PORTSC_PR 0x100 /* Port Reset */
144 #define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */
145 #define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */
146 #define PORTSC_PP 0x1000 /* Port Power */
147 #define PORTSC_PO 0x2000 /* Port Owner */
148
149 #define CAPLENGTH 0 /* Capability Register Length 00h */
150
151 #define HCIVERSION 0x02 /* Interface Version Number 02-03h */
152
153 #define HCSPARAMS 0x04 /* Structural Parameters 04-07h */
154 #define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */
155
156 #define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */
157 #define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */
158 #define HCCP_PFLF 0x02 /* Programmable Frame List Flag */
159 #define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */
160
161 #define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */
162
163 #define CLASSC 0x09 /* Class Code 09-0bh */
164
165 #define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */
166
167 #define SBRN 0x60 /* Serial Bus Release Number 60h */
168
169 #define FLADJ 0x61 /* Frame Length Adjustment Register 61h */
170
171 #define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */
172
173 //
174 // PCI Configuration Registers
175 //
176 #define EHCI_PCI_CLASSC 0x09
177 #define EHCI_PCI_MEMORY_BASE 0x10
178
179 //
180 // Memory Offset Registers
181 //
182 #define EHCI_MEMORY_CAPLENGTH 0x0
183 #define EHCI_MEMORY_CONFIGFLAG 0x40
184
185 //
186 // USB Base Class Code,Sub-Class Code and Programming Interface
187 //
188 #define PCI_CLASSC_PI_EHCI 0x20
189
190 #define SETUP_PACKET_ID 0x2D
191 #define INPUT_PACKET_ID 0x69
192 #define OUTPUT_PACKET_ID 0xE1
193 #define ERROR_PACKET_ID 0x55
194
195 #define bit(a) 1 << (a)
196
197 #define GET_0B_TO_31B(Addr) (((UINTN) Addr) & (0xffffffff))
198 #define GET_32B_TO_63B(Addr) ((((UINTN) Addr) >> 32) & (0xffffffff))
199
200
201 //
202 // Ehci Data and Ctrl Structures
203 //
204 #pragma pack(1)
205
206 typedef struct {
207 UINT8 PI;
208 UINT8 SubClassCode;
209 UINT8 BaseCode;
210 } USB_CLASSC;
211
212 typedef struct {
213 UINT32 NextQtdTerminate : 1;
214 UINT32 Rsvd1 : 4;
215 UINT32 NextQtdPointer : 27;
216
217 UINT32 AltNextQtdTerminate : 1;
218 UINT32 Rsvd2 : 4;
219 UINT32 AltNextQtdPointer : 27;
220
221 UINT32 Status : 8;
222 UINT32 PidCode : 2;
223 UINT32 ErrorCount : 2;
224 UINT32 CurrentPage : 3;
225 UINT32 InterruptOnComplete : 1;
226 UINT32 TotalBytes : 15;
227 UINT32 DataToggle : 1;
228
229 UINT32 CurrentOffset : 12;
230 UINT32 BufferPointer0 : 20;
231
232 UINT32 Rsvd3 : 12;
233 UINT32 BufferPointer1 : 20;
234
235 UINT32 Rsvd4 : 12;
236 UINT32 BufferPointer2 : 20;
237
238 UINT32 Rsvd5 : 12;
239 UINT32 BufferPointer3 : 20;
240
241 UINT32 Rsvd6 : 12;
242 UINT32 BufferPointer4 : 20;
243
244 UINT32 ExtBufferPointer0;
245 UINT32 ExtBufferPointer1;
246 UINT32 ExtBufferPointer2;
247 UINT32 ExtBufferPointer3;
248 UINT32 ExtBufferPointer4;
249 } EHCI_QTD_HW;
250
251 typedef struct {
252 UINT32 QhTerminate : 1;
253 UINT32 SelectType : 2;
254 UINT32 Rsvd1 : 2;
255 UINT32 QhHorizontalPointer : 27;
256
257 UINT32 DeviceAddr : 7;
258 UINT32 Inactive : 1;
259 UINT32 EndpointNum : 4;
260 UINT32 EndpointSpeed : 2;
261 UINT32 DataToggleControl : 1;
262 UINT32 HeadReclamationFlag : 1;
263 UINT32 MaxPacketLen : 11;
264 UINT32 ControlEndpointFlag : 1;
265 UINT32 NakCountReload : 4;
266
267 UINT32 InerruptScheduleMask : 8;
268 UINT32 SplitComletionMask : 8;
269 UINT32 HubAddr : 7;
270 UINT32 PortNum : 7;
271 UINT32 Multiplier : 2;
272
273 UINT32 Rsvd2 : 5;
274 UINT32 CurrentQtdPointer : 27;
275
276 UINT32 NextQtdTerminate : 1;
277 UINT32 Rsvd3 : 4;
278 UINT32 NextQtdPointer : 27;
279
280 UINT32 AltNextQtdTerminate : 1;
281 UINT32 NakCount : 4;
282 UINT32 AltNextQtdPointer : 27;
283
284 UINT32 Status : 8;
285 UINT32 PidCode : 2;
286 UINT32 ErrorCount : 2;
287 UINT32 CurrentPage : 3;
288 UINT32 InterruptOnComplete : 1;
289 UINT32 TotalBytes : 15;
290 UINT32 DataToggle : 1;
291
292 UINT32 CurrentOffset : 12;
293 UINT32 BufferPointer0 : 20;
294
295 UINT32 CompleteSplitMask : 8;
296 UINT32 Rsvd4 : 4;
297 UINT32 BufferPointer1 : 20;
298
299 UINT32 FrameTag : 5;
300 UINT32 SplitBytes : 7;
301 UINT32 BufferPointer2 : 20;
302
303 UINT32 Rsvd5 : 12;
304 UINT32 BufferPointer3 : 20;
305
306 UINT32 Rsvd6 : 12;
307 UINT32 BufferPointer4 : 20;
308
309 UINT32 ExtBufferPointer0;
310 UINT32 ExtBufferPointer1;
311 UINT32 ExtBufferPointer2;
312 UINT32 ExtBufferPointer3;
313 UINT32 ExtBufferPointer4;
314 } EHCI_QH_HW;
315
316 typedef struct {
317 UINT32 LinkTerminate : 1;
318 UINT32 SelectType : 2;
319 UINT32 Rsvd : 2;
320 UINT32 LinkPointer : 27;
321 } FRAME_LIST_ENTRY;
322
323 #pragma pack()
324
325 typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY;
326 typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY;
327 typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST;
328
329 typedef struct _EHCI_QTD_ENTITY {
330 EHCI_QTD_HW Qtd;
331 UINT32 TotalBytes;
332 UINT32 StaticTotalBytes;
333 UINT32 StaticCurrentOffset;
334 EHCI_QTD_ENTITY *Prev;
335 EHCI_QTD_ENTITY *Next;
336 EHCI_QTD_ENTITY *AltNext;
337 EHCI_QH_ENTITY *SelfQh;
338 } EHCI_QTD_ENTITY;
339
340 typedef struct _EHCI_QH_ENTITY {
341 EHCI_QH_HW Qh;
342 EHCI_QH_ENTITY *Next;
343 EHCI_QH_ENTITY *Prev;
344 EHCI_QTD_ENTITY *FirstQtdPtr;
345 EHCI_QTD_ENTITY *LastQtdPtr;
346 EHCI_QTD_ENTITY *AltQtdPtr;
347 UINTN Interval;
348 UINT8 TransferType;
349 } EHCI_QH_ENTITY;
350
351 #define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)
352 #define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)
353
354
355 //
356 // Ehci Managment Structures
357 //
358 #define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
359
360 #define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')
361
362 typedef struct _LIST_HEAD {
363 struct _LIST_HEAD *pre;
364 struct _LIST_HEAD *next;
365 } LIST_HEAD;
366
367 typedef struct _EHCI_ASYNC_REQUEST {
368 UINT8 TransferType;
369 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;
370 VOID *Context;
371 EHCI_ASYNC_REQUEST *Prev;
372 EHCI_ASYNC_REQUEST *Next;
373 EHCI_QH_ENTITY *QhPtr;
374 } EHCI_ASYNC_REQUEST;
375
376 typedef struct _MEMORY_MANAGE_HEADER {
377 UINT8 *BitArrayPtr;
378 UINTN BitArraySizeInBytes;
379 UINT8 *MemoryBlockPtr;
380 UINTN MemoryBlockSizeInBytes;
381 VOID *Mapping;
382 struct _MEMORY_MANAGE_HEADER *Next;
383 } MEMORY_MANAGE_HEADER;
384
385 typedef struct _USB2_HC_DEV {
386 UINTN Signature;
387 EFI_PCI_IO_PROTOCOL *PciIo;
388 EFI_USB2_HC_PROTOCOL Usb2Hc;
389 UINTN PeriodicFrameListLength;
390 VOID *PeriodicFrameListBuffer;
391 VOID *PeriodicFrameListMap;
392 VOID *AsyncList;
393 EHCI_ASYNC_REQUEST *AsyncRequestList;
394 EFI_EVENT AsyncRequestEvent;
395 EFI_UNICODE_STRING_TABLE *ControllerNameTable;
396 MEMORY_MANAGE_HEADER *MemoryHeader;
397 UINT8 Is64BitCapable;
398 UINT32 High32BitAddr;
399 } USB2_HC_DEV;
400
401
402 //
403 // Internal Functions Declaration
404 //
405
406 //
407 // EhciMem Functions
408 //
409 EFI_STATUS
410 CreateMemoryBlock (
411 IN USB2_HC_DEV *HcDev,
412 OUT MEMORY_MANAGE_HEADER **MemoryHeader,
413 IN UINTN MemoryBlockSizeInPages
414 )
415 /*++
416
417 Routine Description:
418
419 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,
420 and use PciIo->Map to map the common buffer for Bus Master Read/Write.
421
422 Arguments:
423
424 HcDev - USB2_HC_DEV
425 MemoryHeader - MEMORY_MANAGE_HEADER to output
426 MemoryBlockSizeInPages - MemoryBlockSizeInPages
427
428 Returns:
429
430 EFI_SUCCESS Success
431 EFI_OUT_OF_RESOURCES Fail for no resources
432 EFI_UNSUPPORTED Unsupported currently
433
434 --*/
435 ;
436
437 EFI_STATUS
438 FreeMemoryHeader (
439 IN USB2_HC_DEV *HcDev,
440 IN MEMORY_MANAGE_HEADER *MemoryHeader
441 )
442 /*++
443
444 Routine Description:
445
446 Free Memory Header
447
448 Arguments:
449
450 HcDev - USB2_HC_DEV
451 MemoryHeader - MemoryHeader to be freed
452
453 Returns:
454
455 EFI_SUCCESS Success
456 EFI_INVALID_PARAMETER Parameter is error
457
458 --*/
459 ;
460
461 VOID
462 InsertMemoryHeaderToList (
463 IN MEMORY_MANAGE_HEADER *MemoryHeader,
464 IN MEMORY_MANAGE_HEADER *NewMemoryHeader
465 )
466 /*++
467
468 Routine Description:
469
470 Insert Memory Header To List
471
472 Arguments:
473
474 MemoryHeader - MEMORY_MANAGE_HEADER
475 NewMemoryHeader - MEMORY_MANAGE_HEADER
476
477 Returns:
478
479 VOID
480
481 --*/
482 ;
483
484 EFI_STATUS
485 AllocMemInMemoryBlock (
486 IN MEMORY_MANAGE_HEADER *MemoryHeader,
487 OUT VOID **Pool,
488 IN UINTN NumberOfMemoryUnit
489 )
490 /*++
491
492 Routine Description:
493
494 Alloc Memory In MemoryBlock
495
496 Arguments:
497
498 MemoryHeader - MEMORY_MANAGE_HEADER
499 Pool - Place to store pointer to memory
500 NumberOfMemoryUnit - Number Of Memory Unit
501
502 Returns:
503
504 EFI_SUCCESS Success
505 EFI_NOT_FOUND Can't find the free memory
506
507 --*/
508 ;
509
510 BOOLEAN
511 IsMemoryBlockEmptied (
512 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr
513 )
514 /*++
515
516 Routine Description:
517
518 Is Memory Block Emptied
519
520 Arguments:
521
522 MemoryHeaderPtr - MEMORY_MANAGE_HEADER
523
524 Returns:
525
526 TRUE Empty
527 FALSE Not Empty
528
529 --*/
530 ;
531
532 VOID
533 DelinkMemoryBlock (
534 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,
535 IN MEMORY_MANAGE_HEADER *NeedFreeMemoryHeader
536 )
537 /*++
538
539 Routine Description:
540
541 Delink Memory Block
542
543 Arguments:
544
545 FirstMemoryHeader - MEMORY_MANAGE_HEADER
546 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER
547
548 Returns:
549
550 VOID
551
552 --*/
553 ;
554
555 EFI_STATUS
556 InitialMemoryManagement (
557 IN USB2_HC_DEV *HcDev
558 )
559 /*++
560
561 Routine Description:
562
563 Initialize Memory Management
564
565 Arguments:
566
567 HcDev - USB2_HC_DEV
568
569 Returns:
570
571 EFI_SUCCESS Success
572 EFI_DEVICE_ERROR Fail
573
574 --*/
575 ;
576
577 EFI_STATUS
578 DeinitialMemoryManagement (
579 IN USB2_HC_DEV *HcDev
580 )
581 /*++
582
583 Routine Description:
584
585 Deinitialize Memory Management
586
587 Arguments:
588
589 HcDev - USB2_HC_DEV
590
591 Returns:
592
593 EFI_SUCCESS Success
594 EFI_DEVICE_ERROR Fail
595
596 --*/
597 ;
598
599 EFI_STATUS
600 EhciAllocatePool (
601 IN USB2_HC_DEV *HcDev,
602 OUT UINT8 **Pool,
603 IN UINTN AllocSize
604 )
605 /*++
606
607 Routine Description:
608
609 Ehci Allocate Pool
610
611 Arguments:
612
613 HcDev - USB2_HC_DEV
614 Pool - Place to store pointer to the memory buffer
615 AllocSize - Alloc Size
616
617 Returns:
618
619 EFI_SUCCESS Success
620 EFI_DEVICE_ERROR Fail
621
622 --*/
623 ;
624
625 VOID
626 EhciFreePool (
627 IN USB2_HC_DEV *HcDev,
628 IN UINT8 *Pool,
629 IN UINTN AllocSize
630 )
631 /*++
632
633 Routine Description:
634
635 Uhci Free Pool
636
637 Arguments:
638
639 HcDev - USB_HC_DEV
640 Pool - Pool to free
641 AllocSize - Pool size
642
643 Returns:
644
645 VOID
646
647 --*/
648 ;
649
650 //
651 // EhciReg Functions
652 //
653 EFI_STATUS
654 ReadEhcCapabiltiyReg (
655 IN USB2_HC_DEV *HcDev,
656 IN UINT32 CapabiltiyRegAddr,
657 IN OUT UINT32 *Data
658 )
659 /*++
660
661 Routine Description:
662
663 Read Ehc Capabitlity register
664
665 Arguments:
666
667 HcDev - USB2_HC_DEV
668 CapabiltiyRegAddr - Ehc Capability register address
669 Data - A pointer to data read from register
670
671 Returns:
672
673 EFI_SUCCESS Success
674 EFI_DEVICE_ERROR Fail
675
676 --*/
677 ;
678
679 EFI_STATUS
680 ReadEhcOperationalReg (
681 IN USB2_HC_DEV *HcDev,
682 IN UINT32 OperationalRegAddr,
683 IN OUT UINT32 *Data
684 )
685 /*++
686
687 Routine Description:
688
689 Read Ehc Operation register
690
691 Arguments:
692
693 HcDev - USB2_HC_DEV
694 OperationalRegAddr - Ehc Operation register address
695 Data - A pointer to data read from register
696
697 Returns:
698
699 EFI_SUCCESS Success
700 EFI_DEVICE_ERROR Fail
701
702 --*/
703 ;
704
705 EFI_STATUS
706 WriteEhcOperationalReg (
707 IN USB2_HC_DEV *HcDev,
708 IN UINT32 OperationalRegAddr,
709 IN UINT32 Data
710 )
711 /*++
712
713 Routine Description:
714
715 Write Ehc Operation register
716
717 Arguments:
718
719 HcDev - USB2_HC_DEV
720 OperationalRegAddr - Ehc Operation register address
721 Data - 32bit write to register
722
723 Returns:
724
725 EFI_SUCCESS Success
726 EFI_DEVICE_ERROR Fail
727
728 --*/
729 ;
730
731 EFI_STATUS
732 SetEhcDoorbell (
733 IN USB2_HC_DEV *HcDev
734 )
735 /*++
736
737 Routine Description:
738
739 Set Ehc door bell bit
740
741 Arguments:
742
743 HcDev - USB2_HC_DEV
744
745 Returns:
746
747 EFI_SUCCESS Success
748 EFI_DEVICE_ERROR Fail
749
750 --*/
751 ;
752
753 EFI_STATUS
754 SetFrameListLen (
755 IN USB2_HC_DEV *HcDev,
756 IN UINTN Length
757 )
758 /*++
759
760 Routine Description:
761
762 Set the length of Frame List
763
764 Arguments:
765
766 HcDev - USB2_HC_DEV
767 Length - the required length of frame list
768
769 Returns:
770
771 EFI_SUCCESS Success
772 EFI_INVALID_PARAMETER Invalid parameter
773 EFI_DEVICE_ERROR Fail
774
775 --*/
776 ;
777
778 BOOLEAN
779 IsFrameListProgrammable (
780 IN USB2_HC_DEV *HcDev
781 )
782 /*++
783
784 Routine Description:
785
786 Whether frame list is programmable
787
788 Arguments:
789
790 HcDev - USB2_HC_DEV
791
792 Returns:
793
794 TRUE Programmable
795 FALSE Unprogrammable
796
797 --*/
798 ;
799
800 BOOLEAN
801 IsPeriodicScheduleEnabled (
802 IN USB2_HC_DEV *HcDev
803 )
804 /*++
805
806 Routine Description:
807
808 Whether periodic schedule is enabled
809
810 Arguments:
811
812 HcDev - USB2_HC_DEV
813
814 Returns:
815
816 TRUE Enabled
817 FALSE Disabled
818
819 --*/
820 ;
821
822 BOOLEAN
823 IsAsyncScheduleEnabled (
824 IN USB2_HC_DEV *HcDev
825 )
826 /*++
827
828 Routine Description:
829
830 Whether asynchronous schedule is enabled
831
832 Arguments:
833
834 HcDev - USB2_HC_DEV
835
836 Returns:
837
838 TRUE Enabled
839 FALSE Disabled
840
841 --*/
842 ;
843
844 BOOLEAN
845 IsEhcPortEnabled (
846 IN USB2_HC_DEV *HcDev,
847 IN UINT8 PortNum
848 )
849 /*++
850
851 Routine Description:
852
853 Whether port is enabled
854
855 Arguments:
856
857 HcDev - USB2_HC_DEV
858
859 Returns:
860
861 TRUE Enabled
862 FALSE Disabled
863
864 --*/
865 ;
866
867 BOOLEAN
868 IsEhcReseted (
869 IN USB2_HC_DEV *HcDev
870 )
871 /*++
872
873 Routine Description:
874
875 Whether Ehc is halted
876
877 Arguments:
878
879 HcDev - USB2_HC_DEV
880
881 Returns:
882
883 TRUE Reseted
884 FALSE Unreseted
885
886 --*/
887 ;
888
889 BOOLEAN
890 IsEhcHalted (
891 IN USB2_HC_DEV *HcDev
892 )
893 /*++
894
895 Routine Description:
896
897 Whether Ehc is halted
898
899 Arguments:
900
901 HcDev - USB2_HC_DEV
902
903 Returns:
904
905 TRUE Halted
906 FALSE Not halted
907
908 --*/
909 ;
910
911 BOOLEAN
912 IsEhcSysError (
913 IN USB2_HC_DEV *HcDev
914 )
915 /*++
916
917 Routine Description:
918
919 Whether Ehc is system error
920
921 Arguments:
922
923 HcDev - USB2_HC_DEV
924
925 Returns:
926
927 TRUE System error
928 FALSE No system error
929
930 --*/
931 ;
932
933 BOOLEAN
934 IsHighSpeedDevice (
935 IN EFI_USB2_HC_PROTOCOL *This,
936 IN UINT8 PortNum
937 )
938 /*++
939
940 Routine Description:
941
942 Whether high speed device attached
943
944 Arguments:
945
946 HcDev - USB2_HC_DEV
947
948 Returns:
949
950 TRUE High speed
951 FALSE Full speed
952
953 --*/
954 ;
955
956 EFI_STATUS
957 WaitForEhcReset (
958 IN USB2_HC_DEV *HcDev,
959 IN UINTN Timeout
960 )
961 /*++
962
963 Routine Description:
964
965 wait for Ehc reset or timeout
966
967 Arguments:
968
969 HcDev - USB2_HC_DEV
970 Timeout - timeout threshold
971
972 Returns:
973
974 EFI_SUCCESS Success
975 EFI_TIMEOUT Timeout
976
977 --*/
978 ;
979
980 EFI_STATUS
981 WaitForEhcHalt (
982 IN USB2_HC_DEV *HcDev,
983 IN UINTN Timeout
984 )
985 /*++
986
987 Routine Description:
988
989 wait for Ehc halt or timeout
990
991 Arguments:
992
993 HcDev - USB2_HC_DEV
994 Timeout - timeout threshold
995
996 Returns:
997
998 EFI_SUCCESS Success
999 EFI_TIMEOUT Timeout
1000
1001 --*/
1002 ;
1003
1004 EFI_STATUS
1005 WaitForEhcNotHalt (
1006 IN USB2_HC_DEV *HcDev,
1007 IN UINTN Timeout
1008 )
1009 /*++
1010
1011 Routine Description:
1012
1013 wait for Ehc not halt or timeout
1014
1015 Arguments:
1016
1017 HcDev - USB2_HC_DEV
1018 Timeout - timeout threshold
1019
1020 Returns:
1021
1022 EFI_SUCCESS Success
1023 EFI_TIMEOUT Timeout
1024
1025 --*/
1026 ;
1027
1028 EFI_STATUS
1029 WaitForEhcDoorbell (
1030 IN USB2_HC_DEV *HcDev,
1031 IN UINTN Timeout
1032 )
1033 /*++
1034
1035 Routine Description:
1036
1037 Wait for periodic schedule disable or timeout
1038
1039 Arguments:
1040
1041 HcDev - USB2_HC_DEV
1042 Timeout - timeout threshold
1043
1044 Returns:
1045
1046 EFI_SUCCESS Success
1047 EFI_TIMEOUT Timeout
1048
1049 --*/
1050 ;
1051
1052 EFI_STATUS
1053 WaitForAsyncScheduleEnable (
1054 IN USB2_HC_DEV *HcDev,
1055 IN UINTN Timeout
1056 )
1057 /*++
1058
1059 Routine Description:
1060
1061 Wait for Ehc asynchronous schedule enable or timeout
1062
1063 Arguments:
1064
1065 HcDev - USB2_HC_DEV
1066 Timeout - timeout threshold
1067
1068 Returns:
1069
1070 EFI_SUCCESS Success
1071 EFI_TIMEOUT Timeout
1072
1073 --*/
1074 ;
1075
1076 EFI_STATUS
1077 WaitForAsyncScheduleDisable (
1078 IN USB2_HC_DEV *HcDev,
1079 IN UINTN Timeout
1080 )
1081 /*++
1082
1083 Routine Description:
1084
1085 Wait for Ehc asynchronous schedule disable or timeout
1086
1087 Arguments:
1088
1089 HcDev - USB2_HC_DEV
1090 Timeout - timeout threshold
1091
1092 Returns:
1093
1094 EFI_SUCCESS Success
1095 EFI_TIMEOUT Timeout
1096
1097 --*/
1098 ;
1099
1100 EFI_STATUS
1101 WaitForPeriodicScheduleEnable (
1102 IN USB2_HC_DEV *HcDev,
1103 IN UINTN Timeout
1104 )
1105 /*++
1106
1107 Routine Description:
1108
1109 Wait for Ehc periodic schedule enable or timeout
1110
1111 Arguments:
1112
1113 HcDev - USB2_HC_DEV
1114 Timeout - timeout threshold
1115
1116 Returns:
1117
1118 EFI_SUCCESS Success
1119 EFI_TIMEOUT Timeout
1120
1121 --*/
1122 ;
1123
1124 EFI_STATUS
1125 WaitForPeriodicScheduleDisable (
1126 IN USB2_HC_DEV *HcDev,
1127 IN UINTN Timeout
1128 )
1129 /*++
1130
1131 Routine Description:
1132
1133 Wait for periodic schedule disable or timeout
1134
1135 Arguments:
1136
1137 HcDev - USB2_HC_DEV
1138 Timeout - timeout threshold
1139
1140 Returns:
1141
1142 EFI_SUCCESS Success
1143 EFI_TIMEOUT Timeout
1144
1145 --*/
1146 ;
1147
1148 EFI_STATUS
1149 GetCapabilityLen (
1150 IN USB2_HC_DEV *HcDev
1151 )
1152 /*++
1153
1154 Routine Description:
1155
1156 Get the length of capability register
1157
1158 Arguments:
1159
1160 HcDev - USB2_HC_DEV
1161
1162 Returns:
1163
1164 EFI_SUCCESS Success
1165 EFI_DEVICE_ERROR Fail
1166
1167 --*/
1168 ;
1169
1170 EFI_STATUS
1171 SetFrameListBaseAddr (
1172 IN USB2_HC_DEV *HcDev,
1173 IN UINT32 FrameBuffer
1174 )
1175 /*++
1176
1177 Routine Description:
1178
1179 Set base address of frame list first entry
1180
1181 Arguments:
1182
1183 HcDev - USB2_HC_DEV
1184 FrameBuffer - base address of first entry of frame list
1185
1186 Returns:
1187
1188 EFI_SUCCESS Success
1189 EFI_DEVICE_ERROR Fail
1190
1191 --*/
1192 ;
1193
1194 EFI_STATUS
1195 SetAsyncListAddr (
1196 IN USB2_HC_DEV *HcDev,
1197 IN EHCI_QH_ENTITY *QhPtr
1198 )
1199 /*++
1200
1201 Routine Description:
1202
1203 Set address of first Async schedule Qh
1204
1205 Arguments:
1206
1207 HcDev - USB2_HC_DEV
1208 QhPtr - A pointer to first Qh in the Async schedule
1209
1210 Returns:
1211
1212 EFI_SUCCESS Success
1213 EFI_DEVICE_ERROR Fail
1214
1215 --*/
1216 ;
1217
1218 EFI_STATUS
1219 SetCtrlDataStructSeg (
1220 IN USB2_HC_DEV *HcDev
1221 )
1222 /*++
1223
1224 Routine Description:
1225
1226 Set address of first Async schedule Qh
1227
1228 Arguments:
1229
1230 HcDev - USB2_HC_DEV
1231 QhPtr - A pointer to first Qh in the Async schedule
1232
1233 Returns:
1234
1235 EFI_SUCCESS Success
1236 EFI_DEVICE_ERROR Fail
1237
1238 --*/
1239 ;
1240
1241 EFI_STATUS
1242 SetPortRoutingEhc (
1243 IN USB2_HC_DEV *HcDev
1244 )
1245 /*++
1246
1247 Routine Description:
1248
1249 Set Ehc port routing bit
1250
1251 Arguments:
1252
1253 HcDev - USB2_HC_DEV
1254
1255 Returns:
1256
1257 EFI_SUCCESS Success
1258 EFI_DEVICE_ERROR Fail
1259
1260 --*/
1261 ;
1262
1263 EFI_STATUS
1264 EnablePeriodicSchedule (
1265 IN USB2_HC_DEV *HcDev
1266 )
1267 /*++
1268
1269 Routine Description:
1270
1271 Enable periodic schedule
1272
1273 Arguments:
1274
1275 HcDev - USB2_HC_DEV
1276
1277 Returns:
1278
1279 EFI_SUCCESS Success
1280 EFI_DEVICE_ERROR Fail
1281
1282 --*/
1283 ;
1284
1285 EFI_STATUS
1286 DisablePeriodicSchedule (
1287 IN USB2_HC_DEV *HcDev
1288 )
1289 /*++
1290
1291 Routine Description:
1292
1293 Disable periodic schedule
1294
1295 Arguments:
1296
1297 HcDev - USB2_HC_DEV
1298
1299 Returns:
1300
1301 EFI_SUCCESS Success
1302 EFI_DEVICE_ERROR Fail
1303
1304 --*/
1305 ;
1306
1307 EFI_STATUS
1308 EnableAsynchronousSchedule (
1309 IN USB2_HC_DEV *HcDev
1310 )
1311 /*++
1312
1313 Routine Description:
1314
1315 Enable asynchrounous schedule
1316
1317 Arguments:
1318
1319 HcDev - USB2_HC_DEV
1320
1321 Returns:
1322
1323 EFI_SUCCESS Success
1324 EFI_DEVICE_ERROR Fail
1325
1326 --*/
1327 ;
1328
1329 EFI_STATUS
1330 DisableAsynchronousSchedule (
1331 IN USB2_HC_DEV *HcDev
1332 )
1333 /*++
1334
1335 Routine Description:
1336
1337 Disable asynchrounous schedule
1338
1339 Arguments:
1340
1341 HcDev - USB2_HC_DEV
1342
1343 Returns:
1344
1345 EFI_SUCCESS Success
1346 EFI_DEVICE_ERROR Fail
1347
1348 --*/
1349 ;
1350
1351 EFI_STATUS
1352 StartScheduleExecution (
1353 IN USB2_HC_DEV *HcDev
1354 )
1355 /*++
1356
1357 Routine Description:
1358
1359 Start Ehc schedule execution
1360
1361 Arguments:
1362
1363 HcDev - USB2_HC_DEV
1364
1365 Returns:
1366
1367 EFI_SUCCESS Success
1368 EFI_DEVICE_ERROR Fail
1369
1370 --*/
1371 ;
1372
1373 EFI_STATUS
1374 ResetEhc (
1375 IN USB2_HC_DEV *HcDev
1376 )
1377 /*++
1378
1379 Routine Description:
1380
1381 Reset Ehc
1382
1383 Arguments:
1384
1385 HcDev - USB2_HC_DEV
1386
1387 Returns:
1388
1389 EFI_SUCCESS Success
1390 EFI_DEVICE_ERROR Fail
1391
1392 --*/
1393 ;
1394
1395 EFI_STATUS
1396 ClearEhcAllStatus (
1397 IN USB2_HC_DEV *HcDev
1398 )
1399 /*++
1400
1401 Routine Description:
1402
1403 Clear Ehc all status bits
1404
1405 Arguments:
1406
1407 HcDev - USB2_HC_DEV
1408
1409 Returns:
1410
1411 EFI_SUCCESS Success
1412 EFI_DEVICE_ERROR Fail
1413
1414 --*/
1415 ;
1416
1417 //
1418 // EhciSched Functions
1419 //
1420 EFI_STATUS
1421 InitialPeriodicFrameList (
1422 IN USB2_HC_DEV *HcDev,
1423 IN UINTN Length
1424 )
1425 /*++
1426
1427 Routine Description:
1428
1429 Initialize Periodic Schedule Frame List
1430
1431 Arguments:
1432
1433 HcDev - USB2_HC_DEV
1434 Length - Frame List Length
1435
1436 Returns:
1437
1438 EFI_SUCCESS Success
1439 EFI_DEVICE_ERROR Fail
1440
1441 --*/
1442 ;
1443
1444 VOID
1445 DeinitialPeriodicFrameList (
1446 IN USB2_HC_DEV *HcDev
1447 )
1448 /*++
1449
1450 Routine Description:
1451
1452 Deinitialize Periodic Schedule Frame List
1453
1454 Arguments:
1455
1456 HcDev - USB2_HC_DEV
1457
1458 Returns:
1459
1460 VOID
1461
1462 --*/
1463 ;
1464
1465 EFI_STATUS
1466 CreatePollingTimer (
1467 IN USB2_HC_DEV *HcDev,
1468 IN EFI_EVENT_NOTIFY NotifyFunction
1469 )
1470 /*++
1471
1472 Routine Description:
1473
1474 Create Async Request Polling Timer
1475
1476 Arguments:
1477
1478 HcDev - USB2_HC_DEV
1479 NotifyFunction - Timer Notify Function
1480
1481 Returns:
1482
1483 EFI_SUCCESS Success
1484 EFI_DEVICE_ERROR Fail
1485
1486 --*/
1487 ;
1488
1489 EFI_STATUS
1490 DestoryPollingTimer (
1491 IN USB2_HC_DEV *HcDev
1492 )
1493 /*++
1494
1495 Routine Description:
1496
1497 Destory Async Request Polling Timer
1498
1499 Arguments:
1500
1501 HcDev - USB2_HC_DEV
1502
1503 Returns:
1504
1505 EFI_SUCCESS Success
1506 EFI_DEVICE_ERROR Fail
1507
1508 --*/
1509 ;
1510
1511 EFI_STATUS
1512 StartPollingTimer (
1513 IN USB2_HC_DEV *HcDev
1514 )
1515 /*++
1516
1517 Routine Description:
1518
1519 Start Async Request Polling Timer
1520
1521 Arguments:
1522
1523 HcDev - USB2_HC_DEV
1524
1525 Returns:
1526
1527 EFI_SUCCESS Success
1528 EFI_DEVICE_ERROR Fail
1529
1530 --*/
1531 ;
1532
1533 EFI_STATUS
1534 StopPollingTimer (
1535 IN USB2_HC_DEV *HcDev
1536 )
1537 /*++
1538
1539 Routine Description:
1540
1541 Stop Async Request Polling Timer
1542
1543 Arguments:
1544
1545 HcDev - USB2_HC_DEV
1546
1547 Returns:
1548
1549 EFI_SUCCESS Success
1550 EFI_DEVICE_ERROR Fail
1551
1552 --*/
1553 ;
1554
1555 EFI_STATUS
1556 CreateQh (
1557 IN USB2_HC_DEV *HcDev,
1558 IN UINT8 DeviceAddr,
1559 IN UINT8 Endpoint,
1560 IN UINT8 DeviceSpeed,
1561 IN UINTN MaxPacketLen,
1562 OUT EHCI_QH_ENTITY **QhPtrPtr
1563 )
1564 /*++
1565
1566 Routine Description:
1567
1568 Create Qh Structure and Pre-Initialize
1569
1570 Arguments:
1571
1572 HcDev - USB2_HC_DEV
1573 DeviceAddr - Address of Device
1574 Endpoint - Endpoint Number
1575 DeviceSpeed - Device Speed
1576 MaxPacketLen - Max Length of one Packet
1577 QhPtrPtr - A pointer of pointer to Qh for return
1578
1579 Returns:
1580
1581 EFI_SUCCESS Success
1582 EFI_DEVICE_ERROR Fail
1583
1584 --*/
1585 ;
1586
1587 EFI_STATUS
1588 CreateControlQh (
1589 IN USB2_HC_DEV *HcDev,
1590 IN UINT8 DeviceAddr,
1591 IN UINT8 DeviceSpeed,
1592 IN UINTN MaxPacketLen,
1593 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1594 OUT EHCI_QH_ENTITY **QhPtrPtr
1595 )
1596 /*++
1597
1598 Routine Description:
1599
1600 Create Qh for Control Transfer
1601
1602 Arguments:
1603
1604 HcDev - USB2_HC_DEV
1605 DeviceAddr - Address of Device
1606 DeviceSpeed - Device Speed
1607 MaxPacketLen - Max Length of one Packet
1608 Translator - Translator Transaction for SplitX
1609 QhPtrPtr - A pointer of pointer to Qh for return
1610
1611 Returns:
1612
1613 EFI_SUCCESS Success
1614 EFI_DEVICE_ERROR Fail
1615
1616 --*/
1617 ;
1618
1619 EFI_STATUS
1620 CreateBulkQh (
1621 IN USB2_HC_DEV *HcDev,
1622 IN UINT8 DeviceAddr,
1623 IN UINT8 EndPointAddr,
1624 IN UINT8 DeviceSpeed,
1625 IN UINT8 DataToggle,
1626 IN UINTN MaxPacketLen,
1627 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1628 OUT EHCI_QH_ENTITY **QhPtrPtr
1629 )
1630 /*++
1631
1632 Routine Description:
1633
1634 Create Qh for Bulk Transfer
1635
1636 Arguments:
1637
1638 HcDev - USB2_HC_DEV
1639 DeviceAddr - Address of Device
1640 EndPointAddr - Address of Endpoint
1641 DeviceSpeed - Device Speed
1642 MaxPacketLen - Max Length of one Packet
1643 Translator - Translator Transaction for SplitX
1644 QhPtrPtr - A pointer of pointer to Qh for return
1645
1646 Returns:
1647
1648 EFI_SUCCESS Success
1649 EFI_DEVICE_ERROR Fail
1650
1651 --*/
1652 ;
1653
1654 EFI_STATUS
1655 CreateInterruptQh (
1656 IN USB2_HC_DEV *HcDev,
1657 IN UINT8 DeviceAddr,
1658 IN UINT8 EndPointAddr,
1659 IN UINT8 DeviceSpeed,
1660 IN UINT8 DataToggle,
1661 IN UINTN MaxPacketLen,
1662 IN UINTN Interval,
1663 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1664 OUT EHCI_QH_ENTITY **QhPtrPtr
1665 )
1666 /*++
1667
1668 Routine Description:
1669
1670 Create Qh for Control Transfer
1671
1672 Arguments:
1673
1674 HcDev - USB2_HC_DEV
1675 DeviceAddr - Address of Device
1676 EndPointAddr - Address of Endpoint
1677 DeviceSpeed - Device Speed
1678 MaxPacketLen - Max Length of one Packet
1679 Interval - value of interval
1680 Translator - Translator Transaction for SplitX
1681 QhPtrPtr - A pointer of pointer to Qh for return
1682
1683 Returns:
1684
1685 EFI_SUCCESS Success
1686 EFI_DEVICE_ERROR Fail
1687
1688 --*/
1689 ;
1690
1691 VOID
1692 DestoryQh (
1693 IN USB2_HC_DEV *HcDev,
1694 IN EHCI_QH_ENTITY *QhPtr
1695 )
1696 /*++
1697
1698 Routine Description:
1699
1700 Destory Qh Structure
1701
1702 Arguments:
1703
1704 HcDev - USB2_HC_DEV
1705 QhPtr - A pointer to Qh
1706
1707 Returns:
1708
1709 VOID
1710
1711 --*/
1712 ;
1713
1714 EFI_STATUS
1715 CreateQtd (
1716 IN USB2_HC_DEV *HcDev,
1717 IN UINT8 *DataPtr,
1718 IN UINTN DataLen,
1719 IN UINT8 PktId,
1720 IN UINT8 Toggle,
1721 IN UINT8 QtdStatus,
1722 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1723 )
1724 /*++
1725
1726 Routine Description:
1727
1728 Create Qtd Structure and Pre-Initialize it
1729
1730 Arguments:
1731
1732 HcDev - USB2_HC_DEV
1733 DataPtr - A pointer to user data buffer to transfer
1734 DataLen - Length of user data to transfer
1735 PktId - Packet Identification of this Qtd
1736 Toggle - Data Toggle of this Qtd
1737 QtdStatus - Default value of status of this Qtd
1738 QtdPtrPtr - A pointer of pointer to Qtd for return
1739
1740 Returns:
1741
1742 EFI_SUCCESS Success
1743 EFI_OUT_OF_RESOURCES Cannot allocate resources
1744
1745 --*/
1746 ;
1747
1748 EFI_STATUS
1749 CreateSetupQtd (
1750 IN USB2_HC_DEV *HcDev,
1751 IN UINT8 *DevReqPtr,
1752 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1753 )
1754 /*++
1755
1756 Routine Description:
1757
1758 Create Qtd Structure for Setup
1759
1760 Arguments:
1761
1762 HcDev - USB2_HC_DEV
1763 DevReqPtr - A pointer to Device Request Data
1764 QtdPtrPtr - A pointer of pointer to Qtd for return
1765
1766 Returns:
1767
1768 EFI_SUCCESS Success
1769 EFI_OUT_OF_RESOURCES Cannot allocate resources
1770
1771 --*/
1772 ;
1773
1774 EFI_STATUS
1775 CreateDataQtd (
1776 IN USB2_HC_DEV *HcDev,
1777 IN UINT8 *DataPtr,
1778 IN UINTN DataLen,
1779 IN UINT8 PktId,
1780 IN UINT8 Toggle,
1781 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1782 )
1783 /*++
1784
1785 Routine Description:
1786
1787 Create Qtd Structure for data
1788
1789 Arguments:
1790
1791 HcDev - USB2_HC_DEV
1792 DataPtr - A pointer to user data buffer to transfer
1793 DataLen - Length of user data to transfer
1794 PktId - Packet Identification of this Qtd
1795 Toggle - Data Toggle of this Qtd
1796 QtdPtrPtr - A pointer of pointer to Qtd for return
1797
1798 Returns:
1799
1800 EFI_SUCCESS Success
1801 EFI_OUT_OF_RESOURCES Cannot allocate resources
1802
1803 --*/
1804 ;
1805
1806 EFI_STATUS
1807 CreateStatusQtd (
1808 IN USB2_HC_DEV *HcDev,
1809 IN UINT8 PktId,
1810 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1811 )
1812 /*++
1813
1814 Routine Description:
1815
1816 Create Qtd Structure for status
1817
1818 Arguments:
1819
1820 HcDev - USB2_HC_DEV
1821 PktId - Packet Identification of this Qtd
1822 QtdPtrPtr - A pointer of pointer to Qtd for return
1823
1824 Returns:
1825
1826 EFI_SUCCESS Success
1827 EFI_OUT_OF_RESOURCES Cannot allocate resources
1828
1829 --*/
1830 ;
1831
1832 EFI_STATUS
1833 CreateAltQtd (
1834 IN USB2_HC_DEV *HcDev,
1835 IN UINT8 PktId,
1836 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1837 )
1838 /*++
1839
1840 Routine Description:
1841
1842 Create Qtd Structure for Alternative
1843
1844 Arguments:
1845
1846 HcDev - USB2_HC_DEV
1847 PktId - Packet Identification of this Qtd
1848 QtdPtrPtr - A pointer of pointer to Qtd for return
1849
1850 Returns:
1851
1852 EFI_SUCCESS Success
1853 EFI_OUT_OF_RESOURCES Cannot allocate resources
1854
1855 --*/
1856 ;
1857
1858 EFI_STATUS
1859 CreateControlQtds (
1860 IN USB2_HC_DEV *HcDev,
1861 IN UINT8 DataPktId,
1862 IN UINT8 *RequestCursor,
1863 IN UINT8 *DataCursor,
1864 IN UINTN DataLen,
1865 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1866 OUT EHCI_QTD_ENTITY **ControlQtdsHead
1867 )
1868 /*++
1869
1870 Routine Description:
1871
1872 Create Qtds list for Control Transfer
1873
1874 Arguments:
1875
1876 HcDev - USB2_HC_DEV
1877 DataPktId - Packet Identification of Data Qtds
1878 RequestCursor - A pointer to request structure buffer to transfer
1879 DataCursor - A pointer to user data buffer to transfer
1880 DataLen - Length of user data to transfer
1881 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return
1882
1883 Returns:
1884
1885 EFI_SUCCESS Success
1886 EFI_DEVICE_ERROR Fail
1887
1888 --*/
1889 ;
1890
1891 EFI_STATUS
1892 CreateBulkOrInterruptQtds (
1893 IN USB2_HC_DEV *HcDev,
1894 IN UINT8 PktId,
1895 IN UINT8 *DataCursor,
1896 IN UINTN DataLen,
1897 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1898 OUT EHCI_QTD_ENTITY **QtdsHead
1899 )
1900 /*++
1901
1902 Routine Description:
1903
1904 Create Qtds list for Bulk or Interrupt Transfer
1905
1906 Arguments:
1907
1908 HcDev - USB2_HC_DEV
1909 PktId - Packet Identification of Qtds
1910 DataCursor - A pointer to user data buffer to transfer
1911 DataLen - Length of user data to transfer
1912 DataToggle - Data Toggle to start
1913 Translator - Translator Transaction for SplitX
1914 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return
1915
1916 Returns:
1917
1918 EFI_SUCCESS Success
1919 EFI_DEVICE_ERROR Fail
1920
1921 --*/
1922 ;
1923
1924 VOID
1925 DestoryQtds (
1926 IN USB2_HC_DEV *HcDev,
1927 IN EHCI_QTD_ENTITY *FirstQtdPtr
1928 )
1929 /*++
1930
1931 Routine Description:
1932
1933 Destory all Qtds in the list
1934
1935 Arguments:
1936
1937 HcDev - USB2_HC_DEV
1938 FirstQtdPtr - A pointer to first Qtd in the list
1939
1940 Returns:
1941
1942 VOID
1943
1944 --*/
1945 ;
1946
1947 VOID
1948 LinkQtdToQtd (
1949 IN EHCI_QTD_ENTITY *PreQtdPtr,
1950 IN EHCI_QTD_ENTITY *QtdPtr
1951 )
1952 /*++
1953
1954 Routine Description:
1955
1956 Link Qtds together
1957
1958 Arguments:
1959
1960 PreQtdPtr - A pointer to pre Qtd
1961 QtdPtr - A pointer to next Qtd
1962
1963 Returns:
1964
1965 VOID
1966
1967 --*/
1968 ;
1969
1970 VOID
1971 LinkQtdsToAltQtd (
1972 IN EHCI_QTD_ENTITY *FirstQtdPtr,
1973 IN EHCI_QTD_ENTITY *AltQtdPtr
1974 )
1975 /*++
1976
1977 Routine Description:
1978
1979 Link AlterQtds together
1980
1981 Arguments:
1982
1983 FirstQtdPtr - A pointer to first Qtd in the list
1984 AltQtdPtr - A pointer to alternative Qtd
1985
1986 Returns:
1987 VOID
1988
1989 --*/
1990 ;
1991
1992 VOID
1993 LinkQtdToQh (
1994 IN EHCI_QH_ENTITY *QhPtr,
1995 IN EHCI_QTD_ENTITY *QtdEntryPtr
1996 )
1997 /*++
1998
1999 Routine Description:
2000
2001 Link Qtds list to Qh
2002
2003 Arguments:
2004
2005 QhPtr - A pointer to Qh
2006 QtdPtr - A pointer to first Qtd in the list
2007
2008 Returns:
2009
2010 VOID
2011
2012 --*/
2013 ;
2014
2015 EFI_STATUS
2016 LinkQhToAsyncList (
2017 IN USB2_HC_DEV *HcDev,
2018 IN EHCI_QH_ENTITY *QhPtr
2019 )
2020 /*++
2021
2022 Routine Description:
2023
2024 Link Qh to Async Schedule List
2025
2026 Arguments:
2027
2028 HcDev - USB2_HC_DEV
2029 QhPtr - A pointer to Qh
2030
2031 Returns:
2032
2033 EFI_SUCCESS Success
2034 EFI_DEVICE_ERROR Fail
2035
2036 --*/
2037 ;
2038
2039 EFI_STATUS
2040 UnlinkQhFromAsyncList (
2041 IN USB2_HC_DEV *HcDev,
2042 IN EHCI_QH_ENTITY *QhPtr
2043 )
2044 /*++
2045
2046 Routine Description:
2047
2048 Unlink Qh from Async Schedule List
2049
2050 Arguments:
2051
2052 HcDev - USB2_HC_DEV
2053 QhPtr - A pointer to Qh
2054
2055 Returns:
2056
2057 EFI_SUCCESS Success
2058 EFI_DEVICE_ERROR Fail
2059
2060 --*/
2061 ;
2062
2063 VOID
2064 LinkQhToPeriodicList (
2065 IN USB2_HC_DEV *HcDev,
2066 IN EHCI_QH_ENTITY *QhPtr
2067 )
2068 /*++
2069
2070 Routine Description:
2071
2072 Link Qh to Periodic Schedule List
2073
2074 Arguments:
2075
2076 HcDev - USB2_HC_DEV
2077 QhPtr - A pointer to Qh
2078
2079 Returns:
2080
2081 VOID
2082
2083 --*/
2084 ;
2085
2086 VOID
2087 UnlinkQhFromPeriodicList (
2088 IN USB2_HC_DEV *HcDev,
2089 IN EHCI_QH_ENTITY *QhPtr,
2090 IN UINTN Interval
2091 )
2092 /*++
2093
2094 Routine Description:
2095
2096 Unlink Qh from Periodic Schedule List
2097
2098 Arguments:
2099
2100 HcDev - USB2_HC_DEV
2101 QhPtr - A pointer to Qh
2102 Interval - Interval of this periodic transfer
2103
2104 Returns:
2105
2106 VOID
2107
2108 --*/
2109 ;
2110
2111 VOID
2112 LinkToAsyncReqeust (
2113 IN USB2_HC_DEV *HcDev,
2114 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr
2115 )
2116 /*++
2117
2118 Routine Description:
2119
2120 Llink AsyncRequest Entry to Async Request List
2121
2122 Arguments:
2123
2124 HcDev - USB2_HC_DEV
2125 AsyncRequestPtr - A pointer to Async Request Entry
2126
2127 Returns:
2128
2129 VOID
2130
2131 --*/
2132 ;
2133
2134 VOID
2135 UnlinkFromAsyncReqeust (
2136 IN USB2_HC_DEV *HcDev,
2137 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr
2138 )
2139 /*++
2140
2141 Routine Description:
2142
2143 Unlink AsyncRequest Entry from Async Request List
2144
2145 Arguments:
2146
2147 HcDev - USB2_HC_DEV
2148 AsyncRequestPtr - A pointer to Async Request Entry
2149
2150 Returns:
2151
2152 VOID
2153
2154 --*/
2155 ;
2156
2157 UINTN
2158 GetNumberOfQtd (
2159 IN EHCI_QTD_ENTITY *FirstQtdPtr
2160 )
2161 /*++
2162
2163 Routine Description:
2164
2165 Number of Qtds in the list
2166
2167 Arguments:
2168
2169 FirstQtdPtr - A pointer to first Qtd in the list
2170
2171 Returns:
2172
2173 Number of Qtds in the list
2174
2175 --*/
2176 ;
2177
2178 UINTN
2179 GetNumberOfTransaction (
2180 IN UINTN SizeOfData,
2181 IN UINTN SizeOfTransaction
2182 )
2183 /*++
2184
2185 Routine Description:
2186
2187 Number of Transactions in one Qtd
2188
2189 Arguments:
2190
2191 SizeOfData - Size of one Qtd
2192 SizeOfTransaction - Size of one Transaction
2193
2194 Returns:
2195
2196 Number of Transactions in this Qtd
2197
2198 --*/
2199 ;
2200
2201 UINTN
2202 GetCapacityOfQtd (
2203 IN UINT8 *BufferCursor
2204 )
2205 /*++
2206
2207 Routine Description:
2208
2209 Get Capacity of Qtd
2210
2211 Arguments:
2212
2213 BufferCursor - BufferCursor of the Qtd
2214
2215 Returns:
2216
2217 Capacity of Qtd
2218
2219 --*/
2220 ;
2221
2222 UINTN
2223 GetApproxiOfInterval (
2224 IN UINTN Interval
2225 )
2226 /*++
2227
2228 Routine Description:
2229
2230 Get the approximate value in the 2 index sequence
2231
2232 Arguments:
2233
2234 Interval - the value of interval
2235
2236 Returns:
2237
2238 approximate value of interval in the 2 index sequence
2239
2240 --*/
2241 ;
2242
2243 EHCI_QTD_HW *
2244 GetQtdNextPointer (
2245 IN EHCI_QTD_HW *HwQtdPtr
2246 )
2247 /*++
2248
2249 Routine Description:
2250
2251 Get Qtd next pointer field
2252
2253 Arguments:
2254
2255 HwQtdPtr - A pointer to hardware Qtd structure
2256
2257 Returns:
2258
2259 A pointer to next hardware Qtd structure
2260
2261 --*/
2262 ;
2263
2264 BOOLEAN
2265 IsQtdStatusActive (
2266 IN EHCI_QTD_HW *HwQtdPtr
2267 )
2268 /*++
2269
2270 Routine Description:
2271
2272 Whether Qtd status is active or not
2273
2274 Arguments:
2275
2276 HwQtdPtr - A pointer to hardware Qtd structure
2277
2278 Returns:
2279
2280 TRUE Active
2281 FALSE Inactive
2282
2283 --*/
2284 ;
2285
2286 BOOLEAN
2287 IsQtdStatusHalted (
2288 IN EHCI_QTD_HW *HwQtdPtr
2289 )
2290 /*++
2291
2292 Routine Description:
2293
2294 Whether Qtd status is halted or not
2295
2296 Arguments:
2297
2298 HwQtdPtr - A pointer to hardware Qtd structure
2299
2300 Returns:
2301
2302 TRUE Halted
2303 FALSE Not halted
2304
2305 --*/
2306 ;
2307
2308 BOOLEAN
2309 IsQtdStatusBufferError (
2310 IN EHCI_QTD_HW *HwQtdPtr
2311 )
2312 /*++
2313
2314 Routine Description:
2315
2316 Whether Qtd status is buffer error or not
2317
2318 Arguments:
2319
2320 HwQtdPtr - A pointer to hardware Qtd structure
2321
2322 Returns:
2323
2324 TRUE Buffer error
2325 FALSE No buffer error
2326
2327 --*/
2328 ;
2329
2330 BOOLEAN
2331 IsQtdStatusBabbleError (
2332 IN EHCI_QTD_HW *HwQtdPtr
2333 )
2334 /*++
2335
2336 Routine Description:
2337
2338 Whether Qtd status is babble error or not
2339
2340 Arguments:
2341
2342 HwQtdPtr - A pointer to hardware Qtd structure
2343
2344 Returns:
2345
2346 TRUE Babble error
2347 FALSE No babble error
2348
2349 --*/
2350 ;
2351
2352 BOOLEAN
2353 IsQtdStatusTransactionError (
2354 IN EHCI_QTD_HW *HwQtdPtr
2355 )
2356 /*++
2357
2358 Routine Description:
2359
2360 Whether Qtd status is transaction error or not
2361
2362 Arguments:
2363
2364 HwQtdPtr - A pointer to hardware Qtd structure
2365
2366 Returns:
2367
2368 TRUE Transaction error
2369 FALSE No transaction error
2370
2371 --*/
2372 ;
2373
2374 BOOLEAN
2375 IsDataInTransfer (
2376 IN UINT8 EndPointAddress
2377 )
2378 /*++
2379
2380 Routine Description:
2381
2382 Whether is a DataIn direction transfer
2383
2384 Arguments:
2385
2386 EndPointAddress - address of the endpoint
2387
2388 Returns:
2389
2390 TRUE DataIn
2391 FALSE DataOut
2392
2393 --*/
2394 ;
2395
2396 EFI_STATUS
2397 MapDataBuffer (
2398 IN USB2_HC_DEV *HcDev,
2399 IN EFI_USB_DATA_DIRECTION TransferDirection,
2400 IN OUT VOID *Data,
2401 IN OUT UINTN *DataLength,
2402 OUT UINT8 *PktId,
2403 OUT UINT8 **DataCursor,
2404 OUT VOID **DataMap
2405 )
2406 /*++
2407
2408 Routine Description:
2409
2410 Map address of user data buffer
2411
2412 Arguments:
2413
2414 HcDev - USB2_HC_DEV
2415 TransferDirection - direction of transfer
2416 Data - A pointer to user data buffer
2417 DataLength - length of user data
2418 PktId - Packte Identificaion
2419 DataCursor - mapped address to return
2420 DataMap - identificaion of this mapping to return
2421
2422 Returns:
2423
2424 EFI_SUCCESS Success
2425 EFI_DEVICE_ERROR Fail
2426
2427 --*/
2428 ;
2429
2430 EFI_STATUS
2431 MapRequestBuffer (
2432 IN USB2_HC_DEV *HcDev,
2433 IN OUT VOID *Request,
2434 OUT UINT8 **RequestCursor,
2435 OUT VOID **RequestMap
2436 )
2437 /*++
2438
2439 Routine Description:
2440
2441 Map address of request structure buffer
2442
2443 Arguments:
2444
2445 HcDev - USB2_HC_DEV
2446 Request - A pointer to request structure
2447 RequestCursor - Mapped address of request structure to return
2448 RequestMap - Identificaion of this mapping to return
2449
2450 Returns:
2451
2452 EFI_SUCCESS Success
2453 EFI_DEVICE_ERROR Fail
2454
2455 --*/
2456 ;
2457
2458 VOID
2459 SetQtdBufferPointer (
2460 IN EHCI_QTD_HW *QtdHwPtr,
2461 IN VOID *DataPtr,
2462 IN UINTN DataLen
2463 )
2464 /*++
2465
2466 Routine Description:
2467
2468 Set data buffer pointers in Qtd
2469
2470 Arguments:
2471
2472 QtdHwPtr - A pointer to Qtd hardware structure
2473 DataPtr - A pointer to user data buffer
2474 DataLen - Length of the user data buffer
2475
2476 Returns:
2477
2478 VOID
2479
2480 --*/
2481 ;
2482
2483 EHCI_QTD_HW *
2484 GetQtdAlternateNextPointer (
2485 IN EHCI_QTD_HW *HwQtdPtr
2486 )
2487 /*++
2488
2489 Routine Description:
2490
2491 Get Qtd alternate next pointer field
2492
2493 Arguments:
2494
2495 HwQtdPtr - A pointer to hardware Qtd structure
2496
2497 Returns:
2498
2499 A pointer to hardware alternate Qtd
2500
2501 --*/
2502 ;
2503
2504 VOID
2505 ZeroOutQhOverlay (
2506 IN EHCI_QH_ENTITY *QhPtr
2507 )
2508 /*++
2509
2510 Routine Description:
2511
2512 Zero out the fields in Qh structure
2513
2514 Arguments:
2515
2516 QhPtr - A pointer to Qh structure
2517
2518 Returns:
2519
2520 VOID
2521
2522 --*/
2523 ;
2524
2525 VOID
2526 UpdateAsyncRequestTransfer (
2527 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,
2528 IN UINT32 TransferResult,
2529 IN UINTN ErrTDPos
2530 )
2531 /*++
2532
2533 Routine Description:
2534
2535 Update asynchronous request transfer
2536
2537 Arguments:
2538
2539 AsyncRequestPtr - A pointer to async request
2540 TransferResult - transfer result
2541 ErrQtdPos - postion of error Qtd
2542
2543 Returns:
2544
2545 VOID
2546
2547 --*/
2548 ;
2549
2550
2551 EFI_STATUS
2552 DeleteAsyncRequestTransfer (
2553 IN USB2_HC_DEV *HcDev,
2554 IN UINT8 DeviceAddress,
2555 IN UINT8 EndPointAddress,
2556 OUT UINT8 *DataToggle
2557 )
2558 /*++
2559
2560 Routine Description:
2561
2562 Delete all asynchronous request transfer
2563
2564 Arguments:
2565
2566 HcDev - USB2_HC_DEV
2567 DeviceAddress - address of usb device
2568 EndPointAddress - address of endpoint
2569 DataToggle - stored data toggle
2570
2571 Returns:
2572
2573 EFI_SUCCESS Success
2574 EFI_DEVICE_ERROR Fail
2575
2576 --*/
2577 ;
2578
2579 VOID
2580 CleanUpAllAsyncRequestTransfer (
2581 IN USB2_HC_DEV *HcDev
2582 )
2583 /*++
2584
2585 Routine Description:
2586
2587 Clean up all asynchronous request transfer
2588
2589 Arguments:
2590
2591 HcDev - USB2_HC_DEV
2592
2593 Returns:
2594 VOID
2595
2596 --*/
2597 ;
2598
2599 EFI_STATUS
2600 ExecuteTransfer (
2601 IN USB2_HC_DEV *HcDev,
2602 IN BOOLEAN IsControl,
2603 IN EHCI_QH_ENTITY *QhPtr,
2604 IN OUT UINTN *ActualLen,
2605 OUT UINT8 *DataToggle,
2606 IN UINTN TimeOut,
2607 OUT UINT32 *TransferResult
2608 )
2609 /*++
2610
2611 Routine Description:
2612
2613 Execute Bulk or SyncInterrupt Transfer
2614
2615 Arguments:
2616
2617 HcDev - USB2_HC_DEV
2618 IsControl - Is control transfer or not
2619 QhPtr - A pointer to Qh
2620 ActualLen - Actual transfered Len
2621 DataToggle - Data Toggle
2622 TimeOut - TimeOut threshold
2623 TransferResult - Transfer result
2624
2625 Returns:
2626
2627 EFI_SUCCESS Sucess
2628 EFI_DEVICE_ERROR Error
2629
2630 --*/
2631 ;
2632
2633 BOOLEAN
2634 CheckQtdsTransferResult (
2635 IN BOOLEAN IsControl,
2636 IN EHCI_QH_ENTITY *QhPtr,
2637 OUT UINT32 *Result,
2638 OUT UINTN *ErrQtdPos,
2639 OUT UINTN *ActualLen
2640 )
2641 /*++
2642
2643 Routine Description:
2644
2645 Check transfer result of Qtds
2646
2647 Arguments:
2648
2649 IsControl - Is control transfer or not
2650 QhPtr - A pointer to Qh
2651 Result - Transfer result
2652 ErrQtdPos - Error TD Position
2653 ActualLen - Actual Transfer Size
2654
2655 Returns:
2656
2657 TRUE Qtds finished
2658 FALSE Not finish
2659
2660 --*/
2661 ;
2662
2663 EFI_STATUS
2664 AsyncRequestMoniter (
2665 IN EFI_EVENT Event,
2666 IN VOID *Context
2667 )
2668 /*++
2669
2670 Routine Description:
2671
2672 Interrupt transfer periodic check handler
2673
2674 Arguments:
2675
2676 Event - Interrupt event
2677 Context - Pointer to USB2_HC_DEV
2678
2679 Returns:
2680
2681 EFI_SUCCESS Success
2682 EFI_DEVICE_ERROR Fail
2683
2684 --*/
2685 ;
2686
2687 #endif