Some library instance's PCD is missing in FPD file for a module, it break single...
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Ehci / Dxe / Ehci.h
1 /*++
2
3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module Name:
13
14 Ehci.h
15
16 Abstract:
17
18
19 Revision History
20 --*/
21
22 #ifndef _EHCI_H
23 #define _EHCI_H
24
25 //
26 // Universal Host Controller Interface data structures and defines
27 //
28 #include <IndustryStandard/pci22.h>
29
30 extern UINTN gEHCDebugLevel;
31 extern UINTN gEHCErrorLevel;
32
33 #define STALL_1_MACRO_SECOND 1
34 #define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND
35 #define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND
36
37 #define SETUP_PACKET_PID_CODE 0x02
38 #define INPUT_PACKET_PID_CODE 0x01
39 #define OUTPUT_PACKET_PID_CODE 0x0
40
41 #define ITD_SELECT_TYPE 0x0
42 #define QH_SELECT_TYPE 0x01
43 #define SITD_SELECT_TYPE 0x02
44 #define FSTN_SELECT_TYPE 0x03
45
46 #define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND
47 #define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND
48 #define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND
49 #define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND
50 #define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND
51 #define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND
52
53 #define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */
54
55 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1
56
57 #define EHCI_MIN_PACKET_SIZE 8
58 #define EHCI_MAX_PACKET_SIZE 1024
59 #define EHCI_MAX_FRAME_LIST_LENGTH 1024
60 #define EHCI_BLOCK_SIZE_WITH_TT 64
61 #define EHCI_BLOCK_SIZE 512
62 #define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)
63
64 #define NAK_COUNT_RELOAD 3
65 #define QTD_ERROR_COUNTER 1
66 #define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1
67
68 #define QTD_STATUS_ACTIVE 0x80
69 #define QTD_STATUS_HALTED 0x40
70 #define QTD_STATUS_BUFFER_ERR 0x20
71 #define QTD_STATUS_BABBLE_ERR 0x10
72 #define QTD_STATUS_TRANSACTION_ERR 0x08
73 #define QTD_STATUS_DO_STOP_SPLIT 0x02
74 #define QTD_STATUS_DO_START_SPLIT 0
75 #define QTD_STATUS_DO_PING 0x01
76 #define QTD_STATUS_DO_OUT 0
77
78 #define DATA0 0
79 #define DATA1 1
80
81 #define MICRO_FRAME_0_CHANNEL 0x01
82 #define MICRO_FRAME_1_CHANNEL 0x02
83 #define MICRO_FRAME_2_CHANNEL 0x04
84 #define MICRO_FRAME_3_CHANNEL 0x08
85 #define MICRO_FRAME_4_CHANNEL 0x10
86 #define MICRO_FRAME_5_CHANNEL 0x20
87 #define MICRO_FRAME_6_CHANNEL 0x40
88 #define MICRO_FRAME_7_CHANNEL 0x80
89
90 #define CONTROL_TRANSFER 0x01
91 #define BULK_TRANSFER 0x02
92 #define SYNC_INTERRUPT_TRANSFER 0x04
93 #define ASYNC_INTERRUPT_TRANSFER 0x08
94 #define SYNC_ISOCHRONOUS_TRANSFER 0x10
95 #define ASYNC_ISOCHRONOUS_TRANSFER 0x20
96
97
98 //
99 // Enhanced Host Controller Registers definitions
100 //
101 extern UINT32 mUsbCapabilityLen;
102 extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;
103 extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;
104
105 #define USBCMD 0x0 /* Command Register Offset 00-03h */
106 #define USBCMD_RS 0x01 /* Run / Stop */
107 #define USBCMD_HCRESET 0x02 /* Host controller reset */
108 #define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */
109 #define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */
110 #define USBCMD_PSE 0x10 /* Periodic schedule enable */
111 #define USBCMD_ASE 0x20 /* Asynchronous schedule enable */
112 #define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */
113
114 #define USBSTS 0x04 /* Statue Register Offset 04-07h */
115 #define USBSTS_HSE 0x10 /* Host system error */
116 #define USBSTS_IAA 0x20 /* Interrupt on async advance */
117 #define USBSTS_HCH 0x1000 /* Host controller halted */
118 #define USBSTS_PSS 0x4000 /* Periodic schedule status */
119 #define USBSTS_ASS 0x8000 /* Asynchronous schedule status */
120
121 #define USBINTR 0x08 /* Command Register Offset 08-0bh */
122
123 #define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */
124
125 #define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */
126
127 #define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */
128
129 #define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */
130
131 #define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */
132 #define CONFIGFLAG_CF 0x01 /* Configure Flag */
133
134 #define PORTSC 0x44 /* Port Status/Control Offset 44-47h */
135 #define PORTSC_CCS 0x01 /* Current Connect Status*/
136 #define PORTSC_CSC 0x02 /* Connect Status Change */
137 #define PORTSC_PED 0x04 /* Port Enable / Disable */
138 #define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */
139 #define PORTSC_OCA 0x10 /* Over current Active */
140 #define PORTSC_OCC 0x20 /* Over current Change */
141 #define PORTSC_FPR 0x40 /* Force Port Resume */
142 #define PORTSC_SUSP 0x80 /* Port Suspend State */
143 #define PORTSC_PR 0x100 /* Port Reset */
144 #define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */
145 #define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */
146 #define PORTSC_PP 0x1000 /* Port Power */
147 #define PORTSC_PO 0x2000 /* Port Owner */
148
149 #define CAPLENGTH 0 /* Capability Register Length 00h */
150
151 #define HCIVERSION 0x02 /* Interface Version Number 02-03h */
152
153 #define HCSPARAMS 0x04 /* Structural Parameters 04-07h */
154 #define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */
155
156 #define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */
157 #define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */
158 #define HCCP_PFLF 0x02 /* Programmable Frame List Flag */
159 #define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */
160
161 #define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */
162
163 #define CLASSC 0x09 /* Class Code 09-0bh */
164
165 #define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */
166
167 #define SBRN 0x60 /* Serial Bus Release Number 60h */
168
169 #define FLADJ 0x61 /* Frame Length Adjustment Register 61h */
170
171 #define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */
172
173 //
174 // PCI Configuration Registers
175 //
176 #define EHCI_PCI_CLASSC 0x09
177 #define EHCI_PCI_MEMORY_BASE 0x10
178
179 //
180 // Memory Offset Registers
181 //
182 #define EHCI_MEMORY_CAPLENGTH 0x0
183 #define EHCI_MEMORY_CONFIGFLAG 0x40
184
185 //
186 // USB Base Class Code,Sub-Class Code and Programming Interface
187 //
188 #define PCI_CLASSC_PI_EHCI 0x20
189
190 #define SETUP_PACKET_ID 0x2D
191 #define INPUT_PACKET_ID 0x69
192 #define OUTPUT_PACKET_ID 0xE1
193 #define ERROR_PACKET_ID 0x55
194
195 #define bit(a) 1 << (a)
196
197 #define GET_0B_TO_31B(Addr) (UINT32) (UINTN) (Addr)
198 #define GET_32B_TO_63B(Addr) (UINT32) (RShiftU64(((UINT64) (UINTN) (Addr)), 32) & 0xffffffff)
199
200 //
201 // Ehci Data and Ctrl Structures
202 //
203 #pragma pack(1)
204
205 typedef struct {
206 UINT8 PI;
207 UINT8 SubClassCode;
208 UINT8 BaseCode;
209 } USB_CLASSC;
210
211 typedef struct {
212 UINT32 NextQtdTerminate : 1;
213 UINT32 Rsvd1 : 4;
214 UINT32 NextQtdPointer : 27;
215
216 UINT32 AltNextQtdTerminate : 1;
217 UINT32 Rsvd2 : 4;
218 UINT32 AltNextQtdPointer : 27;
219
220 UINT32 Status : 8;
221 UINT32 PidCode : 2;
222 UINT32 ErrorCount : 2;
223 UINT32 CurrentPage : 3;
224 UINT32 InterruptOnComplete : 1;
225 UINT32 TotalBytes : 15;
226 UINT32 DataToggle : 1;
227
228 UINT32 CurrentOffset : 12;
229 UINT32 BufferPointer0 : 20;
230
231 UINT32 Rsvd3 : 12;
232 UINT32 BufferPointer1 : 20;
233
234 UINT32 Rsvd4 : 12;
235 UINT32 BufferPointer2 : 20;
236
237 UINT32 Rsvd5 : 12;
238 UINT32 BufferPointer3 : 20;
239
240 UINT32 Rsvd6 : 12;
241 UINT32 BufferPointer4 : 20;
242
243 UINT32 ExtBufferPointer0;
244 UINT32 ExtBufferPointer1;
245 UINT32 ExtBufferPointer2;
246 UINT32 ExtBufferPointer3;
247 UINT32 ExtBufferPointer4;
248 } EHCI_QTD_HW;
249
250 typedef struct {
251 UINT32 QhTerminate : 1;
252 UINT32 SelectType : 2;
253 UINT32 Rsvd1 : 2;
254 UINT32 QhHorizontalPointer : 27;
255
256 UINT32 DeviceAddr : 7;
257 UINT32 Inactive : 1;
258 UINT32 EndpointNum : 4;
259 UINT32 EndpointSpeed : 2;
260 UINT32 DataToggleControl : 1;
261 UINT32 HeadReclamationFlag : 1;
262 UINT32 MaxPacketLen : 11;
263 UINT32 ControlEndpointFlag : 1;
264 UINT32 NakCountReload : 4;
265
266 UINT32 InerruptScheduleMask : 8;
267 UINT32 SplitComletionMask : 8;
268 UINT32 HubAddr : 7;
269 UINT32 PortNum : 7;
270 UINT32 Multiplier : 2;
271
272 UINT32 Rsvd2 : 5;
273 UINT32 CurrentQtdPointer : 27;
274
275 UINT32 NextQtdTerminate : 1;
276 UINT32 Rsvd3 : 4;
277 UINT32 NextQtdPointer : 27;
278
279 UINT32 AltNextQtdTerminate : 1;
280 UINT32 NakCount : 4;
281 UINT32 AltNextQtdPointer : 27;
282
283 UINT32 Status : 8;
284 UINT32 PidCode : 2;
285 UINT32 ErrorCount : 2;
286 UINT32 CurrentPage : 3;
287 UINT32 InterruptOnComplete : 1;
288 UINT32 TotalBytes : 15;
289 UINT32 DataToggle : 1;
290
291 UINT32 CurrentOffset : 12;
292 UINT32 BufferPointer0 : 20;
293
294 UINT32 CompleteSplitMask : 8;
295 UINT32 Rsvd4 : 4;
296 UINT32 BufferPointer1 : 20;
297
298 UINT32 FrameTag : 5;
299 UINT32 SplitBytes : 7;
300 UINT32 BufferPointer2 : 20;
301
302 UINT32 Rsvd5 : 12;
303 UINT32 BufferPointer3 : 20;
304
305 UINT32 Rsvd6 : 12;
306 UINT32 BufferPointer4 : 20;
307
308 UINT32 ExtBufferPointer0;
309 UINT32 ExtBufferPointer1;
310 UINT32 ExtBufferPointer2;
311 UINT32 ExtBufferPointer3;
312 UINT32 ExtBufferPointer4;
313 } EHCI_QH_HW;
314
315 typedef struct {
316 UINT32 LinkTerminate : 1;
317 UINT32 SelectType : 2;
318 UINT32 Rsvd : 2;
319 UINT32 LinkPointer : 27;
320 } FRAME_LIST_ENTRY;
321
322 #pragma pack()
323
324 typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY;
325 typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY;
326 typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST;
327
328 struct _EHCI_QTD_ENTITY {
329 EHCI_QTD_HW Qtd;
330 UINT32 TotalBytes;
331 UINT32 StaticTotalBytes;
332 UINT32 StaticCurrentOffset;
333 EHCI_QTD_ENTITY *Prev;
334 EHCI_QTD_ENTITY *Next;
335 EHCI_QTD_ENTITY *AltNext;
336 EHCI_QH_ENTITY *SelfQh;
337 };
338
339 struct _EHCI_QH_ENTITY {
340 EHCI_QH_HW Qh;
341 EHCI_QH_ENTITY *Next;
342 EHCI_QH_ENTITY *Prev;
343 EHCI_QTD_ENTITY *FirstQtdPtr;
344 EHCI_QTD_ENTITY *LastQtdPtr;
345 EHCI_QTD_ENTITY *AltQtdPtr;
346 UINTN Interval;
347 UINT8 TransferType;
348 };
349
350 #define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)
351 #define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)
352
353
354 //
355 // Ehci Managment Structures
356 //
357 #define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
358
359 #define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')
360
361 struct _EHCI_ASYNC_REQUEST {
362 UINT8 TransferType;
363 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;
364 VOID *Context;
365 EHCI_ASYNC_REQUEST *Prev;
366 EHCI_ASYNC_REQUEST *Next;
367 EHCI_QH_ENTITY *QhPtr;
368 };
369
370 typedef struct _MEMORY_MANAGE_HEADER {
371 UINT8 *BitArrayPtr;
372 UINTN BitArraySizeInBytes;
373 UINT8 *MemoryBlockPtr;
374 UINTN MemoryBlockSizeInBytes;
375 VOID *Mapping;
376 struct _MEMORY_MANAGE_HEADER *Next;
377 } MEMORY_MANAGE_HEADER;
378
379 typedef struct _USB2_HC_DEV {
380 UINTN Signature;
381 EFI_PCI_IO_PROTOCOL *PciIo;
382 EFI_USB2_HC_PROTOCOL Usb2Hc;
383 UINTN PeriodicFrameListLength;
384 VOID *PeriodicFrameListBuffer;
385 VOID *PeriodicFrameListMap;
386 VOID *AsyncList;
387 EHCI_ASYNC_REQUEST *AsyncRequestList;
388 EFI_EVENT AsyncRequestEvent;
389 EFI_UNICODE_STRING_TABLE *ControllerNameTable;
390 MEMORY_MANAGE_HEADER *MemoryHeader;
391 UINT8 Is64BitCapable;
392 UINT32 High32BitAddr;
393 } USB2_HC_DEV;
394
395
396 //
397 // Internal Functions Declaration
398 //
399
400 //
401 // EhciMem Functions
402 //
403 EFI_STATUS
404 CreateMemoryBlock (
405 IN USB2_HC_DEV *HcDev,
406 OUT MEMORY_MANAGE_HEADER **MemoryHeader,
407 IN UINTN MemoryBlockSizeInPages
408 )
409 /*++
410
411 Routine Description:
412
413 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,
414 and use PciIo->Map to map the common buffer for Bus Master Read/Write.
415
416 Arguments:
417
418 HcDev - USB2_HC_DEV
419 MemoryHeader - MEMORY_MANAGE_HEADER to output
420 MemoryBlockSizeInPages - MemoryBlockSizeInPages
421
422 Returns:
423
424 EFI_SUCCESS Success
425 EFI_OUT_OF_RESOURCES Fail for no resources
426 EFI_UNSUPPORTED Unsupported currently
427
428 --*/
429 ;
430
431 EFI_STATUS
432 FreeMemoryHeader (
433 IN USB2_HC_DEV *HcDev,
434 IN MEMORY_MANAGE_HEADER *MemoryHeader
435 )
436 /*++
437
438 Routine Description:
439
440 Free Memory Header
441
442 Arguments:
443
444 HcDev - USB2_HC_DEV
445 MemoryHeader - MemoryHeader to be freed
446
447 Returns:
448
449 EFI_SUCCESS Success
450 EFI_INVALID_PARAMETER Parameter is error
451
452 --*/
453 ;
454
455 VOID
456 InsertMemoryHeaderToList (
457 IN MEMORY_MANAGE_HEADER *MemoryHeader,
458 IN MEMORY_MANAGE_HEADER *NewMemoryHeader
459 )
460 /*++
461
462 Routine Description:
463
464 Insert Memory Header To List
465
466 Arguments:
467
468 MemoryHeader - MEMORY_MANAGE_HEADER
469 NewMemoryHeader - MEMORY_MANAGE_HEADER
470
471 Returns:
472
473 VOID
474
475 --*/
476 ;
477
478 EFI_STATUS
479 AllocMemInMemoryBlock (
480 IN MEMORY_MANAGE_HEADER *MemoryHeader,
481 OUT VOID **Pool,
482 IN UINTN NumberOfMemoryUnit
483 )
484 /*++
485
486 Routine Description:
487
488 Alloc Memory In MemoryBlock
489
490 Arguments:
491
492 MemoryHeader - MEMORY_MANAGE_HEADER
493 Pool - Place to store pointer to memory
494 NumberOfMemoryUnit - Number Of Memory Unit
495
496 Returns:
497
498 EFI_SUCCESS Success
499 EFI_NOT_FOUND Can't find the free memory
500
501 --*/
502 ;
503
504 BOOLEAN
505 IsMemoryBlockEmptied (
506 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr
507 )
508 /*++
509
510 Routine Description:
511
512 Is Memory Block Emptied
513
514 Arguments:
515
516 MemoryHeaderPtr - MEMORY_MANAGE_HEADER
517
518 Returns:
519
520 TRUE Empty
521 FALSE Not Empty
522
523 --*/
524 ;
525
526 VOID
527 DelinkMemoryBlock (
528 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,
529 IN MEMORY_MANAGE_HEADER *NeedFreeMemoryHeader
530 )
531 /*++
532
533 Routine Description:
534
535 Delink Memory Block
536
537 Arguments:
538
539 FirstMemoryHeader - MEMORY_MANAGE_HEADER
540 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER
541
542 Returns:
543
544 VOID
545
546 --*/
547 ;
548
549 EFI_STATUS
550 InitialMemoryManagement (
551 IN USB2_HC_DEV *HcDev
552 )
553 /*++
554
555 Routine Description:
556
557 Initialize Memory Management
558
559 Arguments:
560
561 HcDev - USB2_HC_DEV
562
563 Returns:
564
565 EFI_SUCCESS Success
566 EFI_DEVICE_ERROR Fail
567
568 --*/
569 ;
570
571 EFI_STATUS
572 DeinitialMemoryManagement (
573 IN USB2_HC_DEV *HcDev
574 )
575 /*++
576
577 Routine Description:
578
579 Deinitialize Memory Management
580
581 Arguments:
582
583 HcDev - USB2_HC_DEV
584
585 Returns:
586
587 EFI_SUCCESS Success
588 EFI_DEVICE_ERROR Fail
589
590 --*/
591 ;
592
593 EFI_STATUS
594 EhciAllocatePool (
595 IN USB2_HC_DEV *HcDev,
596 OUT UINT8 **Pool,
597 IN UINTN AllocSize
598 )
599 /*++
600
601 Routine Description:
602
603 Ehci Allocate Pool
604
605 Arguments:
606
607 HcDev - USB2_HC_DEV
608 Pool - Place to store pointer to the memory buffer
609 AllocSize - Alloc Size
610
611 Returns:
612
613 EFI_SUCCESS Success
614 EFI_DEVICE_ERROR Fail
615
616 --*/
617 ;
618
619 VOID
620 EhciFreePool (
621 IN USB2_HC_DEV *HcDev,
622 IN UINT8 *Pool,
623 IN UINTN AllocSize
624 )
625 /*++
626
627 Routine Description:
628
629 Uhci Free Pool
630
631 Arguments:
632
633 HcDev - USB_HC_DEV
634 Pool - Pool to free
635 AllocSize - Pool size
636
637 Returns:
638
639 VOID
640
641 --*/
642 ;
643
644 //
645 // EhciReg Functions
646 //
647 EFI_STATUS
648 ReadEhcCapabiltiyReg (
649 IN USB2_HC_DEV *HcDev,
650 IN UINT32 CapabiltiyRegAddr,
651 IN OUT UINT32 *Data
652 )
653 /*++
654
655 Routine Description:
656
657 Read Ehc Capabitlity register
658
659 Arguments:
660
661 HcDev - USB2_HC_DEV
662 CapabiltiyRegAddr - Ehc Capability register address
663 Data - A pointer to data read from register
664
665 Returns:
666
667 EFI_SUCCESS Success
668 EFI_DEVICE_ERROR Fail
669
670 --*/
671 ;
672
673 EFI_STATUS
674 ReadEhcOperationalReg (
675 IN USB2_HC_DEV *HcDev,
676 IN UINT32 OperationalRegAddr,
677 IN OUT UINT32 *Data
678 )
679 /*++
680
681 Routine Description:
682
683 Read Ehc Operation register
684
685 Arguments:
686
687 HcDev - USB2_HC_DEV
688 OperationalRegAddr - Ehc Operation register address
689 Data - A pointer to data read from register
690
691 Returns:
692
693 EFI_SUCCESS Success
694 EFI_DEVICE_ERROR Fail
695
696 --*/
697 ;
698
699 EFI_STATUS
700 WriteEhcOperationalReg (
701 IN USB2_HC_DEV *HcDev,
702 IN UINT32 OperationalRegAddr,
703 IN UINT32 Data
704 )
705 /*++
706
707 Routine Description:
708
709 Write Ehc Operation register
710
711 Arguments:
712
713 HcDev - USB2_HC_DEV
714 OperationalRegAddr - Ehc Operation register address
715 Data - 32bit write to register
716
717 Returns:
718
719 EFI_SUCCESS Success
720 EFI_DEVICE_ERROR Fail
721
722 --*/
723 ;
724
725 EFI_STATUS
726 SetEhcDoorbell (
727 IN USB2_HC_DEV *HcDev
728 )
729 /*++
730
731 Routine Description:
732
733 Set Ehc door bell bit
734
735 Arguments:
736
737 HcDev - USB2_HC_DEV
738
739 Returns:
740
741 EFI_SUCCESS Success
742 EFI_DEVICE_ERROR Fail
743
744 --*/
745 ;
746
747 EFI_STATUS
748 SetFrameListLen (
749 IN USB2_HC_DEV *HcDev,
750 IN UINTN Length
751 )
752 /*++
753
754 Routine Description:
755
756 Set the length of Frame List
757
758 Arguments:
759
760 HcDev - USB2_HC_DEV
761 Length - the required length of frame list
762
763 Returns:
764
765 EFI_SUCCESS Success
766 EFI_INVALID_PARAMETER Invalid parameter
767 EFI_DEVICE_ERROR Fail
768
769 --*/
770 ;
771
772 BOOLEAN
773 IsFrameListProgrammable (
774 IN USB2_HC_DEV *HcDev
775 )
776 /*++
777
778 Routine Description:
779
780 Whether frame list is programmable
781
782 Arguments:
783
784 HcDev - USB2_HC_DEV
785
786 Returns:
787
788 TRUE Programmable
789 FALSE Unprogrammable
790
791 --*/
792 ;
793
794 BOOLEAN
795 IsPeriodicScheduleEnabled (
796 IN USB2_HC_DEV *HcDev
797 )
798 /*++
799
800 Routine Description:
801
802 Whether periodic schedule is enabled
803
804 Arguments:
805
806 HcDev - USB2_HC_DEV
807
808 Returns:
809
810 TRUE Enabled
811 FALSE Disabled
812
813 --*/
814 ;
815
816 BOOLEAN
817 IsAsyncScheduleEnabled (
818 IN USB2_HC_DEV *HcDev
819 )
820 /*++
821
822 Routine Description:
823
824 Whether asynchronous schedule is enabled
825
826 Arguments:
827
828 HcDev - USB2_HC_DEV
829
830 Returns:
831
832 TRUE Enabled
833 FALSE Disabled
834
835 --*/
836 ;
837
838 BOOLEAN
839 IsEhcPortEnabled (
840 IN USB2_HC_DEV *HcDev,
841 IN UINT8 PortNum
842 )
843 /*++
844
845 Routine Description:
846
847 Whether port is enabled
848
849 Arguments:
850
851 HcDev - USB2_HC_DEV
852
853 Returns:
854
855 TRUE Enabled
856 FALSE Disabled
857
858 --*/
859 ;
860
861 BOOLEAN
862 IsEhcReseted (
863 IN USB2_HC_DEV *HcDev
864 )
865 /*++
866
867 Routine Description:
868
869 Whether Ehc is halted
870
871 Arguments:
872
873 HcDev - USB2_HC_DEV
874
875 Returns:
876
877 TRUE Reseted
878 FALSE Unreseted
879
880 --*/
881 ;
882
883 BOOLEAN
884 IsEhcHalted (
885 IN USB2_HC_DEV *HcDev
886 )
887 /*++
888
889 Routine Description:
890
891 Whether Ehc is halted
892
893 Arguments:
894
895 HcDev - USB2_HC_DEV
896
897 Returns:
898
899 TRUE Halted
900 FALSE Not halted
901
902 --*/
903 ;
904
905 BOOLEAN
906 IsEhcSysError (
907 IN USB2_HC_DEV *HcDev
908 )
909 /*++
910
911 Routine Description:
912
913 Whether Ehc is system error
914
915 Arguments:
916
917 HcDev - USB2_HC_DEV
918
919 Returns:
920
921 TRUE System error
922 FALSE No system error
923
924 --*/
925 ;
926
927 BOOLEAN
928 IsHighSpeedDevice (
929 IN EFI_USB2_HC_PROTOCOL *This,
930 IN UINT8 PortNum
931 )
932 /*++
933
934 Routine Description:
935
936 Whether high speed device attached
937
938 Arguments:
939
940 HcDev - USB2_HC_DEV
941
942 Returns:
943
944 TRUE High speed
945 FALSE Full speed
946
947 --*/
948 ;
949
950 EFI_STATUS
951 WaitForEhcReset (
952 IN USB2_HC_DEV *HcDev,
953 IN UINTN Timeout
954 )
955 /*++
956
957 Routine Description:
958
959 wait for Ehc reset or timeout
960
961 Arguments:
962
963 HcDev - USB2_HC_DEV
964 Timeout - timeout threshold
965
966 Returns:
967
968 EFI_SUCCESS Success
969 EFI_TIMEOUT Timeout
970
971 --*/
972 ;
973
974 EFI_STATUS
975 WaitForEhcHalt (
976 IN USB2_HC_DEV *HcDev,
977 IN UINTN Timeout
978 )
979 /*++
980
981 Routine Description:
982
983 wait for Ehc halt or timeout
984
985 Arguments:
986
987 HcDev - USB2_HC_DEV
988 Timeout - timeout threshold
989
990 Returns:
991
992 EFI_SUCCESS Success
993 EFI_TIMEOUT Timeout
994
995 --*/
996 ;
997
998 EFI_STATUS
999 WaitForEhcNotHalt (
1000 IN USB2_HC_DEV *HcDev,
1001 IN UINTN Timeout
1002 )
1003 /*++
1004
1005 Routine Description:
1006
1007 wait for Ehc not halt or timeout
1008
1009 Arguments:
1010
1011 HcDev - USB2_HC_DEV
1012 Timeout - timeout threshold
1013
1014 Returns:
1015
1016 EFI_SUCCESS Success
1017 EFI_TIMEOUT Timeout
1018
1019 --*/
1020 ;
1021
1022 EFI_STATUS
1023 WaitForEhcDoorbell (
1024 IN USB2_HC_DEV *HcDev,
1025 IN UINTN Timeout
1026 )
1027 /*++
1028
1029 Routine Description:
1030
1031 Wait for periodic schedule disable or timeout
1032
1033 Arguments:
1034
1035 HcDev - USB2_HC_DEV
1036 Timeout - timeout threshold
1037
1038 Returns:
1039
1040 EFI_SUCCESS Success
1041 EFI_TIMEOUT Timeout
1042
1043 --*/
1044 ;
1045
1046 EFI_STATUS
1047 WaitForAsyncScheduleEnable (
1048 IN USB2_HC_DEV *HcDev,
1049 IN UINTN Timeout
1050 )
1051 /*++
1052
1053 Routine Description:
1054
1055 Wait for Ehc asynchronous schedule enable or timeout
1056
1057 Arguments:
1058
1059 HcDev - USB2_HC_DEV
1060 Timeout - timeout threshold
1061
1062 Returns:
1063
1064 EFI_SUCCESS Success
1065 EFI_TIMEOUT Timeout
1066
1067 --*/
1068 ;
1069
1070 EFI_STATUS
1071 WaitForAsyncScheduleDisable (
1072 IN USB2_HC_DEV *HcDev,
1073 IN UINTN Timeout
1074 )
1075 /*++
1076
1077 Routine Description:
1078
1079 Wait for Ehc asynchronous schedule disable or timeout
1080
1081 Arguments:
1082
1083 HcDev - USB2_HC_DEV
1084 Timeout - timeout threshold
1085
1086 Returns:
1087
1088 EFI_SUCCESS Success
1089 EFI_TIMEOUT Timeout
1090
1091 --*/
1092 ;
1093
1094 EFI_STATUS
1095 WaitForPeriodicScheduleEnable (
1096 IN USB2_HC_DEV *HcDev,
1097 IN UINTN Timeout
1098 )
1099 /*++
1100
1101 Routine Description:
1102
1103 Wait for Ehc periodic schedule enable or timeout
1104
1105 Arguments:
1106
1107 HcDev - USB2_HC_DEV
1108 Timeout - timeout threshold
1109
1110 Returns:
1111
1112 EFI_SUCCESS Success
1113 EFI_TIMEOUT Timeout
1114
1115 --*/
1116 ;
1117
1118 EFI_STATUS
1119 WaitForPeriodicScheduleDisable (
1120 IN USB2_HC_DEV *HcDev,
1121 IN UINTN Timeout
1122 )
1123 /*++
1124
1125 Routine Description:
1126
1127 Wait for periodic schedule disable or timeout
1128
1129 Arguments:
1130
1131 HcDev - USB2_HC_DEV
1132 Timeout - timeout threshold
1133
1134 Returns:
1135
1136 EFI_SUCCESS Success
1137 EFI_TIMEOUT Timeout
1138
1139 --*/
1140 ;
1141
1142 EFI_STATUS
1143 GetCapabilityLen (
1144 IN USB2_HC_DEV *HcDev
1145 )
1146 /*++
1147
1148 Routine Description:
1149
1150 Get the length of capability register
1151
1152 Arguments:
1153
1154 HcDev - USB2_HC_DEV
1155
1156 Returns:
1157
1158 EFI_SUCCESS Success
1159 EFI_DEVICE_ERROR Fail
1160
1161 --*/
1162 ;
1163
1164 EFI_STATUS
1165 SetFrameListBaseAddr (
1166 IN USB2_HC_DEV *HcDev,
1167 IN UINT32 FrameBuffer
1168 )
1169 /*++
1170
1171 Routine Description:
1172
1173 Set base address of frame list first entry
1174
1175 Arguments:
1176
1177 HcDev - USB2_HC_DEV
1178 FrameBuffer - base address of first entry of frame list
1179
1180 Returns:
1181
1182 EFI_SUCCESS Success
1183 EFI_DEVICE_ERROR Fail
1184
1185 --*/
1186 ;
1187
1188 EFI_STATUS
1189 SetAsyncListAddr (
1190 IN USB2_HC_DEV *HcDev,
1191 IN EHCI_QH_ENTITY *QhPtr
1192 )
1193 /*++
1194
1195 Routine Description:
1196
1197 Set address of first Async schedule Qh
1198
1199 Arguments:
1200
1201 HcDev - USB2_HC_DEV
1202 QhPtr - A pointer to first Qh in the Async schedule
1203
1204 Returns:
1205
1206 EFI_SUCCESS Success
1207 EFI_DEVICE_ERROR Fail
1208
1209 --*/
1210 ;
1211
1212 EFI_STATUS
1213 SetCtrlDataStructSeg (
1214 IN USB2_HC_DEV *HcDev
1215 )
1216 /*++
1217
1218 Routine Description:
1219
1220 Set address of first Async schedule Qh
1221
1222 Arguments:
1223
1224 HcDev - USB2_HC_DEV
1225 QhPtr - A pointer to first Qh in the Async schedule
1226
1227 Returns:
1228
1229 EFI_SUCCESS Success
1230 EFI_DEVICE_ERROR Fail
1231
1232 --*/
1233 ;
1234
1235 EFI_STATUS
1236 SetPortRoutingEhc (
1237 IN USB2_HC_DEV *HcDev
1238 )
1239 /*++
1240
1241 Routine Description:
1242
1243 Set Ehc port routing bit
1244
1245 Arguments:
1246
1247 HcDev - USB2_HC_DEV
1248
1249 Returns:
1250
1251 EFI_SUCCESS Success
1252 EFI_DEVICE_ERROR Fail
1253
1254 --*/
1255 ;
1256
1257 EFI_STATUS
1258 EnablePeriodicSchedule (
1259 IN USB2_HC_DEV *HcDev
1260 )
1261 /*++
1262
1263 Routine Description:
1264
1265 Enable periodic schedule
1266
1267 Arguments:
1268
1269 HcDev - USB2_HC_DEV
1270
1271 Returns:
1272
1273 EFI_SUCCESS Success
1274 EFI_DEVICE_ERROR Fail
1275
1276 --*/
1277 ;
1278
1279 EFI_STATUS
1280 DisablePeriodicSchedule (
1281 IN USB2_HC_DEV *HcDev
1282 )
1283 /*++
1284
1285 Routine Description:
1286
1287 Disable periodic schedule
1288
1289 Arguments:
1290
1291 HcDev - USB2_HC_DEV
1292
1293 Returns:
1294
1295 EFI_SUCCESS Success
1296 EFI_DEVICE_ERROR Fail
1297
1298 --*/
1299 ;
1300
1301 EFI_STATUS
1302 EnableAsynchronousSchedule (
1303 IN USB2_HC_DEV *HcDev
1304 )
1305 /*++
1306
1307 Routine Description:
1308
1309 Enable asynchrounous schedule
1310
1311 Arguments:
1312
1313 HcDev - USB2_HC_DEV
1314
1315 Returns:
1316
1317 EFI_SUCCESS Success
1318 EFI_DEVICE_ERROR Fail
1319
1320 --*/
1321 ;
1322
1323 EFI_STATUS
1324 DisableAsynchronousSchedule (
1325 IN USB2_HC_DEV *HcDev
1326 )
1327 /*++
1328
1329 Routine Description:
1330
1331 Disable asynchrounous schedule
1332
1333 Arguments:
1334
1335 HcDev - USB2_HC_DEV
1336
1337 Returns:
1338
1339 EFI_SUCCESS Success
1340 EFI_DEVICE_ERROR Fail
1341
1342 --*/
1343 ;
1344
1345 EFI_STATUS
1346 StartScheduleExecution (
1347 IN USB2_HC_DEV *HcDev
1348 )
1349 /*++
1350
1351 Routine Description:
1352
1353 Start Ehc schedule execution
1354
1355 Arguments:
1356
1357 HcDev - USB2_HC_DEV
1358
1359 Returns:
1360
1361 EFI_SUCCESS Success
1362 EFI_DEVICE_ERROR Fail
1363
1364 --*/
1365 ;
1366
1367 EFI_STATUS
1368 ResetEhc (
1369 IN USB2_HC_DEV *HcDev
1370 )
1371 /*++
1372
1373 Routine Description:
1374
1375 Reset Ehc
1376
1377 Arguments:
1378
1379 HcDev - USB2_HC_DEV
1380
1381 Returns:
1382
1383 EFI_SUCCESS Success
1384 EFI_DEVICE_ERROR Fail
1385
1386 --*/
1387 ;
1388
1389 EFI_STATUS
1390 ClearEhcAllStatus (
1391 IN USB2_HC_DEV *HcDev
1392 )
1393 /*++
1394
1395 Routine Description:
1396
1397 Clear Ehc all status bits
1398
1399 Arguments:
1400
1401 HcDev - USB2_HC_DEV
1402
1403 Returns:
1404
1405 EFI_SUCCESS Success
1406 EFI_DEVICE_ERROR Fail
1407
1408 --*/
1409 ;
1410
1411 //
1412 // EhciSched Functions
1413 //
1414 EFI_STATUS
1415 InitialPeriodicFrameList (
1416 IN USB2_HC_DEV *HcDev,
1417 IN UINTN Length
1418 )
1419 /*++
1420
1421 Routine Description:
1422
1423 Initialize Periodic Schedule Frame List
1424
1425 Arguments:
1426
1427 HcDev - USB2_HC_DEV
1428 Length - Frame List Length
1429
1430 Returns:
1431
1432 EFI_SUCCESS Success
1433 EFI_DEVICE_ERROR Fail
1434
1435 --*/
1436 ;
1437
1438 VOID
1439 DeinitialPeriodicFrameList (
1440 IN USB2_HC_DEV *HcDev
1441 )
1442 /*++
1443
1444 Routine Description:
1445
1446 Deinitialize Periodic Schedule Frame List
1447
1448 Arguments:
1449
1450 HcDev - USB2_HC_DEV
1451
1452 Returns:
1453
1454 VOID
1455
1456 --*/
1457 ;
1458
1459 EFI_STATUS
1460 CreatePollingTimer (
1461 IN USB2_HC_DEV *HcDev,
1462 IN EFI_EVENT_NOTIFY NotifyFunction
1463 )
1464 /*++
1465
1466 Routine Description:
1467
1468 Create Async Request Polling Timer
1469
1470 Arguments:
1471
1472 HcDev - USB2_HC_DEV
1473 NotifyFunction - Timer Notify Function
1474
1475 Returns:
1476
1477 EFI_SUCCESS Success
1478 EFI_DEVICE_ERROR Fail
1479
1480 --*/
1481 ;
1482
1483 EFI_STATUS
1484 DestoryPollingTimer (
1485 IN USB2_HC_DEV *HcDev
1486 )
1487 /*++
1488
1489 Routine Description:
1490
1491 Destory Async Request Polling Timer
1492
1493 Arguments:
1494
1495 HcDev - USB2_HC_DEV
1496
1497 Returns:
1498
1499 EFI_SUCCESS Success
1500 EFI_DEVICE_ERROR Fail
1501
1502 --*/
1503 ;
1504
1505 EFI_STATUS
1506 StartPollingTimer (
1507 IN USB2_HC_DEV *HcDev
1508 )
1509 /*++
1510
1511 Routine Description:
1512
1513 Start Async Request Polling Timer
1514
1515 Arguments:
1516
1517 HcDev - USB2_HC_DEV
1518
1519 Returns:
1520
1521 EFI_SUCCESS Success
1522 EFI_DEVICE_ERROR Fail
1523
1524 --*/
1525 ;
1526
1527 EFI_STATUS
1528 StopPollingTimer (
1529 IN USB2_HC_DEV *HcDev
1530 )
1531 /*++
1532
1533 Routine Description:
1534
1535 Stop Async Request Polling Timer
1536
1537 Arguments:
1538
1539 HcDev - USB2_HC_DEV
1540
1541 Returns:
1542
1543 EFI_SUCCESS Success
1544 EFI_DEVICE_ERROR Fail
1545
1546 --*/
1547 ;
1548
1549 EFI_STATUS
1550 CreateQh (
1551 IN USB2_HC_DEV *HcDev,
1552 IN UINT8 DeviceAddr,
1553 IN UINT8 Endpoint,
1554 IN UINT8 DeviceSpeed,
1555 IN UINTN MaxPacketLen,
1556 OUT EHCI_QH_ENTITY **QhPtrPtr
1557 )
1558 /*++
1559
1560 Routine Description:
1561
1562 Create Qh Structure and Pre-Initialize
1563
1564 Arguments:
1565
1566 HcDev - USB2_HC_DEV
1567 DeviceAddr - Address of Device
1568 Endpoint - Endpoint Number
1569 DeviceSpeed - Device Speed
1570 MaxPacketLen - Max Length of one Packet
1571 QhPtrPtr - A pointer of pointer to Qh for return
1572
1573 Returns:
1574
1575 EFI_SUCCESS Success
1576 EFI_DEVICE_ERROR Fail
1577
1578 --*/
1579 ;
1580
1581 EFI_STATUS
1582 CreateControlQh (
1583 IN USB2_HC_DEV *HcDev,
1584 IN UINT8 DeviceAddr,
1585 IN UINT8 DeviceSpeed,
1586 IN UINTN MaxPacketLen,
1587 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1588 OUT EHCI_QH_ENTITY **QhPtrPtr
1589 )
1590 /*++
1591
1592 Routine Description:
1593
1594 Create Qh for Control Transfer
1595
1596 Arguments:
1597
1598 HcDev - USB2_HC_DEV
1599 DeviceAddr - Address of Device
1600 DeviceSpeed - Device Speed
1601 MaxPacketLen - Max Length of one Packet
1602 Translator - Translator Transaction for SplitX
1603 QhPtrPtr - A pointer of pointer to Qh for return
1604
1605 Returns:
1606
1607 EFI_SUCCESS Success
1608 EFI_DEVICE_ERROR Fail
1609
1610 --*/
1611 ;
1612
1613 EFI_STATUS
1614 CreateBulkQh (
1615 IN USB2_HC_DEV *HcDev,
1616 IN UINT8 DeviceAddr,
1617 IN UINT8 EndPointAddr,
1618 IN UINT8 DeviceSpeed,
1619 IN UINT8 DataToggle,
1620 IN UINTN MaxPacketLen,
1621 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1622 OUT EHCI_QH_ENTITY **QhPtrPtr
1623 )
1624 /*++
1625
1626 Routine Description:
1627
1628 Create Qh for Bulk Transfer
1629
1630 Arguments:
1631
1632 HcDev - USB2_HC_DEV
1633 DeviceAddr - Address of Device
1634 EndPointAddr - Address of Endpoint
1635 DeviceSpeed - Device Speed
1636 MaxPacketLen - Max Length of one Packet
1637 Translator - Translator Transaction for SplitX
1638 QhPtrPtr - A pointer of pointer to Qh for return
1639
1640 Returns:
1641
1642 EFI_SUCCESS Success
1643 EFI_DEVICE_ERROR Fail
1644
1645 --*/
1646 ;
1647
1648 EFI_STATUS
1649 CreateInterruptQh (
1650 IN USB2_HC_DEV *HcDev,
1651 IN UINT8 DeviceAddr,
1652 IN UINT8 EndPointAddr,
1653 IN UINT8 DeviceSpeed,
1654 IN UINT8 DataToggle,
1655 IN UINTN MaxPacketLen,
1656 IN UINTN Interval,
1657 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1658 OUT EHCI_QH_ENTITY **QhPtrPtr
1659 )
1660 /*++
1661
1662 Routine Description:
1663
1664 Create Qh for Control Transfer
1665
1666 Arguments:
1667
1668 HcDev - USB2_HC_DEV
1669 DeviceAddr - Address of Device
1670 EndPointAddr - Address of Endpoint
1671 DeviceSpeed - Device Speed
1672 MaxPacketLen - Max Length of one Packet
1673 Interval - value of interval
1674 Translator - Translator Transaction for SplitX
1675 QhPtrPtr - A pointer of pointer to Qh for return
1676
1677 Returns:
1678
1679 EFI_SUCCESS Success
1680 EFI_DEVICE_ERROR Fail
1681
1682 --*/
1683 ;
1684
1685 VOID
1686 DestoryQh (
1687 IN USB2_HC_DEV *HcDev,
1688 IN EHCI_QH_ENTITY *QhPtr
1689 )
1690 /*++
1691
1692 Routine Description:
1693
1694 Destory Qh Structure
1695
1696 Arguments:
1697
1698 HcDev - USB2_HC_DEV
1699 QhPtr - A pointer to Qh
1700
1701 Returns:
1702
1703 VOID
1704
1705 --*/
1706 ;
1707
1708 EFI_STATUS
1709 CreateQtd (
1710 IN USB2_HC_DEV *HcDev,
1711 IN UINT8 *DataPtr,
1712 IN UINTN DataLen,
1713 IN UINT8 PktId,
1714 IN UINT8 Toggle,
1715 IN UINT8 QtdStatus,
1716 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1717 )
1718 /*++
1719
1720 Routine Description:
1721
1722 Create Qtd Structure and Pre-Initialize it
1723
1724 Arguments:
1725
1726 HcDev - USB2_HC_DEV
1727 DataPtr - A pointer to user data buffer to transfer
1728 DataLen - Length of user data to transfer
1729 PktId - Packet Identification of this Qtd
1730 Toggle - Data Toggle of this Qtd
1731 QtdStatus - Default value of status of this Qtd
1732 QtdPtrPtr - A pointer of pointer to Qtd for return
1733
1734 Returns:
1735
1736 EFI_SUCCESS Success
1737 EFI_OUT_OF_RESOURCES Cannot allocate resources
1738
1739 --*/
1740 ;
1741
1742 EFI_STATUS
1743 CreateSetupQtd (
1744 IN USB2_HC_DEV *HcDev,
1745 IN UINT8 *DevReqPtr,
1746 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1747 )
1748 /*++
1749
1750 Routine Description:
1751
1752 Create Qtd Structure for Setup
1753
1754 Arguments:
1755
1756 HcDev - USB2_HC_DEV
1757 DevReqPtr - A pointer to Device Request Data
1758 QtdPtrPtr - A pointer of pointer to Qtd for return
1759
1760 Returns:
1761
1762 EFI_SUCCESS Success
1763 EFI_OUT_OF_RESOURCES Cannot allocate resources
1764
1765 --*/
1766 ;
1767
1768 EFI_STATUS
1769 CreateDataQtd (
1770 IN USB2_HC_DEV *HcDev,
1771 IN UINT8 *DataPtr,
1772 IN UINTN DataLen,
1773 IN UINT8 PktId,
1774 IN UINT8 Toggle,
1775 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1776 )
1777 /*++
1778
1779 Routine Description:
1780
1781 Create Qtd Structure for data
1782
1783 Arguments:
1784
1785 HcDev - USB2_HC_DEV
1786 DataPtr - A pointer to user data buffer to transfer
1787 DataLen - Length of user data to transfer
1788 PktId - Packet Identification of this Qtd
1789 Toggle - Data Toggle of this Qtd
1790 QtdPtrPtr - A pointer of pointer to Qtd for return
1791
1792 Returns:
1793
1794 EFI_SUCCESS Success
1795 EFI_OUT_OF_RESOURCES Cannot allocate resources
1796
1797 --*/
1798 ;
1799
1800 EFI_STATUS
1801 CreateStatusQtd (
1802 IN USB2_HC_DEV *HcDev,
1803 IN UINT8 PktId,
1804 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1805 )
1806 /*++
1807
1808 Routine Description:
1809
1810 Create Qtd Structure for status
1811
1812 Arguments:
1813
1814 HcDev - USB2_HC_DEV
1815 PktId - Packet Identification of this Qtd
1816 QtdPtrPtr - A pointer of pointer to Qtd for return
1817
1818 Returns:
1819
1820 EFI_SUCCESS Success
1821 EFI_OUT_OF_RESOURCES Cannot allocate resources
1822
1823 --*/
1824 ;
1825
1826 EFI_STATUS
1827 CreateAltQtd (
1828 IN USB2_HC_DEV *HcDev,
1829 IN UINT8 PktId,
1830 OUT EHCI_QTD_ENTITY **QtdPtrPtr
1831 )
1832 /*++
1833
1834 Routine Description:
1835
1836 Create Qtd Structure for Alternative
1837
1838 Arguments:
1839
1840 HcDev - USB2_HC_DEV
1841 PktId - Packet Identification of this Qtd
1842 QtdPtrPtr - A pointer of pointer to Qtd for return
1843
1844 Returns:
1845
1846 EFI_SUCCESS Success
1847 EFI_OUT_OF_RESOURCES Cannot allocate resources
1848
1849 --*/
1850 ;
1851
1852 EFI_STATUS
1853 CreateControlQtds (
1854 IN USB2_HC_DEV *HcDev,
1855 IN UINT8 DataPktId,
1856 IN UINT8 *RequestCursor,
1857 IN UINT8 *DataCursor,
1858 IN UINTN DataLen,
1859 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1860 OUT EHCI_QTD_ENTITY **ControlQtdsHead
1861 )
1862 /*++
1863
1864 Routine Description:
1865
1866 Create Qtds list for Control Transfer
1867
1868 Arguments:
1869
1870 HcDev - USB2_HC_DEV
1871 DataPktId - Packet Identification of Data Qtds
1872 RequestCursor - A pointer to request structure buffer to transfer
1873 DataCursor - A pointer to user data buffer to transfer
1874 DataLen - Length of user data to transfer
1875 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return
1876
1877 Returns:
1878
1879 EFI_SUCCESS Success
1880 EFI_DEVICE_ERROR Fail
1881
1882 --*/
1883 ;
1884
1885 EFI_STATUS
1886 CreateBulkOrInterruptQtds (
1887 IN USB2_HC_DEV *HcDev,
1888 IN UINT8 PktId,
1889 IN UINT8 *DataCursor,
1890 IN UINTN DataLen,
1891 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
1892 OUT EHCI_QTD_ENTITY **QtdsHead
1893 )
1894 /*++
1895
1896 Routine Description:
1897
1898 Create Qtds list for Bulk or Interrupt Transfer
1899
1900 Arguments:
1901
1902 HcDev - USB2_HC_DEV
1903 PktId - Packet Identification of Qtds
1904 DataCursor - A pointer to user data buffer to transfer
1905 DataLen - Length of user data to transfer
1906 DataToggle - Data Toggle to start
1907 Translator - Translator Transaction for SplitX
1908 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return
1909
1910 Returns:
1911
1912 EFI_SUCCESS Success
1913 EFI_DEVICE_ERROR Fail
1914
1915 --*/
1916 ;
1917
1918 VOID
1919 DestoryQtds (
1920 IN USB2_HC_DEV *HcDev,
1921 IN EHCI_QTD_ENTITY *FirstQtdPtr
1922 )
1923 /*++
1924
1925 Routine Description:
1926
1927 Destory all Qtds in the list
1928
1929 Arguments:
1930
1931 HcDev - USB2_HC_DEV
1932 FirstQtdPtr - A pointer to first Qtd in the list
1933
1934 Returns:
1935
1936 VOID
1937
1938 --*/
1939 ;
1940
1941 VOID
1942 LinkQtdToQtd (
1943 IN EHCI_QTD_ENTITY *PreQtdPtr,
1944 IN EHCI_QTD_ENTITY *QtdPtr
1945 )
1946 /*++
1947
1948 Routine Description:
1949
1950 Link Qtds together
1951
1952 Arguments:
1953
1954 PreQtdPtr - A pointer to pre Qtd
1955 QtdPtr - A pointer to next Qtd
1956
1957 Returns:
1958
1959 VOID
1960
1961 --*/
1962 ;
1963
1964 VOID
1965 LinkQtdsToAltQtd (
1966 IN EHCI_QTD_ENTITY *FirstQtdPtr,
1967 IN EHCI_QTD_ENTITY *AltQtdPtr
1968 )
1969 /*++
1970
1971 Routine Description:
1972
1973 Link AlterQtds together
1974
1975 Arguments:
1976
1977 FirstQtdPtr - A pointer to first Qtd in the list
1978 AltQtdPtr - A pointer to alternative Qtd
1979
1980 Returns:
1981 VOID
1982
1983 --*/
1984 ;
1985
1986 VOID
1987 LinkQtdToQh (
1988 IN EHCI_QH_ENTITY *QhPtr,
1989 IN EHCI_QTD_ENTITY *QtdEntryPtr
1990 )
1991 /*++
1992
1993 Routine Description:
1994
1995 Link Qtds list to Qh
1996
1997 Arguments:
1998
1999 QhPtr - A pointer to Qh
2000 QtdPtr - A pointer to first Qtd in the list
2001
2002 Returns:
2003
2004 VOID
2005
2006 --*/
2007 ;
2008
2009 EFI_STATUS
2010 LinkQhToAsyncList (
2011 IN USB2_HC_DEV *HcDev,
2012 IN EHCI_QH_ENTITY *QhPtr
2013 )
2014 /*++
2015
2016 Routine Description:
2017
2018 Link Qh to Async Schedule List
2019
2020 Arguments:
2021
2022 HcDev - USB2_HC_DEV
2023 QhPtr - A pointer to Qh
2024
2025 Returns:
2026
2027 EFI_SUCCESS Success
2028 EFI_DEVICE_ERROR Fail
2029
2030 --*/
2031 ;
2032
2033 EFI_STATUS
2034 UnlinkQhFromAsyncList (
2035 IN USB2_HC_DEV *HcDev,
2036 IN EHCI_QH_ENTITY *QhPtr
2037 )
2038 /*++
2039
2040 Routine Description:
2041
2042 Unlink Qh from Async Schedule List
2043
2044 Arguments:
2045
2046 HcDev - USB2_HC_DEV
2047 QhPtr - A pointer to Qh
2048
2049 Returns:
2050
2051 EFI_SUCCESS Success
2052 EFI_DEVICE_ERROR Fail
2053
2054 --*/
2055 ;
2056
2057 VOID
2058 LinkQhToPeriodicList (
2059 IN USB2_HC_DEV *HcDev,
2060 IN EHCI_QH_ENTITY *QhPtr
2061 )
2062 /*++
2063
2064 Routine Description:
2065
2066 Link Qh to Periodic Schedule List
2067
2068 Arguments:
2069
2070 HcDev - USB2_HC_DEV
2071 QhPtr - A pointer to Qh
2072
2073 Returns:
2074
2075 VOID
2076
2077 --*/
2078 ;
2079
2080 VOID
2081 UnlinkQhFromPeriodicList (
2082 IN USB2_HC_DEV *HcDev,
2083 IN EHCI_QH_ENTITY *QhPtr,
2084 IN UINTN Interval
2085 )
2086 /*++
2087
2088 Routine Description:
2089
2090 Unlink Qh from Periodic Schedule List
2091
2092 Arguments:
2093
2094 HcDev - USB2_HC_DEV
2095 QhPtr - A pointer to Qh
2096 Interval - Interval of this periodic transfer
2097
2098 Returns:
2099
2100 VOID
2101
2102 --*/
2103 ;
2104
2105 VOID
2106 LinkToAsyncReqeust (
2107 IN USB2_HC_DEV *HcDev,
2108 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr
2109 )
2110 /*++
2111
2112 Routine Description:
2113
2114 Llink AsyncRequest Entry to Async Request List
2115
2116 Arguments:
2117
2118 HcDev - USB2_HC_DEV
2119 AsyncRequestPtr - A pointer to Async Request Entry
2120
2121 Returns:
2122
2123 VOID
2124
2125 --*/
2126 ;
2127
2128 VOID
2129 UnlinkFromAsyncReqeust (
2130 IN USB2_HC_DEV *HcDev,
2131 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr
2132 )
2133 /*++
2134
2135 Routine Description:
2136
2137 Unlink AsyncRequest Entry from Async Request List
2138
2139 Arguments:
2140
2141 HcDev - USB2_HC_DEV
2142 AsyncRequestPtr - A pointer to Async Request Entry
2143
2144 Returns:
2145
2146 VOID
2147
2148 --*/
2149 ;
2150
2151 UINTN
2152 GetNumberOfQtd (
2153 IN EHCI_QTD_ENTITY *FirstQtdPtr
2154 )
2155 /*++
2156
2157 Routine Description:
2158
2159 Number of Qtds in the list
2160
2161 Arguments:
2162
2163 FirstQtdPtr - A pointer to first Qtd in the list
2164
2165 Returns:
2166
2167 Number of Qtds in the list
2168
2169 --*/
2170 ;
2171
2172 UINTN
2173 GetNumberOfTransaction (
2174 IN UINTN SizeOfData,
2175 IN UINTN SizeOfTransaction
2176 )
2177 /*++
2178
2179 Routine Description:
2180
2181 Number of Transactions in one Qtd
2182
2183 Arguments:
2184
2185 SizeOfData - Size of one Qtd
2186 SizeOfTransaction - Size of one Transaction
2187
2188 Returns:
2189
2190 Number of Transactions in this Qtd
2191
2192 --*/
2193 ;
2194
2195 UINTN
2196 GetCapacityOfQtd (
2197 IN UINT8 *BufferCursor
2198 )
2199 /*++
2200
2201 Routine Description:
2202
2203 Get Capacity of Qtd
2204
2205 Arguments:
2206
2207 BufferCursor - BufferCursor of the Qtd
2208
2209 Returns:
2210
2211 Capacity of Qtd
2212
2213 --*/
2214 ;
2215
2216 UINTN
2217 GetApproxiOfInterval (
2218 IN UINTN Interval
2219 )
2220 /*++
2221
2222 Routine Description:
2223
2224 Get the approximate value in the 2 index sequence
2225
2226 Arguments:
2227
2228 Interval - the value of interval
2229
2230 Returns:
2231
2232 approximate value of interval in the 2 index sequence
2233
2234 --*/
2235 ;
2236
2237 EHCI_QTD_HW *
2238 GetQtdNextPointer (
2239 IN EHCI_QTD_HW *HwQtdPtr
2240 )
2241 /*++
2242
2243 Routine Description:
2244
2245 Get Qtd next pointer field
2246
2247 Arguments:
2248
2249 HwQtdPtr - A pointer to hardware Qtd structure
2250
2251 Returns:
2252
2253 A pointer to next hardware Qtd structure
2254
2255 --*/
2256 ;
2257
2258 BOOLEAN
2259 IsQtdStatusActive (
2260 IN EHCI_QTD_HW *HwQtdPtr
2261 )
2262 /*++
2263
2264 Routine Description:
2265
2266 Whether Qtd status is active or not
2267
2268 Arguments:
2269
2270 HwQtdPtr - A pointer to hardware Qtd structure
2271
2272 Returns:
2273
2274 TRUE Active
2275 FALSE Inactive
2276
2277 --*/
2278 ;
2279
2280 BOOLEAN
2281 IsQtdStatusHalted (
2282 IN EHCI_QTD_HW *HwQtdPtr
2283 )
2284 /*++
2285
2286 Routine Description:
2287
2288 Whether Qtd status is halted or not
2289
2290 Arguments:
2291
2292 HwQtdPtr - A pointer to hardware Qtd structure
2293
2294 Returns:
2295
2296 TRUE Halted
2297 FALSE Not halted
2298
2299 --*/
2300 ;
2301
2302 BOOLEAN
2303 IsQtdStatusBufferError (
2304 IN EHCI_QTD_HW *HwQtdPtr
2305 )
2306 /*++
2307
2308 Routine Description:
2309
2310 Whether Qtd status is buffer error or not
2311
2312 Arguments:
2313
2314 HwQtdPtr - A pointer to hardware Qtd structure
2315
2316 Returns:
2317
2318 TRUE Buffer error
2319 FALSE No buffer error
2320
2321 --*/
2322 ;
2323
2324 BOOLEAN
2325 IsQtdStatusBabbleError (
2326 IN EHCI_QTD_HW *HwQtdPtr
2327 )
2328 /*++
2329
2330 Routine Description:
2331
2332 Whether Qtd status is babble error or not
2333
2334 Arguments:
2335
2336 HwQtdPtr - A pointer to hardware Qtd structure
2337
2338 Returns:
2339
2340 TRUE Babble error
2341 FALSE No babble error
2342
2343 --*/
2344 ;
2345
2346 BOOLEAN
2347 IsQtdStatusTransactionError (
2348 IN EHCI_QTD_HW *HwQtdPtr
2349 )
2350 /*++
2351
2352 Routine Description:
2353
2354 Whether Qtd status is transaction error or not
2355
2356 Arguments:
2357
2358 HwQtdPtr - A pointer to hardware Qtd structure
2359
2360 Returns:
2361
2362 TRUE Transaction error
2363 FALSE No transaction error
2364
2365 --*/
2366 ;
2367
2368 BOOLEAN
2369 IsDataInTransfer (
2370 IN UINT8 EndPointAddress
2371 )
2372 /*++
2373
2374 Routine Description:
2375
2376 Whether is a DataIn direction transfer
2377
2378 Arguments:
2379
2380 EndPointAddress - address of the endpoint
2381
2382 Returns:
2383
2384 TRUE DataIn
2385 FALSE DataOut
2386
2387 --*/
2388 ;
2389
2390 EFI_STATUS
2391 MapDataBuffer (
2392 IN USB2_HC_DEV *HcDev,
2393 IN EFI_USB_DATA_DIRECTION TransferDirection,
2394 IN OUT VOID *Data,
2395 IN OUT UINTN *DataLength,
2396 OUT UINT8 *PktId,
2397 OUT UINT8 **DataCursor,
2398 OUT VOID **DataMap
2399 )
2400 /*++
2401
2402 Routine Description:
2403
2404 Map address of user data buffer
2405
2406 Arguments:
2407
2408 HcDev - USB2_HC_DEV
2409 TransferDirection - direction of transfer
2410 Data - A pointer to user data buffer
2411 DataLength - length of user data
2412 PktId - Packte Identificaion
2413 DataCursor - mapped address to return
2414 DataMap - identificaion of this mapping to return
2415
2416 Returns:
2417
2418 EFI_SUCCESS Success
2419 EFI_DEVICE_ERROR Fail
2420
2421 --*/
2422 ;
2423
2424 EFI_STATUS
2425 MapRequestBuffer (
2426 IN USB2_HC_DEV *HcDev,
2427 IN OUT VOID *Request,
2428 OUT UINT8 **RequestCursor,
2429 OUT VOID **RequestMap
2430 )
2431 /*++
2432
2433 Routine Description:
2434
2435 Map address of request structure buffer
2436
2437 Arguments:
2438
2439 HcDev - USB2_HC_DEV
2440 Request - A pointer to request structure
2441 RequestCursor - Mapped address of request structure to return
2442 RequestMap - Identificaion of this mapping to return
2443
2444 Returns:
2445
2446 EFI_SUCCESS Success
2447 EFI_DEVICE_ERROR Fail
2448
2449 --*/
2450 ;
2451
2452 VOID
2453 SetQtdBufferPointer (
2454 IN EHCI_QTD_HW *QtdHwPtr,
2455 IN VOID *DataPtr,
2456 IN UINTN DataLen
2457 )
2458 /*++
2459
2460 Routine Description:
2461
2462 Set data buffer pointers in Qtd
2463
2464 Arguments:
2465
2466 QtdHwPtr - A pointer to Qtd hardware structure
2467 DataPtr - A pointer to user data buffer
2468 DataLen - Length of the user data buffer
2469
2470 Returns:
2471
2472 VOID
2473
2474 --*/
2475 ;
2476
2477 EHCI_QTD_HW *
2478 GetQtdAlternateNextPointer (
2479 IN EHCI_QTD_HW *HwQtdPtr
2480 )
2481 /*++
2482
2483 Routine Description:
2484
2485 Get Qtd alternate next pointer field
2486
2487 Arguments:
2488
2489 HwQtdPtr - A pointer to hardware Qtd structure
2490
2491 Returns:
2492
2493 A pointer to hardware alternate Qtd
2494
2495 --*/
2496 ;
2497
2498 VOID
2499 ZeroOutQhOverlay (
2500 IN EHCI_QH_ENTITY *QhPtr
2501 )
2502 /*++
2503
2504 Routine Description:
2505
2506 Zero out the fields in Qh structure
2507
2508 Arguments:
2509
2510 QhPtr - A pointer to Qh structure
2511
2512 Returns:
2513
2514 VOID
2515
2516 --*/
2517 ;
2518
2519 VOID
2520 UpdateAsyncRequestTransfer (
2521 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,
2522 IN UINT32 TransferResult,
2523 IN UINTN ErrTDPos
2524 )
2525 /*++
2526
2527 Routine Description:
2528
2529 Update asynchronous request transfer
2530
2531 Arguments:
2532
2533 AsyncRequestPtr - A pointer to async request
2534 TransferResult - transfer result
2535 ErrQtdPos - postion of error Qtd
2536
2537 Returns:
2538
2539 VOID
2540
2541 --*/
2542 ;
2543
2544
2545 EFI_STATUS
2546 DeleteAsyncRequestTransfer (
2547 IN USB2_HC_DEV *HcDev,
2548 IN UINT8 DeviceAddress,
2549 IN UINT8 EndPointAddress,
2550 OUT UINT8 *DataToggle
2551 )
2552 /*++
2553
2554 Routine Description:
2555
2556 Delete all asynchronous request transfer
2557
2558 Arguments:
2559
2560 HcDev - USB2_HC_DEV
2561 DeviceAddress - address of usb device
2562 EndPointAddress - address of endpoint
2563 DataToggle - stored data toggle
2564
2565 Returns:
2566
2567 EFI_SUCCESS Success
2568 EFI_DEVICE_ERROR Fail
2569
2570 --*/
2571 ;
2572
2573 VOID
2574 CleanUpAllAsyncRequestTransfer (
2575 IN USB2_HC_DEV *HcDev
2576 )
2577 /*++
2578
2579 Routine Description:
2580
2581 Clean up all asynchronous request transfer
2582
2583 Arguments:
2584
2585 HcDev - USB2_HC_DEV
2586
2587 Returns:
2588 VOID
2589
2590 --*/
2591 ;
2592
2593 EFI_STATUS
2594 ExecuteTransfer (
2595 IN USB2_HC_DEV *HcDev,
2596 IN BOOLEAN IsControl,
2597 IN EHCI_QH_ENTITY *QhPtr,
2598 IN OUT UINTN *ActualLen,
2599 OUT UINT8 *DataToggle,
2600 IN UINTN TimeOut,
2601 OUT UINT32 *TransferResult
2602 )
2603 /*++
2604
2605 Routine Description:
2606
2607 Execute Bulk or SyncInterrupt Transfer
2608
2609 Arguments:
2610
2611 HcDev - USB2_HC_DEV
2612 IsControl - Is control transfer or not
2613 QhPtr - A pointer to Qh
2614 ActualLen - Actual transfered Len
2615 DataToggle - Data Toggle
2616 TimeOut - TimeOut threshold
2617 TransferResult - Transfer result
2618
2619 Returns:
2620
2621 EFI_SUCCESS Sucess
2622 EFI_DEVICE_ERROR Error
2623
2624 --*/
2625 ;
2626
2627 BOOLEAN
2628 CheckQtdsTransferResult (
2629 IN BOOLEAN IsControl,
2630 IN EHCI_QH_ENTITY *QhPtr,
2631 OUT UINT32 *Result,
2632 OUT UINTN *ErrQtdPos,
2633 OUT UINTN *ActualLen
2634 )
2635 /*++
2636
2637 Routine Description:
2638
2639 Check transfer result of Qtds
2640
2641 Arguments:
2642
2643 IsControl - Is control transfer or not
2644 QhPtr - A pointer to Qh
2645 Result - Transfer result
2646 ErrQtdPos - Error TD Position
2647 ActualLen - Actual Transfer Size
2648
2649 Returns:
2650
2651 TRUE Qtds finished
2652 FALSE Not finish
2653
2654 --*/
2655 ;
2656
2657 EFI_STATUS
2658 AsyncRequestMoniter (
2659 IN EFI_EVENT Event,
2660 IN VOID *Context
2661 )
2662 /*++
2663
2664 Routine Description:
2665
2666 Interrupt transfer periodic check handler
2667
2668 Arguments:
2669
2670 Event - Interrupt event
2671 Context - Pointer to USB2_HC_DEV
2672
2673 Returns:
2674
2675 EFI_SUCCESS Success
2676 EFI_DEVICE_ERROR Fail
2677
2678 --*/
2679 ;
2680
2681 #endif