]> git.proxmox.com Git - mirror_edk2.git/blob - EdkModulePkg/Bus/Pci/IdeBus/Dxe/ata.c
projects / mirror_edk2.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Make EdkModulePkg pass Intel IPF compiler with /W4 /WX switches, solving warning...
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / IdeBus / Dxe / ata.c
1 /** @file
2 Copyright (c) 2006, Intel Corporation
3 All rights reserved. This program and the accompanying materials
4 are licensed and made available under the terms and conditions of the BSD License
5 which accompanies this distribution. The full text of the license may be found at
6 http://opensource.org/licenses/bsd-license.php
7
8 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
10
11 @par Revision Reference:
12 2002-6: Add Atapi6 enhancement, support >120GB hard disk, including
13 update - ATAIdentity() func
14 update - AtaBlockIoReadBlocks() func
15 update - AtaBlockIoWriteBlocks() func
16 add - AtaAtapi6Identify() func
17 add - AtaReadSectorsExt() func
18 add - AtaWriteSectorsExt() func
19 add - AtaPioDataInExt() func
20 add - AtaPioDataOutExt() func
21
22 **/
23
24 #include "idebus.h"
25
26 /**
27 Sends out an ATA Identify Command to the specified device.
28
29 This function is called by DiscoverIdeDevice() during its device
30 identification. It sends out the ATA Identify Command to the
31 specified device. Only ATA device responses to this command. If
32 the command succeeds, it returns the Identify data structure which
33 contains information about the device. This function extracts the
34 information it needs to fill the IDE_BLK_IO_DEV data structure,
35 including device type, media block size, media capacity, and etc.
36
37 @param[in] *IdeDev
38 pointer pointing to IDE_BLK_IO_DEV data structure,used
39 to record all the information of the IDE device.
40
41 @retval EFI_SUCCESS Identify ATA device successfully.
42
43 @retval EFI_DEVICE_ERROR ATA Identify Device Command failed or
44 device is not ATA device.
45
46 @note
47 parameter IdeDev will be updated in this function.
48
49 **/
50 EFI_STATUS
51 ATAIdentify (
52 IN IDE_BLK_IO_DEV *IdeDev
53 )
54 {
55 EFI_STATUS Status;
56 EFI_IDENTIFY_DATA *AtaIdentifyPointer;
57 UINT32 Capacity;
58 UINT8 DeviceSelect;
59
60 //
61 // AtaIdentifyPointer is used for accommodating returned IDENTIFY data of
62 // the ATA Identify command
63 //
64 AtaIdentifyPointer = (EFI_IDENTIFY_DATA *) AllocateZeroPool (sizeof (EFI_IDENTIFY_DATA));
65
66 //
67 // use ATA PIO Data In protocol to send ATA Identify command
68 // and receive data from device
69 //
70 DeviceSelect = 0;
71 DeviceSelect = (UINT8) ((IdeDev->Device) << 4);
72 Status = AtaPioDataIn (
73 IdeDev,
74 (VOID *) AtaIdentifyPointer,
75 sizeof (EFI_IDENTIFY_DATA),
76 IDENTIFY_DRIVE_CMD,
77 DeviceSelect,
78 0,
79 0,
80 0,
81 0
82 );
83 //
84 // If ATA Identify command succeeds, then according to the received
85 // IDENTIFY data,
86 // identify the device type ( ATA or not ).
87 // If ATA device, fill the information in IdeDev.
88 // If not ATA device, return IDE_DEVICE_ERROR
89 //
90 if (!EFI_ERROR (Status)) {
91
92 IdeDev->pIdData = AtaIdentifyPointer;
93
94 //
95 // Print ATA Module Name
96 //
97 PrintAtaModuleName (IdeDev);
98
99 //
100 // bit 15 of pAtaIdentify->config is used to identify whether device is
101 // ATA device or ATAPI device.
102 // if 0, means ATA device; if 1, means ATAPI device.
103 //
104 if ((AtaIdentifyPointer->AtaData.config & 0x8000) == 0x00) {
105 //
106 // Detect if support S.M.A.R.T. If yes, enable it as default
107 //
108 AtaSMARTSupport (IdeDev);
109
110 //
111 // Check whether this device needs 48-bit addressing (ATAPI-6 ata device)
112 //
113 Status = AtaAtapi6Identify (IdeDev);
114 if (!EFI_ERROR (Status)) {
115 //
116 // It's a disk with >120GB capacity, initialized in AtaAtapi6Identify()
117 //
118 return EFI_SUCCESS;
119 }
120 //
121 // This is a hard disk <= 120GB capacity, treat it as normal hard disk
122 //
123 IdeDev->Type = IdeHardDisk;
124
125 //
126 // Block Media Information:
127 // Media->LogicalPartition , Media->WriteCaching will be filled
128 // in the DiscoverIdeDevcie() function.
129 //
130 IdeDev->BlkIo.Media->IoAlign = 4;
131 IdeDev->BlkIo.Media->MediaId = 1;
132 IdeDev->BlkIo.Media->RemovableMedia = FALSE;
133 IdeDev->BlkIo.Media->MediaPresent = TRUE;
134 IdeDev->BlkIo.Media->ReadOnly = FALSE;
135 IdeDev->BlkIo.Media->BlockSize = 0x200;
136
137 //
138 // Calculate device capacity
139 //
140 Capacity = ((UINT32)AtaIdentifyPointer->AtaData.user_addressable_sectors_hi << 16) |
141 AtaIdentifyPointer->AtaData.user_addressable_sectors_lo ;
142 IdeDev->BlkIo.Media->LastBlock = Capacity - 1;
143
144 return EFI_SUCCESS;
145
146 }
147 }
148
149 gBS->FreePool (AtaIdentifyPointer);
150 //
151 // Make sure the pIdData will not be freed again.
152 //
153 IdeDev->pIdData = NULL;
154
155 return EFI_DEVICE_ERROR;
156 }
157
158
159 /**
160 This function is called by ATAIdentify() to identity whether this disk
161 supports ATA/ATAPI6 48bit addressing, ie support >120G capacity
162
163 @param[in] *IdeDev
164 pointer pointing to IDE_BLK_IO_DEV data structure, used
165 to record all the information of the IDE device.
166
167 @retval EFI_SUCCESS The disk specified by IdeDev is a Atapi6 supported one
168 and 48-bit addressing must be used
169
170 @retval EFI_UNSUPPORTED The disk dosn't not support Atapi6 or it supports but
171 the capacity is below 120G, 48bit addressing is not
172 needed
173
174 @note
175 This function must be called after DEVICE_IDENTITY command has been
176 successfully returned
177
178 **/
179 EFI_STATUS
180 AtaAtapi6Identify (
181 IN IDE_BLK_IO_DEV *IdeDev
182 )
183 {
184 UINT8 Index;
185 EFI_LBA TmpLba;
186 EFI_LBA Capacity;
187 EFI_IDENTIFY_DATA *Atapi6IdentifyStruct;
188
189 if (IdeDev->pIdData == NULL) {
190 return EFI_UNSUPPORTED;
191 }
192
193 Atapi6IdentifyStruct = IdeDev->pIdData;
194
195 if ((Atapi6IdentifyStruct->AtapiData.cmd_set_support_83 & bit10) == 0) {
196 //
197 // The device dosn't support 48 bit addressing
198 //
199 return EFI_UNSUPPORTED;
200 }
201
202 //
203 // 48 bit address feature set is supported, get maximum capacity
204 //
205 Capacity = Atapi6IdentifyStruct->AtapiData.max_user_lba_for_48bit_addr[0];
206 for (Index = 1; Index < 4; Index++) {
207 //
208 // Lower byte goes first: word[100] is the lowest word, word[103] is highest
209 //
210 TmpLba = Atapi6IdentifyStruct->AtapiData.max_user_lba_for_48bit_addr[Index];
211 Capacity |= LShiftU64 (TmpLba, 16 * Index);
212 }
213
214 if (Capacity > MAX_28BIT_ADDRESSING_CAPACITY) {
215 //
216 // Capacity exceeds 120GB. 48-bit addressing is really needed
217 //
218 IdeDev->Type = Ide48bitAddressingHardDisk;
219
220 //
221 // Fill block media information:Media->LogicalPartition ,
222 // Media->WriteCaching will be filledin the DiscoverIdeDevcie() function.
223 //
224 IdeDev->BlkIo.Media->IoAlign = 4;
225 IdeDev->BlkIo.Media->MediaId = 1;
226 IdeDev->BlkIo.Media->RemovableMedia = FALSE;
227 IdeDev->BlkIo.Media->MediaPresent = TRUE;
228 IdeDev->BlkIo.Media->ReadOnly = FALSE;
229 IdeDev->BlkIo.Media->BlockSize = 0x200;
230 IdeDev->BlkIo.Media->LastBlock = Capacity - 1;
231
232 return EFI_SUCCESS;
233 }
234
235 return EFI_UNSUPPORTED;
236 }
237
238 /**
239 This function is called by ATAIdentify() or ATAPIIdentify()
240 to print device's module name.
241
242 @param[in] *IdeDev
243 pointer pointing to IDE_BLK_IO_DEV data structure, used
244 to record all the information of the IDE device.
245
246 **/
247 VOID
248 PrintAtaModuleName (
249 IN IDE_BLK_IO_DEV *IdeDev
250 )
251 {
252 if (IdeDev->pIdData == NULL) {
253 return ;
254 }
255
256 SwapStringChars (IdeDev->ModelName, IdeDev->pIdData->AtaData.ModelName, 40);
257 IdeDev->ModelName[40] = 0x00;
258 }
259
260 /**
261 This function is used to send out ATA commands conforms to the
262 PIO Data In Protocol.
263
264 @param[in] *IdeDev
265 pointer pointing to IDE_BLK_IO_DEV data structure, used
266 to record all the information of the IDE device.
267
268 @param[in] *Buffer
269 buffer contained data transferred from device to host.
270
271 @param[in] ByteCount
272 data size in byte unit of the buffer.
273
274 @param[in] AtaCommand
275 value of the Command Register
276
277 @param[in] Head
278 value of the Head/Device Register
279
280 @param[in] SectorCount
281 value of the Sector Count Register
282
283 @param[in] SectorNumber
284 value of the Sector Number Register
285
286 @param[in] CylinderLsb
287 value of the low byte of the Cylinder Register
288
289 @param[in] CylinderMsb
290 value of the high byte of the Cylinder Register
291
292 @retval EFI_SUCCESS send out the ATA command and device send required
293 data successfully.
294
295 @retval EFI_DEVICE_ERROR command sent failed.
296
297 **/
298 EFI_STATUS
299 AtaPioDataIn (
300 IN IDE_BLK_IO_DEV *IdeDev,
301 IN VOID *Buffer,
302 IN UINT32 ByteCount,
303 IN UINT8 AtaCommand,
304 IN UINT8 Head,
305 IN UINT8 SectorCount,
306 IN UINT8 SectorNumber,
307 IN UINT8 CylinderLsb,
308 IN UINT8 CylinderMsb
309 )
310 {
311 UINTN WordCount;
312 UINTN Increment;
313 UINT16 *Buffer16;
314 EFI_STATUS Status;
315
316 Status = WaitForBSYClear (IdeDev, ATATIMEOUT);
317 if (EFI_ERROR (Status)) {
318 return EFI_DEVICE_ERROR;
319 }
320
321 //
322 // e0:1110,0000-- bit7 and bit5 are reserved bits.
323 // bit6 set means LBA mode
324 //
325 IDEWritePortB (
326 IdeDev->PciIo,
327 IdeDev->IoPort->Head,
328 (UINT8) ((IdeDev->Device << 4) | 0xe0 | Head)
329 );
330
331 //
332 // All ATAPI device's ATA commands can be issued regardless of the
333 // state of the DRDY
334 //
335 if (IdeDev->Type == IdeHardDisk) {
336
337 Status = DRDYReady (IdeDev, ATATIMEOUT);
338 if (EFI_ERROR (Status)) {
339 return EFI_DEVICE_ERROR;
340 }
341 }
342 //
343 // set all the command parameters
344 // Before write to all the following registers, BSY and DRQ must be 0.
345 //
346 Status = DRQClear2 (IdeDev, ATATIMEOUT);
347 if (EFI_ERROR (Status)) {
348 return EFI_DEVICE_ERROR;
349 }
350
351 if (AtaCommand == SET_FEATURES_CMD) {
352 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, 0x03);
353 }
354
355 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount);
356 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, SectorNumber);
357 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, CylinderLsb);
358 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, CylinderMsb);
359
360 //
361 // send command via Command Register
362 //
363 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, AtaCommand);
364
365 Buffer16 = (UINT16 *) Buffer;
366
367 //
368 // According to PIO data in protocol, host can perform a series of reads to
369 // the data register after each time device set DRQ ready;
370 // The data size of "a series of read" is command specific.
371 // For most ATA command, data size received from device will not exceed
372 // 1 sector, hence the data size for "a series of read" can be the whole data
373 // size of one command request.
374 // For ATA command such as Read Sector command, the data size of one ATA
375 // command request is often larger than 1 sector, according to the
376 // Read Sector command, the data size of "a series of read" is exactly 1
377 // sector.
378 // Here for simplification reason, we specify the data size for
379 // "a series of read" to 1 sector (256 words) if data size of one ATA command
380 // request is larger than 256 words.
381 //
382 Increment = 256;
383
384 //
385 // used to record bytes of currently transfered data
386 //
387 WordCount = 0;
388
389 while (WordCount < ByteCount / 2) {
390 //
391 // Poll DRQ bit set, data transfer can be performed only when DRQ is ready.
392 //
393 Status = DRQReady2 (IdeDev, ATATIMEOUT);
394 if (EFI_ERROR (Status)) {
395 return EFI_DEVICE_ERROR;
396 }
397
398 Status = CheckErrorStatus (IdeDev);
399 if (EFI_ERROR (Status)) {
400 return EFI_DEVICE_ERROR;
401 }
402
403 //
404 // Get the byte count for one series of read
405 //
406 if ((WordCount + Increment) > ByteCount / 2) {
407 Increment = ByteCount / 2 - WordCount;
408 }
409
410 IDEReadPortWMultiple (
411 IdeDev->PciIo,
412 IdeDev->IoPort->Data,
413 Increment,
414 Buffer16
415 );
416
417 WordCount += Increment;
418 Buffer16 += Increment;
419
420 }
421
422 DRQClear (IdeDev, ATATIMEOUT);
423
424 return CheckErrorStatus (IdeDev);
425 }
426
427 /**
428 This function is used to send out ATA commands conforms to the
429 PIO Data Out Protocol.
430
431 @param *IdeDev
432 pointer pointing to IDE_BLK_IO_DEV data structure, used
433 to record all the information of the IDE device.
434
435 @param *Buffer buffer contained data transferred from host to device.
436 @param ByteCount data size in byte unit of the buffer.
437 @param AtaCommand value of the Command Register
438 @param Head value of the Head/Device Register
439 @param SectorCount value of the Sector Count Register
440 @param SectorNumber value of the Sector Number Register
441 @param CylinderLsb value of the low byte of the Cylinder Register
442 @param CylinderMsb value of the high byte of the Cylinder Register
443
444 @retval EFI_SUCCESS send out the ATA command and device received required
445 data successfully.
446
447 @retval EFI_DEVICE_ERROR command sent failed.
448
449 **/
450 EFI_STATUS
451 AtaPioDataOut (
452 IN IDE_BLK_IO_DEV *IdeDev,
453 IN VOID *Buffer,
454 IN UINT32 ByteCount,
455 IN UINT8 AtaCommand,
456 IN UINT8 Head,
457 IN UINT8 SectorCount,
458 IN UINT8 SectorNumber,
459 IN UINT8 CylinderLsb,
460 IN UINT8 CylinderMsb
461 )
462 {
463 UINTN WordCount;
464 UINTN Increment;
465 UINT16 *Buffer16;
466 EFI_STATUS Status;
467
468 Status = WaitForBSYClear (IdeDev, ATATIMEOUT);
469 if (EFI_ERROR (Status)) {
470 return EFI_DEVICE_ERROR;
471 }
472
473 //
474 // select device via Head/Device register.
475 // Before write Head/Device register, BSY and DRQ must be 0.
476 //
477 Status = DRQClear2 (IdeDev, ATATIMEOUT);
478 if (EFI_ERROR (Status)) {
479 return EFI_DEVICE_ERROR;
480 }
481
482 //
483 // e0:1110,0000-- bit7 and bit5 are reserved bits.
484 // bit6 set means LBA mode
485 //
486 IDEWritePortB (
487 IdeDev->PciIo,
488 IdeDev->IoPort->Head,
489 (UINT8) ((IdeDev->Device << 4) | 0xe0 | Head)
490 );
491
492 Status = DRDYReady (IdeDev, ATATIMEOUT);
493 if (EFI_ERROR (Status)) {
494 return EFI_DEVICE_ERROR;
495 }
496
497 //
498 // set all the command parameters
499 // Before write to all the following registers, BSY and DRQ must be 0.
500 //
501 Status = DRQClear2 (IdeDev, ATATIMEOUT);
502 if (EFI_ERROR (Status)) {
503 return EFI_DEVICE_ERROR;
504 }
505
506 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount);
507 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, SectorNumber);
508 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, CylinderLsb);
509 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, CylinderMsb);
510
511 //
512 // send command via Command Register
513 //
514 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, AtaCommand);
515
516 Buffer16 = (UINT16 *) Buffer;
517
518 //
519 // According to PIO data out protocol, host can perform a series of
520 // writes to the data register after each time device set DRQ ready;
521 // The data size of "a series of read" is command specific.
522 // For most ATA command, data size written to device will not exceed 1 sector,
523 // hence the data size for "a series of write" can be the data size of one
524 // command request.
525 // For ATA command such as Write Sector command, the data size of one
526 // ATA command request is often larger than 1 sector, according to the
527 // Write Sector command, the data size of "a series of read" is exactly
528 // 1 sector.
529 // Here for simplification reason, we specify the data size for
530 // "a series of write" to 1 sector (256 words) if data size of one ATA command
531 // request is larger than 256 words.
532 //
533 Increment = 256;
534 WordCount = 0;
535
536 while (WordCount < ByteCount / 2) {
537
538 //
539 // DRQReady2-- read Alternate Status Register to determine the DRQ bit
540 // data transfer can be performed only when DRQ is ready.
541 //
542 Status = DRQReady2 (IdeDev, ATATIMEOUT);
543 if (EFI_ERROR (Status)) {
544 return EFI_DEVICE_ERROR;
545 }
546
547 Status = CheckErrorStatus (IdeDev);
548 if (EFI_ERROR (Status)) {
549 return EFI_DEVICE_ERROR;
550 }
551
552 //
553 // Check the remaining byte count is less than 512 bytes
554 //
555 if ((WordCount + Increment) > ByteCount / 2) {
556 Increment = ByteCount / 2 - WordCount;
557 }
558 //
559 // perform a series of write without check DRQ ready
560 //
561
562 IDEWritePortWMultiple (
563 IdeDev->PciIo,
564 IdeDev->IoPort->Data,
565 Increment,
566 Buffer16
567 );
568 WordCount += Increment;
569 Buffer16 += Increment;
570
571 }
572
573 DRQClear (IdeDev, ATATIMEOUT);
574
575 return CheckErrorStatus (IdeDev);
576 }
577
578 /**
579 This function is used to analyze the Status Register and print out
580 some debug information and if there is ERR bit set in the Status
581 Register, the Error Register's value is also be parsed and print out.
582
583 @param[in] *IdeDev
584 pointer pointing to IDE_BLK_IO_DEV data structure, used
585 to record all the information of the IDE device.
586
587 @retval EFI_SUCCESS No err information in the Status Register.
588 @retval EFI_DEVICE_ERROR Any err information in the Status Register.
589
590 **/
591 EFI_STATUS
592 CheckErrorStatus (
593 IN IDE_BLK_IO_DEV *IdeDev
594 )
595 {
596 UINT8 StatusRegister;
597
598 //#ifdef EFI_DEBUG
599
600 UINT8 ErrorRegister;
601
602 //#endif
603
604 StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);
605
606 DEBUG_CODE_BEGIN ();
607
608 if (StatusRegister & DWF) {
609 DEBUG (
610 (EFI_D_BLKIO,
611 "CheckErrorStatus()-- %02x : Error : Write Fault\n",
612 StatusRegister)
613 );
614 }
615
616 if (StatusRegister & CORR) {
617 DEBUG (
618 (EFI_D_BLKIO,
619 "CheckErrorStatus()-- %02x : Error : Corrected Data\n",
620 StatusRegister)
621 );
622 }
623
624 if (StatusRegister & ERR) {
625 ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);
626
627 if (ErrorRegister & BBK_ERR) {
628 DEBUG (
629 (EFI_D_BLKIO,
630 "CheckErrorStatus()-- %02x : Error : Bad Block Detected\n",
631 ErrorRegister)
632 );
633 }
634
635 if (ErrorRegister & UNC_ERR) {
636 DEBUG (
637 (EFI_D_BLKIO,
638 "CheckErrorStatus()-- %02x : Error : Uncorrectable Data\n",
639 ErrorRegister)
640 );
641 }
642
643 if (ErrorRegister & MC_ERR) {
644 DEBUG (
645 (EFI_D_BLKIO,
646 "CheckErrorStatus()-- %02x : Error : Media Change\n",
647 ErrorRegister)
648 );
649 }
650
651 if (ErrorRegister & ABRT_ERR) {
652 DEBUG (
653 (EFI_D_BLKIO,
654 "CheckErrorStatus()-- %02x : Error : Abort\n",
655 ErrorRegister)
656 );
657 }
658
659 if (ErrorRegister & TK0NF_ERR) {
660 DEBUG (
661 (EFI_D_BLKIO,
662 "CheckErrorStatus()-- %02x : Error : Track 0 Not Found\n",
663 ErrorRegister)
664 );
665 }
666
667 if (ErrorRegister & AMNF_ERR) {
668 DEBUG (
669 (EFI_D_BLKIO,
670 "CheckErrorStatus()-- %02x : Error : Address Mark Not Found\n",
671 ErrorRegister)
672 );
673 }
674 }
675
676 DEBUG_CODE_END ();
677
678 if ((StatusRegister & (ERR | DWF | CORR)) == 0) {
679 return EFI_SUCCESS;
680 }
681
682 return EFI_DEVICE_ERROR;
683
684 }
685
686 /**
687 This function is called by the AtaBlkIoReadBlocks() to perform
688 reading from media in block unit.
689
690 @param[in] *IdeDev
691 pointer pointing to IDE_BLK_IO_DEV data structure, used
692 to record all the information of the IDE device.
693
694 @param[in] *DataBuffer
695 A pointer to the destination buffer for the data.
696
697 @param[in] Lba
698 The starting logical block address to read from
699 on the device media.
700
701 @param[in] NumberOfBlocks
702 The number of transfer data blocks.
703
704 @return return status is fully dependent on the return status
705 of AtaPioDataIn() function.
706
707 **/
708 EFI_STATUS
709 AtaReadSectors (
710 IN IDE_BLK_IO_DEV *IdeDev,
711 IN VOID *DataBuffer,
712 IN EFI_LBA Lba,
713 IN UINTN NumberOfBlocks
714 )
715 {
716 EFI_STATUS Status;
717 UINTN BlocksRemaining;
718 UINT32 Lba32;
719 UINT8 Lba0;
720 UINT8 Lba1;
721 UINT8 Lba2;
722 UINT8 Lba3;
723 UINT8 AtaCommand;
724 UINT8 SectorCount8;
725 UINT16 SectorCount;
726 UINTN ByteCount;
727 VOID *Buffer;
728
729 Buffer = DataBuffer;
730
731 //
732 // Using ATA Read Sector(s) command (opcode=0x20) with PIO DATA IN protocol
733 //
734 AtaCommand = READ_SECTORS_CMD;
735
736
737 BlocksRemaining = NumberOfBlocks;
738
739 Lba32 = (UINT32) Lba;
740
741 Status = EFI_SUCCESS;
742
743 while (BlocksRemaining > 0) {
744
745 //
746 // in ATA-3 spec, LBA is in 28 bit width
747 //
748 Lba0 = (UINT8) Lba32;
749 Lba1 = (UINT8) (Lba32 >> 8);
750 Lba2 = (UINT8) (Lba32 >> 16);
751 //
752 // low 4 bit of Lba3 stands for LBA bit24~bit27.
753 //
754 Lba3 = (UINT8) ((Lba32 >> 24) & 0x0f);
755
756 if (BlocksRemaining >= 0x100) {
757
758 //
759 // SectorCount8 is sent to Sector Count register, 0x00 means 256
760 // sectors to be read
761 //
762 SectorCount8 = 0x00;
763 //
764 // SectorCount is used to record the number of sectors to be read
765 //
766 SectorCount = 256;
767 } else {
768
769 SectorCount8 = (UINT8) BlocksRemaining;
770 SectorCount = (UINT16) BlocksRemaining;
771 }
772
773 //
774 // ByteCount is the number of bytes that will be read
775 //
776 ByteCount = SectorCount * (IdeDev->BlkIo.Media->BlockSize);
777
778 //
779 // call AtaPioDataIn() to send Read Sector Command and receive data read
780 //
781 Status = AtaPioDataIn (
782 IdeDev,
783 Buffer,
784 (UINT32) ByteCount,
785 AtaCommand,
786 Lba3,
787 SectorCount8,
788 Lba0,
789 Lba1,
790 Lba2
791 );
792 if (EFI_ERROR (Status)) {
793 return Status;
794 }
795
796 Lba32 += SectorCount;
797 Buffer = ((UINT8 *) Buffer + ByteCount);
798 BlocksRemaining -= SectorCount;
799 }
800
801 return Status;
802 }
803
804 /**
805 This function is called by the AtaBlkIoWriteBlocks() to perform
806 writing onto media in block unit.
807
808 @param[in] *IdeDev
809 pointer pointing to IDE_BLK_IO_DEV data structure,used
810 to record all the information of the IDE device.
811
812 @param[in] *BufferData
813 A pointer to the source buffer for the data.
814
815 @param[in] Lba
816 The starting logical block address to write onto
817 the device media.
818
819 @param[in] NumberOfBlocks
820 The number of transfer data blocks.
821
822 @return return status is fully dependent on the return status
823 of AtaPioDataOut() function.
824
825 **/
826 EFI_STATUS
827 AtaWriteSectors (
828 IN IDE_BLK_IO_DEV *IdeDev,
829 IN VOID *BufferData,
830 IN EFI_LBA Lba,
831 IN UINTN NumberOfBlocks
832 )
833 {
834 EFI_STATUS Status;
835 UINTN BlocksRemaining;
836 UINT32 Lba32;
837 UINT8 Lba0;
838 UINT8 Lba1;
839 UINT8 Lba2;
840 UINT8 Lba3;
841 UINT8 AtaCommand;
842 UINT8 SectorCount8;
843 UINT16 SectorCount;
844 UINTN ByteCount;
845 VOID *Buffer;
846
847 Buffer = BufferData;
848
849 //
850 // Using Write Sector(s) command (opcode=0x30) with PIO DATA OUT protocol
851 //
852 AtaCommand = WRITE_SECTORS_CMD;
853
854 BlocksRemaining = NumberOfBlocks;
855
856 Lba32 = (UINT32) Lba;
857
858 Status = EFI_SUCCESS;
859
860 while (BlocksRemaining > 0) {
861
862 Lba0 = (UINT8) Lba32;
863 Lba1 = (UINT8) (Lba32 >> 8);
864 Lba2 = (UINT8) (Lba32 >> 16);
865 Lba3 = (UINT8) ((Lba32 >> 24) & 0x0f);
866
867 if (BlocksRemaining >= 0x100) {
868
869 //
870 // SectorCount8 is sent to Sector Count register, 0x00 means 256 sectors
871 // to be written
872 //
873 SectorCount8 = 0x00;
874 //
875 // SectorCount is used to record the number of sectors to be written
876 //
877 SectorCount = 256;
878 } else {
879
880 SectorCount8 = (UINT8) BlocksRemaining;
881 SectorCount = (UINT16) BlocksRemaining;
882 }
883
884 ByteCount = SectorCount * (IdeDev->BlkIo.Media->BlockSize);
885
886 Status = AtaPioDataOut (
887 IdeDev,
888 Buffer,
889 (UINT32) ByteCount,
890 AtaCommand,
891 Lba3,
892 SectorCount8,
893 Lba0,
894 Lba1,
895 Lba2
896 );
897 if (EFI_ERROR (Status)) {
898 return Status;
899 }
900
901 Lba32 += SectorCount;
902 Buffer = ((UINT8 *) Buffer + ByteCount);
903 BlocksRemaining -= SectorCount;
904 }
905
906 return Status;
907 }
908
909 /**
910 This function is used to implement the Soft Reset on the specified
911 device. But, the ATA Soft Reset mechanism is so strong a reset method
912 that it will force resetting on both devices connected to the
913 same cable.
914
915 It is called by IdeBlkIoReset(), a interface function of Block
916 I/O protocol.
917
918 This function can also be used by the ATAPI device to perform reset when
919 ATAPI Reset command is failed.
920
921 @param[in] *IdeDev
922 pointer pointing to IDE_BLK_IO_DEV data structure, used
923 to record all the information of the IDE device.
924
925 @retval EFI_SUCCESS Soft reset completes successfully.
926 @retval EFI_DEVICE_ERROR Any step during the reset process is failed.
927
928 @note
929 The registers initial values after ATA soft reset are different
930 to the ATA device and ATAPI device.
931
932 **/
933 EFI_STATUS
934 AtaSoftReset (
935 IN IDE_BLK_IO_DEV *IdeDev
936 )
937 {
938
939 UINT8 DeviceControl;
940
941 DeviceControl = 0;
942 //
943 // set SRST bit to initiate soft reset
944 //
945 DeviceControl |= SRST;
946
947 //
948 // disable Interrupt
949 //
950 DeviceControl |= bit1;
951
952 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
953
954 //
955 // SRST should assert for at least 5 us, we use 10 us for
956 // better compatibility
957 //
958 gBS->Stall (10);
959
960 //
961 // Enable interrupt to support UDMA, and clear SRST bit
962 //
963 DeviceControl = 0;
964 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
965
966 //
967 // Wait for at least 2 ms to check BSY status, we use 10 ms
968 // for better compatibility
969 //
970 gBS->Stall(10000);
971 //
972 // slave device needs at most 31s to clear BSY
973 //
974 if (WaitForBSYClear (IdeDev, 31000) == EFI_TIMEOUT) {
975 return EFI_DEVICE_ERROR;
976 }
977
978 return EFI_SUCCESS;
979 }
980
981 /**
982 This function is the ATA implementation for ReadBlocks in the
983 Block I/O Protocol interface.
984
985 @param[in] *IdeBlkIoDevice
986 Indicates the calling context.
987
988 @param[in] MediaId
989 The media id that the read request is for.
990
991 @param[in] LBA
992 The starting logical block address to read from
993 on the device.
994
995 @param[in] BufferSize
996 The size of the Buffer in bytes. This must be a
997 multiple of the intrinsic block size of the device.
998
999 @param[out] *Buffer
1000 A pointer to the destination buffer for the data.
1001 The caller is responsible for either having implicit
1002 or explicit ownership of the memory that data is read into.
1003
1004 @retval EFI_SUCCESS Read Blocks successfully.
1005 @retval EFI_DEVICE_ERROR Read Blocks failed.
1006 @retval EFI_NO_MEDIA There is no media in the device.
1007 @retval EFI_MEDIA_CHANGE The MediaId is not for the current media.
1008
1009 @retval EFI_BAD_BUFFER_SIZE
1010 The BufferSize parameter is not a multiple of the
1011 intrinsic block size of the device.
1012
1013 @retval EFI_INVALID_PARAMETER
1014 The read request contains LBAs that are not valid,
1015 or the data buffer is not valid.
1016
1017 @note
1018 If Read Block error because of device error, this function will call
1019 AtaSoftReset() function to reset device.
1020
1021 **/
1022 EFI_STATUS
1023 AtaBlkIoReadBlocks (
1024 IN IDE_BLK_IO_DEV *IdeBlkIoDevice,
1025 IN UINT32 MediaId,
1026 IN EFI_LBA LBA,
1027 IN UINTN BufferSize,
1028 OUT VOID *Buffer
1029 )
1030 {
1031 EFI_BLOCK_IO_MEDIA *Media;
1032 UINTN BlockSize;
1033 UINTN NumberOfBlocks;
1034 EFI_STATUS Status;
1035
1036 if (Buffer == NULL) {
1037 return EFI_INVALID_PARAMETER;
1038 }
1039
1040 if (BufferSize == 0) {
1041 return EFI_SUCCESS;
1042 }
1043
1044 Status = EFI_SUCCESS;
1045
1046 //
1047 // Get the intrinsic block size
1048 //
1049 Media = IdeBlkIoDevice->BlkIo.Media;
1050 BlockSize = Media->BlockSize;
1051
1052 NumberOfBlocks = BufferSize / BlockSize;
1053
1054 if (MediaId != Media->MediaId) {
1055 return EFI_MEDIA_CHANGED;
1056 }
1057
1058 if (BufferSize % BlockSize != 0) {
1059 return EFI_BAD_BUFFER_SIZE;
1060 }
1061
1062 if (!(Media->MediaPresent)) {
1063 return EFI_NO_MEDIA;
1064 }
1065
1066 if (LBA > Media->LastBlock) {
1067 return EFI_INVALID_PARAMETER;
1068 }
1069
1070 if ((LBA + NumberOfBlocks - 1) > Media->LastBlock) {
1071 return EFI_INVALID_PARAMETER;
1072 }
1073
1074 if ((Media->IoAlign > 1) && (((UINTN) Buffer & (Media->IoAlign - 1)) != 0)) {
1075 return EFI_INVALID_PARAMETER;
1076 }
1077
1078 if (IdeBlkIoDevice->Type == Ide48bitAddressingHardDisk) {
1079 //
1080 // For ATA/ATAPI-6 device(capcity > 120GB), use ATA-6 read block mechanism
1081 //
1082 Status = AtaUdmaReadExt (IdeBlkIoDevice, Buffer, LBA, NumberOfBlocks);
1083 if (EFI_ERROR (Status)) {
1084 Status = AtaReadSectorsExt (IdeBlkIoDevice, Buffer, LBA, NumberOfBlocks);
1085 }
1086 } else {
1087 //
1088 // For ATA-3 compatible device, use ATA-3 read block mechanism
1089 //
1090 Status = AtaUdmaRead (IdeBlkIoDevice, Buffer, LBA, NumberOfBlocks);
1091 if (EFI_ERROR (Status)) {
1092 Status = AtaReadSectors (IdeBlkIoDevice, Buffer, LBA, NumberOfBlocks);
1093 }
1094 }
1095
1096 if (EFI_ERROR (Status)) {
1097 AtaSoftReset (IdeBlkIoDevice);
1098 return EFI_DEVICE_ERROR;
1099 }
1100
1101 return EFI_SUCCESS;
1102
1103 }
1104
1105 /**
1106 This function is the ATA implementation for WriteBlocks in the
1107 Block I/O Protocol interface.
1108
1109 @param[in] *IdeBlkIoDevice
1110 Indicates the calling context.
1111
1112 @param[in] MediaId
1113 The media id that the write request is for.
1114
1115 @param[in] LBA
1116 The starting logical block address to write onto
1117 the device.
1118
1119 @param[in] BufferSize
1120 The size of the Buffer in bytes. This must be a
1121 multiple of the intrinsic block size of the device.
1122
1123 @param[out] *Buffer
1124 A pointer to the source buffer for the data.
1125 The caller is responsible for either having implicit
1126 or explicit ownership of the memory that data is
1127 written from.
1128
1129 @retval EFI_SUCCESS Write Blocks successfully.
1130 @retval EFI_DEVICE_ERROR Write Blocks failed.
1131 @retval EFI_NO_MEDIA There is no media in the device.
1132 @retval EFI_MEDIA_CHANGE The MediaId is not for the current media.
1133
1134 @retval EFI_BAD_BUFFER_SIZE
1135 The BufferSize parameter is not a multiple of the
1136 intrinsic block size of the device.
1137
1138 @retval EFI_INVALID_PARAMETER
1139 The write request contains LBAs that are not valid,
1140 or the data buffer is not valid.
1141
1142 @note
1143 If Write Block error because of device error, this function will call
1144 AtaSoftReset() function to reset device.
1145
1146 **/
1147 EFI_STATUS
1148 AtaBlkIoWriteBlocks (
1149 IN IDE_BLK_IO_DEV *IdeBlkIoDevice,
1150 IN UINT32 MediaId,
1151 IN EFI_LBA LBA,
1152 IN UINTN BufferSize,
1153 OUT VOID *Buffer
1154 )
1155 {
1156
1157 EFI_BLOCK_IO_MEDIA *Media;
1158 UINTN BlockSize;
1159 UINTN NumberOfBlocks;
1160 EFI_STATUS Status;
1161
1162 if (Buffer == NULL) {
1163 return EFI_INVALID_PARAMETER;
1164 }
1165
1166 if (BufferSize == 0) {
1167 return EFI_SUCCESS;
1168 }
1169
1170 Status = EFI_SUCCESS;
1171
1172 //
1173 // Get the intrinsic block size
1174 //
1175 Media = IdeBlkIoDevice->BlkIo.Media;
1176 BlockSize = Media->BlockSize;
1177 NumberOfBlocks = BufferSize / BlockSize;
1178
1179 if (MediaId != Media->MediaId) {
1180 return EFI_MEDIA_CHANGED;
1181 }
1182
1183 if (BufferSize % BlockSize != 0) {
1184 return EFI_BAD_BUFFER_SIZE;
1185 }
1186
1187 if (LBA > Media->LastBlock) {
1188 return EFI_INVALID_PARAMETER;
1189 }
1190
1191 if ((LBA + NumberOfBlocks - 1) > Media->LastBlock) {
1192 return EFI_INVALID_PARAMETER;
1193 }
1194
1195 if ((Media->IoAlign > 1) && (((UINTN) Buffer & (Media->IoAlign - 1)) != 0)) {
1196 return EFI_INVALID_PARAMETER;
1197 }
1198
1199 if (IdeBlkIoDevice->Type == Ide48bitAddressingHardDisk) {
1200 //
1201 // For ATA/ATAPI-6 device(capcity > 120GB), use ATA-6 write block mechanism
1202 //
1203 Status = AtaUdmaWriteExt (IdeBlkIoDevice, Buffer, LBA, NumberOfBlocks);
1204 if (EFI_ERROR (Status)) {
1205 Status = AtaWriteSectorsExt (IdeBlkIoDevice, Buffer, LBA, NumberOfBlocks);
1206 }
1207 } else {
1208 //
1209 // For ATA-3 compatible device, use ATA-3 write block mechanism
1210 //
1211 Status = AtaUdmaWrite (IdeBlkIoDevice, Buffer, LBA, NumberOfBlocks);
1212 if (EFI_ERROR (Status)) {
1213 Status = AtaWriteSectors (IdeBlkIoDevice, Buffer, LBA, NumberOfBlocks);
1214 }
1215 }
1216
1217 if (EFI_ERROR (Status)) {
1218 AtaSoftReset (IdeBlkIoDevice);
1219 return EFI_DEVICE_ERROR;
1220 }
1221
1222 return EFI_SUCCESS;
1223 }
1224
1225 /**
1226 This function is called by the AtaBlkIoReadBlocks() to perform
1227 reading from media in block unit. The function has been enhanced to
1228 support >120GB access and transfer at most 65536 blocks per command
1229
1230 @param[in] *IdeDev
1231 pointer pointing to IDE_BLK_IO_DEV data structure, used
1232 to record all the information of the IDE device.
1233
1234 @param[in] *DataBuffer A pointer to the destination buffer for the data.
1235 @param[in] StartLba The starting logical block address to read from
1236 on the device media.
1237 @param[in] NumberOfBlocks The number of transfer data blocks.
1238
1239 @return return status is fully dependent on the return status
1240 of AtaPioDataInExt() function.
1241
1242 **/
1243 EFI_STATUS
1244 AtaReadSectorsExt (
1245 IN IDE_BLK_IO_DEV *IdeDev,
1246 IN VOID *DataBuffer,
1247 IN EFI_LBA StartLba,
1248 IN UINTN NumberOfBlocks
1249 )
1250 {
1251 EFI_STATUS Status;
1252 UINTN BlocksRemaining;
1253 EFI_LBA Lba64;
1254 UINT8 AtaCommand;
1255 UINT16 SectorCount;
1256 UINT32 ByteCount;
1257 VOID *Buffer;
1258
1259 //
1260 // Using ATA "Read Sectors Ext" command(opcode=0x24) with PIO DATA IN protocol
1261 //
1262 AtaCommand = READ_SECTORS_EXT_CMD;
1263 Buffer = DataBuffer;
1264 BlocksRemaining = NumberOfBlocks;
1265 Lba64 = StartLba;
1266 Status = EFI_SUCCESS;
1267
1268 while (BlocksRemaining > 0) {
1269
1270 if (BlocksRemaining >= 0x10000) {
1271 //
1272 // SectorCount is used to record the number of sectors to be read
1273 // Max 65536 sectors can be transfered at a time.
1274 //
1275 SectorCount = 0xffff;
1276 } else {
1277 SectorCount = (UINT16) BlocksRemaining;
1278 }
1279
1280 //
1281 // ByteCount is the number of bytes that will be read
1282 //
1283 ByteCount = SectorCount * (IdeDev->BlkIo.Media->BlockSize);
1284
1285 //
1286 // call AtaPioDataInExt() to send Read Sector Command and receive data read
1287 //
1288 Status = AtaPioDataInExt (
1289 IdeDev,
1290 Buffer,
1291 ByteCount,
1292 AtaCommand,
1293 Lba64,
1294 SectorCount
1295 );
1296 if (EFI_ERROR (Status)) {
1297 return Status;
1298 }
1299
1300 Lba64 += SectorCount;
1301 Buffer = ((UINT8 *) Buffer + ByteCount);
1302 BlocksRemaining -= SectorCount;
1303 }
1304
1305 return Status;
1306 }
1307
1308 /**
1309 This function is called by the AtaBlkIoWriteBlocks() to perform
1310 writing onto media in block unit. The function has been enhanced to
1311 support >120GB access and transfer at most 65536 blocks per command
1312
1313 @param[in] *IdeDev
1314 pointer pointing to IDE_BLK_IO_DEV data structure,used
1315 to record all the information of the IDE device.
1316
1317 @param[in] *DataBuffer
1318 A pointer to the source buffer for the data.
1319
1320 @param[in] Lba
1321 The starting logical block address to write onto
1322 the device media.
1323
1324 @param[in] NumberOfBlocks
1325 The number of transfer data blocks.
1326
1327 @return status is fully dependent on the return status
1328 of AtaPioDataOutExt() function.
1329
1330 **/
1331 EFI_STATUS
1332 AtaWriteSectorsExt (
1333 IN IDE_BLK_IO_DEV *IdeDev,
1334 IN VOID *DataBuffer,
1335 IN EFI_LBA StartLba,
1336 IN UINTN NumberOfBlocks
1337 )
1338 {
1339 EFI_STATUS Status;
1340 EFI_LBA Lba64;
1341 UINTN BlocksRemaining;
1342 UINT8 AtaCommand;
1343 UINT16 SectorCount;
1344 UINT32 ByteCount;
1345 VOID *Buffer;
1346
1347 //
1348 // Using ATA "Write Sectors Ext" cmd(opcode=0x24) with PIO DATA OUT protocol
1349 //
1350 AtaCommand = WRITE_SECTORS_EXT_CMD;
1351 Lba64 = StartLba;
1352 Buffer = DataBuffer;
1353 BlocksRemaining = NumberOfBlocks;
1354
1355 Status = EFI_SUCCESS;
1356
1357 while (BlocksRemaining > 0) {
1358
1359 if (BlocksRemaining >= 0x10000) {
1360 //
1361 // SectorCount is used to record the number of sectors to be written.
1362 // Max 65536 sectors can be transfered at a time.
1363 //
1364 SectorCount = 0xffff;
1365 } else {
1366 SectorCount = (UINT16) BlocksRemaining;
1367 }
1368
1369 //
1370 // ByteCount is the number of bytes that will be written
1371 //
1372 ByteCount = SectorCount * (IdeDev->BlkIo.Media->BlockSize);
1373
1374 //
1375 // Call AtaPioDataOutExt() to send "Write Sectors Ext" Command
1376 //
1377 Status = AtaPioDataOutExt (
1378 IdeDev,
1379 Buffer,
1380 ByteCount,
1381 AtaCommand,
1382 Lba64,
1383 SectorCount
1384 );
1385 if (EFI_ERROR (Status)) {
1386 return Status;
1387 }
1388
1389 Lba64 += SectorCount;
1390 Buffer = ((UINT8 *) Buffer + ByteCount);
1391 BlocksRemaining -= SectorCount;
1392 }
1393
1394 return Status;
1395 }
1396
1397 /**
1398 This function is used to send out ATA commands conforms to the
1399 PIO Data In Protocol, supporting ATA/ATAPI-6 standard
1400
1401 Comparing with ATA-3 data in protocol, we have two differents here:<BR>
1402 1. Do NOT wait for DRQ clear before sending command into IDE device.(the
1403 wait will frequently fail... cause writing function return error)
1404
1405 2. Do NOT wait for DRQ clear after all data readed.(the wait greatly
1406 slow down writing performance by 100 times!)
1407
1408 @param[in] *IdeDev pointer pointing to IDE_BLK_IO_DEV data structure, used
1409 to record all the information of the IDE device.
1410
1411 @param[in,out] *Buffer buffer contained data transferred from device to host.
1412 @param[in] ByteCount data size in byte unit of the buffer.
1413 @param[in] AtaCommand value of the Command Register
1414 @param[in] StartLba the start LBA of this transaction
1415 @param[in] SectorCount the count of sectors to be transfered
1416
1417 @retval EFI_SUCCESS send out the ATA command and device send required
1418 data successfully.
1419
1420 @retval EFI_DEVICE_ERROR command sent failed.
1421
1422 **/
1423 EFI_STATUS
1424 AtaPioDataInExt (
1425 IN IDE_BLK_IO_DEV *IdeDev,
1426 IN OUT VOID *Buffer,
1427 IN UINT32 ByteCount,
1428 IN UINT8 AtaCommand,
1429 IN EFI_LBA StartLba,
1430 IN UINT16 SectorCount
1431 )
1432 {
1433 UINT8 DevSel;
1434 UINT8 SectorCount8;
1435 UINT8 LbaLow;
1436 UINT8 LbaMid;
1437 UINT8 LbaHigh;
1438 UINTN WordCount;
1439 UINTN Increment;
1440 UINT16 *Buffer16;
1441 EFI_STATUS Status;
1442
1443 Status = WaitForBSYClear (IdeDev, ATATIMEOUT);
1444 if (EFI_ERROR (Status)) {
1445 return EFI_DEVICE_ERROR;
1446 }
1447
1448 //
1449 // Select device, set bit6 as 1 to indicate LBA mode is used
1450 //
1451 DevSel = (UINT8) (IdeDev->Device << 4);
1452 DevSel |= 0x40;
1453 IDEWritePortB (
1454 IdeDev->PciIo,
1455 IdeDev->IoPort->Head,
1456 DevSel
1457 );
1458
1459 //
1460 // Wait for DRDY singnal asserting. ATAPI device needn't wait
1461 //
1462 if ( (IdeDev->Type == IdeHardDisk) ||
1463 (IdeDev->Type == Ide48bitAddressingHardDisk)) {
1464
1465 Status = DRDYReady (IdeDev, ATATIMEOUT);
1466 if (EFI_ERROR (Status)) {
1467 return EFI_DEVICE_ERROR;
1468 }
1469 }
1470
1471 //
1472 // Fill feature register if needed
1473 //
1474 if (AtaCommand == SET_FEATURES_CMD) {
1475 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, 0x03);
1476 }
1477
1478 //
1479 // Fill the sector count register, which is a two-byte FIFO. Need write twice.
1480 //
1481 SectorCount8 = (UINT8) (SectorCount >> 8);
1482 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount8);
1483
1484 SectorCount8 = (UINT8) SectorCount;
1485 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount8);
1486
1487 //
1488 // Fill the start LBA registers, which are also two-byte FIFO
1489 //
1490 LbaLow = (UINT8) RShiftU64 (StartLba, 24);
1491 LbaMid = (UINT8) RShiftU64 (StartLba, 32);
1492 LbaHigh = (UINT8) RShiftU64 (StartLba, 40);
1493 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, LbaLow);
1494 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, LbaMid);
1495 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, LbaHigh);
1496
1497 LbaLow = (UINT8) StartLba;
1498 LbaMid = (UINT8) RShiftU64 (StartLba, 8);
1499 LbaHigh = (UINT8) RShiftU64 (StartLba, 16);
1500 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, LbaLow);
1501 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, LbaMid);
1502 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, LbaHigh);
1503
1504 //
1505 // Send command via Command Register, invoking the processing of this command
1506 //
1507 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, AtaCommand);
1508
1509 Buffer16 = (UINT16 *) Buffer;
1510
1511 //
1512 // According to PIO data in protocol, host can perform a series of reads to
1513 // the data register after each time device set DRQ ready;
1514 //
1515
1516 //
1517 // 256 words
1518 //
1519 Increment = 256;
1520
1521 //
1522 // used to record bytes of currently transfered data
1523 //
1524 WordCount = 0;
1525
1526 while (WordCount < ByteCount / 2) {
1527 //
1528 // Poll DRQ bit set, data transfer can be performed only when DRQ is ready.
1529 //
1530 Status = DRQReady2 (IdeDev, ATATIMEOUT);
1531 if (EFI_ERROR (Status)) {
1532 return EFI_DEVICE_ERROR;
1533 }
1534
1535 Status = CheckErrorStatus (IdeDev);
1536 if (EFI_ERROR (Status)) {
1537 return EFI_DEVICE_ERROR;
1538 }
1539
1540 //
1541 // Get the byte count for one series of read
1542 //
1543 if ((WordCount + Increment) > ByteCount / 2) {
1544 Increment = ByteCount / 2 - WordCount;
1545 }
1546
1547 IDEReadPortWMultiple (
1548 IdeDev->PciIo,
1549 IdeDev->IoPort->Data,
1550 Increment,
1551 Buffer16
1552 );
1553
1554 WordCount += Increment;
1555 Buffer16 += Increment;
1556
1557 }
1558
1559 return CheckErrorStatus (IdeDev);
1560 }
1561
1562 /**
1563 This function is used to send out ATA commands conforms to the
1564 PIO Data Out Protocol, supporting ATA/ATAPI-6 standard
1565
1566 Comparing with ATA-3 data out protocol, we have two differents here:<BR>
1567 1. Do NOT wait for DRQ clear before sending command into IDE device.(the
1568 wait will frequently fail... cause writing function return error)
1569
1570 2. Do NOT wait for DRQ clear after all data readed.(the wait greatly
1571 slow down writing performance by 100 times!)
1572
1573 @param[in] *IdeDev
1574 pointer pointing to IDE_BLK_IO_DEV data structure, used
1575 to record all the information of the IDE device.
1576
1577 @param[in] *Buffer buffer contained data transferred from host to device.
1578 @param[in] ByteCount data size in byte unit of the buffer.
1579 @param[in] AtaCommand value of the Command Register
1580 @param[in] StartLba the start LBA of this transaction
1581 @param[in] SectorCount the count of sectors to be transfered
1582
1583 @retval EFI_SUCCESS send out the ATA command and device receive required
1584 data successfully.
1585
1586 @retval EFI_DEVICE_ERROR command sent failed.
1587
1588 **/
1589 EFI_STATUS
1590 AtaPioDataOutExt (
1591 IN IDE_BLK_IO_DEV *IdeDev,
1592 IN VOID *Buffer,
1593 IN UINT32 ByteCount,
1594 IN UINT8 AtaCommand,
1595 IN EFI_LBA StartLba,
1596 IN UINT16 SectorCount
1597 )
1598 {
1599 UINT8 DevSel;
1600 UINT8 SectorCount8;
1601 UINT8 LbaLow;
1602 UINT8 LbaMid;
1603 UINT8 LbaHigh;
1604 UINTN WordCount;
1605 UINTN Increment;
1606 UINT16 *Buffer16;
1607 EFI_STATUS Status;
1608
1609 Status = WaitForBSYClear (IdeDev, ATATIMEOUT);
1610 if (EFI_ERROR (Status)) {
1611 return EFI_DEVICE_ERROR;
1612 }
1613
1614 //
1615 // Select device. Set bit6 as 1 to indicate LBA mode is used
1616 //
1617 DevSel = (UINT8) (IdeDev->Device << 4);
1618 DevSel |= 0x40;
1619 IDEWritePortB (
1620 IdeDev->PciIo,
1621 IdeDev->IoPort->Head,
1622 DevSel
1623 );
1624
1625 //
1626 // Wait for DRDY singnal asserting.
1627 //
1628 Status = DRDYReady (IdeDev, ATATIMEOUT);
1629 if (EFI_ERROR (Status)) {
1630 return EFI_DEVICE_ERROR;
1631 }
1632
1633 //
1634 // Fill feature register if needed
1635 //
1636 if (AtaCommand == SET_FEATURES_CMD) {
1637 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, 0x03);
1638 }
1639
1640 //
1641 // Fill the sector count register, which is a two-byte FIFO. Need write twice.
1642 //
1643 SectorCount8 = (UINT8) (SectorCount >> 8);
1644 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount8);
1645
1646 SectorCount8 = (UINT8) SectorCount;
1647 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount8);
1648
1649 //
1650 // Fill the start LBA registers, which are also two-byte FIFO
1651 //
1652 LbaLow = (UINT8) RShiftU64 (StartLba, 24);
1653 LbaMid = (UINT8) RShiftU64 (StartLba, 32);
1654 LbaHigh = (UINT8) RShiftU64 (StartLba, 40);
1655 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, LbaLow);
1656 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, LbaMid);
1657 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, LbaHigh);
1658
1659 LbaLow = (UINT8) StartLba;
1660 LbaMid = (UINT8) RShiftU64 (StartLba, 8);
1661 LbaHigh = (UINT8) RShiftU64 (StartLba, 16);
1662 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, LbaLow);
1663 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, LbaMid);
1664 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, LbaHigh);
1665
1666 //
1667 // Send command via Command Register, invoking the processing of this command
1668 //
1669 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, AtaCommand);
1670
1671 Buffer16 = (UINT16 *) Buffer;
1672
1673 //
1674 // According to PIO Data Out protocol, host can perform a series of writes to
1675 // the data register after each time device set DRQ ready;
1676 //
1677 Increment = 256;
1678
1679 //
1680 // used to record bytes of currently transfered data
1681 //
1682 WordCount = 0;
1683
1684 while (WordCount < ByteCount / 2) {
1685 //
1686 // Poll DRQ bit set, data transfer can be performed only when DRQ is ready.
1687 //
1688 Status = DRQReady2 (IdeDev, ATATIMEOUT);
1689 if (EFI_ERROR (Status)) {
1690 return EFI_DEVICE_ERROR;
1691 }
1692
1693 Status = CheckErrorStatus (IdeDev);
1694 if (EFI_ERROR (Status)) {
1695 return EFI_DEVICE_ERROR;
1696 }
1697
1698 //
1699 // Write data into device by one series of writing to data register
1700 //
1701 if ((WordCount + Increment) > ByteCount / 2) {
1702 Increment = ByteCount / 2 - WordCount;
1703 }
1704
1705 IDEWritePortWMultiple (
1706 IdeDev->PciIo,
1707 IdeDev->IoPort->Data,
1708 Increment,
1709 Buffer16
1710 );
1711
1712 WordCount += Increment;
1713 Buffer16 += Increment;
1714
1715 }
1716 //
1717 // while
1718 //
1719
1720 return CheckErrorStatus (IdeDev);
1721 }
1722
1723
1724 /**
1725 Enable SMART of the disk if supported
1726
1727 @param[in] *IdeDev
1728 pointer pointing to IDE_BLK_IO_DEV data structure,used
1729 to record all the information of the IDE device.
1730
1731 **/
1732 VOID
1733 AtaSMARTSupport (
1734 IN IDE_BLK_IO_DEV *IdeDev
1735 )
1736 {
1737 EFI_STATUS Status;
1738 BOOLEAN SMARTSupported;
1739 UINT8 Device;
1740 EFI_IDENTIFY_DATA *TmpAtaIdentifyPointer;
1741 UINT8 DeviceSelect;
1742 UINT8 LBAMid;
1743 UINT8 LBAHigh;
1744
1745 //
1746 // Detect if the device supports S.M.A.R.T.
1747 //
1748 if ((IdeDev->pIdData->AtaData.command_set_supported_83 & 0xc000) != 0x4000) {
1749 //
1750 // Data in word 82 is not valid (bit15 shall be zero and bit14 shall be to one)
1751 //
1752 return ;
1753 } else {
1754 if ((IdeDev->pIdData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
1755 //
1756 // S.M.A.R.T is not supported by the device
1757 //
1758 SMARTSupported = FALSE;
1759 } else {
1760 SMARTSupported = TRUE;
1761 }
1762 }
1763
1764 if (!SMARTSupported) {
1765 //
1766 // Report nonsupport status code
1767 //
1768 REPORT_STATUS_CODE (
1769 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1770 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)
1771 );
1772 } else {
1773 //
1774 // Enable this feature
1775 //
1776 REPORT_STATUS_CODE (
1777 EFI_PROGRESS_CODE,
1778 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)
1779 );
1780
1781 Device = (UINT8) ((IdeDev->Device << 4) | 0xe0);
1782 Status = AtaNonDataCommandIn (
1783 IdeDev,
1784 ATA_SMART_CMD,
1785 Device,
1786 ATA_SMART_ENABLE_OPERATION,
1787 0,
1788 0,
1789 ATA_CONSTANT_4F,
1790 ATA_CONSTANT_C2
1791 );
1792 //
1793 // Detect if this feature is enabled
1794 //
1795 TmpAtaIdentifyPointer = (EFI_IDENTIFY_DATA *) AllocateZeroPool (sizeof (EFI_IDENTIFY_DATA));
1796
1797 DeviceSelect = (UINT8) ((IdeDev->Device) << 4);
1798 Status = AtaPioDataIn (
1799 IdeDev,
1800 (VOID *) TmpAtaIdentifyPointer,
1801 sizeof (EFI_IDENTIFY_DATA),
1802 IDENTIFY_DRIVE_CMD,
1803 DeviceSelect,
1804 0,
1805 0,
1806 0,
1807 0
1808 );
1809 if (EFI_ERROR (Status)) {
1810 gBS->FreePool (TmpAtaIdentifyPointer);
1811 return ;
1812 }
1813
1814 //
1815 // Check if the feature is enabled
1816 //
1817 if ((TmpAtaIdentifyPointer->AtaData.command_set_feature_enb_85 & 0x0001) == 0x0001) {
1818 //
1819 // Read status data
1820 //
1821 AtaNonDataCommandIn (
1822 IdeDev,
1823 ATA_SMART_CMD,
1824 Device,
1825 ATA_SMART_RETURN_STATUS,
1826 0,
1827 0,
1828 ATA_CONSTANT_4F,
1829 ATA_CONSTANT_C2
1830 );
1831 LBAMid = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb);
1832 LBAHigh = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb);
1833
1834 if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
1835 //
1836 // The threshold exceeded condition is not detected by the device
1837 //
1838 REPORT_STATUS_CODE (
1839 EFI_PROGRESS_CODE,
1840 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
1841 );
1842
1843 } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
1844 //
1845 // The threshold exceeded condition is detected by the device
1846 //
1847 REPORT_STATUS_CODE (
1848 EFI_PROGRESS_CODE,
1849 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
1850 );
1851 }
1852
1853 } else {
1854 //
1855 // Report disabled status code
1856 //
1857 REPORT_STATUS_CODE (
1858 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1859 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)
1860 );
1861 }
1862
1863 gBS->FreePool (TmpAtaIdentifyPointer);
1864 }
1865
1866 return ;
1867 }
1868
1869 /**
1870 Send ATA Ext command into device with NON_DATA protocol
1871
1872 @param IdeDev Standard IDE device private data structure
1873 @param AtaCommand The ATA command to be sent
1874 @param Device The value in Device register
1875 @param Feature The value in Feature register
1876 @param SectorCount The value in SectorCount register
1877 @param LbaAddress The LBA address in 48-bit mode
1878
1879 @retval EFI_SUCCESS Reading succeed
1880 @retval EFI_DEVICE_ERROR Error executing commands on this device
1881
1882 **/
1883 EFI_STATUS
1884 AtaCommandIssueExt (
1885 IN IDE_BLK_IO_DEV *IdeDev,
1886 IN UINT8 AtaCommand,
1887 IN UINT8 Device,
1888 IN UINT16 Feature,
1889 IN UINT16 SectorCount,
1890 IN EFI_LBA LbaAddress
1891 )
1892 {
1893 EFI_STATUS Status;
1894 UINT8 SectorCount8;
1895 UINT8 Feature8;
1896 UINT8 LbaLow;
1897 UINT8 LbaMid;
1898 UINT8 LbaHigh;
1899
1900 Status = WaitForBSYClear (IdeDev, ATATIMEOUT);
1901 if (EFI_ERROR (Status)) {
1902 return EFI_DEVICE_ERROR;
1903 }
1904
1905 //
1906 // Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)
1907 //
1908 IDEWritePortB (
1909 IdeDev->PciIo,
1910 IdeDev->IoPort->Head,
1911 (UINT8) ((IdeDev->Device << 4) | 0xe0)
1912 );
1913
1914 //
1915 // ATA commands for ATA device must be issued when DRDY is set
1916 //
1917 Status = DRDYReady (IdeDev, ATATIMEOUT);
1918 if (EFI_ERROR (Status)) {
1919 return EFI_DEVICE_ERROR;
1920 }
1921
1922 //
1923 // Pass parameter into device register block
1924 //
1925 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Head, Device);
1926
1927 //
1928 // Fill the feature register, which is a two-byte FIFO. Need write twice.
1929 //
1930 Feature8 = (UINT8) (Feature >> 8);
1931 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, Feature8);
1932
1933 Feature8 = (UINT8) Feature;
1934 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, Feature8);
1935
1936 //
1937 // Fill the sector count register, which is a two-byte FIFO. Need write twice.
1938 //
1939 SectorCount8 = (UINT8) (SectorCount >> 8);
1940 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount8);
1941
1942 SectorCount8 = (UINT8) SectorCount;
1943 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount8);
1944
1945 //
1946 // Fill the start LBA registers, which are also two-byte FIFO
1947 //
1948 LbaLow = (UINT8) RShiftU64 (LbaAddress, 24);
1949 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, LbaLow);
1950 LbaLow = (UINT8) LbaAddress;
1951 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, LbaLow);
1952
1953 LbaMid = (UINT8) RShiftU64 (LbaAddress, 32);
1954 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, LbaMid);
1955 LbaMid = (UINT8) RShiftU64 (LbaAddress, 8);
1956 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, LbaMid);
1957
1958 LbaHigh = (UINT8) RShiftU64 (LbaAddress, 40);
1959 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, LbaHigh);
1960 LbaHigh = (UINT8) RShiftU64 (LbaAddress, 16);
1961 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, LbaHigh);
1962
1963 //
1964 // Work around for Segate 160G disk writing
1965 //
1966 gBS->Stall (1800);
1967
1968 //
1969 // Send command via Command Register
1970 //
1971 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, AtaCommand);
1972
1973 //
1974 // Stall at least 400ns
1975 //
1976 gBS->Stall (100);
1977
1978 return EFI_SUCCESS;
1979 }
1980
1981 /**
1982 Send ATA Ext command into device with NON_DATA protocol
1983
1984 @param IdeDev Standard IDE device private data structure
1985 @param AtaCommand The ATA command to be sent
1986 @param Device The value in Device register
1987 @param Feature The value in Feature register
1988 @param SectorCount The value in SectorCount register
1989 @param LbaAddress The LBA address in 48-bit mode
1990
1991 @retval EFI_SUCCESS Reading succeed
1992 @retval EFI_DEVICE_ERROR Error executing commands on this device
1993
1994 **/
1995 EFI_STATUS
1996 AtaCommandIssue (
1997 IN IDE_BLK_IO_DEV *IdeDev,
1998 IN UINT8 AtaCommand,
1999 IN UINT8 Device,
2000 IN UINT16 Feature,
2001 IN UINT16 SectorCount,
2002 IN EFI_LBA LbaAddress
2003 )
2004 {
2005 EFI_STATUS Status;
2006 UINT8 SectorCount8;
2007 UINT8 Feature8;
2008 UINT8 Lba0;
2009 UINT8 Lba1;
2010 UINT8 Lba2;
2011 UINT8 Lba3;
2012
2013 Status = WaitForBSYClear (IdeDev, ATATIMEOUT);
2014 if (EFI_ERROR (Status)) {
2015 return EFI_DEVICE_ERROR;
2016 }
2017
2018 //
2019 // Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)
2020 //
2021 IDEWritePortB (
2022 IdeDev->PciIo,
2023 IdeDev->IoPort->Head,
2024 (UINT8) ((IdeDev->Device << 4) | 0xe0)
2025 );
2026
2027 //
2028 // ATA commands for ATA device must be issued when DRDY is set
2029 //
2030 Status = DRDYReady (IdeDev, ATATIMEOUT);
2031 if (EFI_ERROR (Status)) {
2032 return EFI_DEVICE_ERROR;
2033 }
2034
2035 Lba0 = (UINT8) LbaAddress;
2036 Lba1 = (UINT8) RShiftU64 (LbaAddress, 8);
2037 Lba2 = (UINT8) RShiftU64 (LbaAddress, 16);
2038 Lba3 = (UINT8) RShiftU64 (LbaAddress, 24);
2039 Device = (UINT8) (Device | Lba3);
2040
2041 //
2042 // Pass parameter into device register block
2043 //
2044 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Head, Device);
2045
2046 //
2047 // Fill the feature register, which is a two-byte FIFO. Need write twice.
2048 //
2049 Feature8 = (UINT8) Feature;
2050 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, Feature8);
2051
2052 //
2053 // Fill the sector count register, which is a two-byte FIFO. Need write twice.
2054 //
2055 SectorCount8 = (UINT8) SectorCount;
2056 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorCount, SectorCount8);
2057
2058 //
2059 // Fill the start LBA registers, which are also two-byte FIFO
2060 //
2061
2062 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->SectorNumber, Lba0);
2063 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderLsb, Lba1);
2064 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->CylinderMsb, Lba2);
2065
2066 //
2067 // Send command via Command Register
2068 //
2069 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, AtaCommand);
2070
2071 //
2072 // Stall at least 400ns
2073 //
2074 gBS->Stall (100);
2075
2076 return EFI_SUCCESS;
2077 }
2078
2079 /**
2080 This function is called by the AtaBlkIoReadBlocks() to perform
2081 reading from media in block unit. The function has been enhanced to
2082 support >120GB access and transfer at most 65536 blocks per command
2083
2084 @param[in] *IdeDev pointer pointing to IDE_BLK_IO_DEV data structure, used
2085 to record all the information of the IDE device.
2086
2087 @param[in] *DataBuffer A pointer to the destination buffer for the data.
2088
2089 @param[in] StartLba The starting logical block address to read from
2090 on the device media.
2091
2092 @param[in] NumberOfBlocks The number of transfer data blocks.
2093
2094 @return The device status of UDMA operation. If the operation is
2095 successful, return EFI_SUCCESS.
2096
2097 TODO: EFI_UNSUPPORTED - add return value to function comment
2098 TODO: EFI_DEVICE_ERROR - add return value to function comment
2099 TODO: EFI_DEVICE_ERROR - add return value to function comment
2100 TODO: EFI_DEVICE_ERROR - add return value to function comment
2101 **/
2102 EFI_STATUS
2103 AtaUdmaReadExt (
2104 IN IDE_BLK_IO_DEV *IdeDev,
2105 IN VOID *DataBuffer,
2106 IN EFI_LBA StartLba,
2107 IN UINTN NumberOfBlocks
2108 )
2109 {
2110 IDE_DMA_PRD *PrdAddr;
2111 IDE_DMA_PRD *UsedPrdAddr;
2112 IDE_DMA_PRD *TempPrdAddr;
2113 UINT8 RegisterValue;
2114 UINT8 Device;
2115 UINT64 IoPortForBmic;
2116 UINT64 IoPortForBmis;
2117 UINT64 IoPortForBmid;
2118 EFI_STATUS Status;
2119 UINTN PrdTableNum;
2120 UINTN ByteCount;
2121 UINTN ByteAvailable;
2122 UINT8 *PrdBuffer;
2123 UINTN RemainBlockNum;
2124 UINT8 DeviceControl;
2125 UINT32 Count;
2126 UINTN PageCount;
2127 VOID *Map;
2128 VOID *MemPage;
2129 EFI_PHYSICAL_ADDRESS DeviceAddress;
2130
2131 //
2132 // Channel and device differential. Select device.
2133 //
2134 Device = (UINT8) ((IdeDev->Device << 4) | 0xe0);
2135
2136 //
2137 // Enable interrupt to support UDMA and Select device
2138 //
2139 DeviceControl = 0;
2140 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
2141
2142 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Head, Device);
2143
2144 if (IdePrimary == IdeDev->Channel) {
2145 IoPortForBmic = IdeDev->IoPort->BusMasterBaseAddr + BMICP_OFFSET;
2146 IoPortForBmis = IdeDev->IoPort->BusMasterBaseAddr + BMISP_OFFSET;
2147 IoPortForBmid = IdeDev->IoPort->BusMasterBaseAddr + BMIDP_OFFSET;
2148 } else {
2149 if (IdeSecondary == IdeDev->Channel) {
2150 IoPortForBmic = IdeDev->IoPort->BusMasterBaseAddr + BMICS_OFFSET;
2151 IoPortForBmis = IdeDev->IoPort->BusMasterBaseAddr + BMISS_OFFSET;
2152 IoPortForBmid = IdeDev->IoPort->BusMasterBaseAddr + BMIDS_OFFSET;
2153 } else {
2154 return EFI_UNSUPPORTED;
2155 }
2156 }
2157
2158 RemainBlockNum = NumberOfBlocks;
2159 while (RemainBlockNum > 0) {
2160
2161 if (RemainBlockNum >= MAX_DMA_EXT_COMMAND_SECTORS) {
2162 //
2163 // SectorCount is used to record the number of sectors to be read
2164 // Max 65536 sectors can be transfered at a time.
2165 //
2166 NumberOfBlocks = MAX_DMA_EXT_COMMAND_SECTORS;
2167 RemainBlockNum -= MAX_DMA_EXT_COMMAND_SECTORS;
2168 } else {
2169 NumberOfBlocks = (UINT16) RemainBlockNum;
2170 RemainBlockNum = 0;
2171 }
2172
2173 //
2174 // Calculate the number of PRD table to make sure the memory region
2175 // not cross 64K boundary
2176 //
2177 ByteCount = NumberOfBlocks * IdeDev->BlkIo.Media->BlockSize;
2178 PrdTableNum = ((ByteCount >> 16) + 1) + 1;
2179
2180 //
2181 // Build PRD table
2182 //
2183 PageCount = EFI_SIZE_TO_PAGES (2 * PrdTableNum * sizeof (IDE_DMA_PRD));
2184 Status = IdeDev->PciIo->AllocateBuffer (
2185 IdeDev->PciIo,
2186 AllocateAnyPages,
2187 EfiBootServicesData,
2188 PageCount,
2189 &MemPage,
2190 0
2191 );
2192 if (EFI_ERROR (Status)) {
2193 return EFI_OUT_OF_RESOURCES;
2194 }
2195 ZeroMem ((VOID *) ((UINTN) MemPage), EFI_PAGES_TO_SIZE (PageCount));
2196
2197 PrdAddr = (IDE_DMA_PRD *) ((UINTN) MemPage);
2198
2199 //
2200 // To make sure PRD is allocated in one 64K page
2201 //
2202 if (((UINTN) PrdAddr & 0x0FFFF) > (((UINTN) PrdAddr + PrdTableNum * sizeof (IDE_DMA_PRD) - 1) & 0x0FFFF)) {
2203 UsedPrdAddr = (IDE_DMA_PRD *) ((UINTN) ((UINT8 *) PrdAddr + 0x10000) & 0xFFFF0000);
2204 } else {
2205 if ((UINTN) PrdAddr & 0x03) {
2206 UsedPrdAddr = (IDE_DMA_PRD *) ((UINTN) ((UINT8 *) PrdAddr + 0x04) & 0xFFFFFFFC);
2207 } else {
2208 UsedPrdAddr = PrdAddr;
2209 }
2210 }
2211
2212 //
2213 // Build the PRD table
2214 //
2215 Status = IdeDev->PciIo->Map (
2216 IdeDev->PciIo,
2217 EfiPciIoOperationBusMasterWrite,
2218 DataBuffer,
2219 &ByteCount,
2220 &DeviceAddress,
2221 &Map
2222 );
2223 if (EFI_ERROR (Status)) {
2224 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
2225 return EFI_OUT_OF_RESOURCES;
2226 }
2227 PrdBuffer = (VOID *) ((UINTN) DeviceAddress);
2228 TempPrdAddr = UsedPrdAddr;
2229 while (TRUE) {
2230
2231 ByteAvailable = 0x10000 - ((UINTN) PrdBuffer & 0xFFFF);
2232
2233 if (ByteCount <= ByteAvailable) {
2234 TempPrdAddr->RegionBaseAddr = (UINT32) ((UINTN) PrdBuffer);
2235 TempPrdAddr->ByteCount = (UINT16) ByteCount;
2236 TempPrdAddr->EndOfTable = 0x8000;
2237 break;
2238 }
2239
2240 TempPrdAddr->RegionBaseAddr = (UINT32) ((UINTN) PrdBuffer);
2241 TempPrdAddr->ByteCount = (UINT16) ByteAvailable;
2242
2243 ByteCount -= ByteAvailable;
2244 PrdBuffer += ByteAvailable;
2245 TempPrdAddr++;
2246 }
2247
2248 //
2249 // Set the base address to BMID register
2250 //
2251 IdeDev->PciIo->Io.Write (
2252 IdeDev->PciIo,
2253 EfiPciIoWidthUint32,
2254 EFI_PCI_IO_PASS_THROUGH_BAR,
2255 IoPortForBmid,
2256 1,
2257 &UsedPrdAddr
2258 );
2259
2260 //
2261 // Set BMIC register to identify the operation direction
2262 //
2263 IdeDev->PciIo->Io.Read (
2264 IdeDev->PciIo,
2265 EfiPciIoWidthUint8,
2266 EFI_PCI_IO_PASS_THROUGH_BAR,
2267 IoPortForBmic,
2268 1,
2269 &RegisterValue
2270 );
2271
2272 RegisterValue |= BMIC_nREAD;
2273
2274 IdeDev->PciIo->Io.Write (
2275 IdeDev->PciIo,
2276 EfiPciIoWidthUint8,
2277 EFI_PCI_IO_PASS_THROUGH_BAR,
2278 IoPortForBmic,
2279 1,
2280 &RegisterValue
2281 );
2282
2283 //
2284 // Read BMIS register and clear ERROR and INTR bit
2285 //
2286 IdeDev->PciIo->Io.Read (
2287 IdeDev->PciIo,
2288 EfiPciIoWidthUint8,
2289 EFI_PCI_IO_PASS_THROUGH_BAR,
2290 IoPortForBmis,
2291 1,
2292 &RegisterValue
2293 );
2294
2295 RegisterValue |= BMIS_INTERRUPT | BMIS_ERROR;
2296
2297 IdeDev->PciIo->Io.Write (
2298 IdeDev->PciIo,
2299 EfiPciIoWidthUint8,
2300 EFI_PCI_IO_PASS_THROUGH_BAR,
2301 IoPortForBmis,
2302 1,
2303 &RegisterValue
2304 );
2305
2306 //
2307 // Issue READ DMA EXT command
2308 //
2309 Status = AtaCommandIssueExt (
2310 IdeDev,
2311 READ_DMA_EXT_CMD,
2312 Device,
2313 0,
2314 (UINT16) NumberOfBlocks,
2315 StartLba
2316 );
2317 if (EFI_ERROR (Status)) {
2318 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
2319 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
2320 return EFI_DEVICE_ERROR;
2321 }
2322
2323 //
2324 // Set START bit of BMIC register
2325 //
2326 IdeDev->PciIo->Io.Read (
2327 IdeDev->PciIo,
2328 EfiPciIoWidthUint8,
2329 EFI_PCI_IO_PASS_THROUGH_BAR,
2330 IoPortForBmic,
2331 1,
2332 &RegisterValue
2333 );
2334
2335 RegisterValue |= BMIC_START;
2336
2337 IdeDev->PciIo->Io.Write (
2338 IdeDev->PciIo,
2339 EfiPciIoWidthUint8,
2340 EFI_PCI_IO_PASS_THROUGH_BAR,
2341 IoPortForBmic,
2342 1,
2343 &RegisterValue
2344 );
2345
2346 //
2347 // Check the INTERRUPT and ERROR bit of BMIS
2348 // Max transfer number of sectors for one command is 65536(32Mbyte),
2349 // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).
2350 // So set the variable Count to 2000, for about 2 second timeout time.
2351 //
2352 Count = 2000;
2353 while (TRUE) {
2354
2355 IdeDev->PciIo->Io.Read (
2356 IdeDev->PciIo,
2357 EfiPciIoWidthUint8,
2358 EFI_PCI_IO_PASS_THROUGH_BAR,
2359 IoPortForBmis,
2360 1,
2361 &RegisterValue
2362 );
2363 if ((RegisterValue & (BMIS_INTERRUPT | BMIS_ERROR)) || (Count == 0)) {
2364 if ((RegisterValue & BMIS_ERROR) || (Count == 0)) {
2365 //
2366 // Clear START bit of BMIC register before return EFI_DEVICE_ERROR
2367 //
2368 IdeDev->PciIo->Io.Read (
2369 IdeDev->PciIo,
2370 EfiPciIoWidthUint8,
2371 EFI_PCI_IO_PASS_THROUGH_BAR,
2372 IoPortForBmic,
2373 1,
2374 &RegisterValue
2375 );
2376
2377 RegisterValue &= ~((UINT8)BMIC_START);
2378
2379 IdeDev->PciIo->Io.Write (
2380 IdeDev->PciIo,
2381 EfiPciIoWidthUint8,
2382 EFI_PCI_IO_PASS_THROUGH_BAR,
2383 IoPortForBmic,
2384 1,
2385 &RegisterValue
2386 );
2387 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
2388 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
2389 return EFI_DEVICE_ERROR;
2390 }
2391 break;
2392 }
2393
2394 gBS->Stall (1000);
2395 Count --;
2396 }
2397
2398 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
2399 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
2400 //
2401 // Read Status Register of IDE device to clear interrupt
2402 //
2403 RegisterValue = IDEReadPortB(IdeDev->PciIo,IdeDev->IoPort->Reg.Status);
2404 //
2405 // Clear START bit of BMIC register
2406 //
2407 IdeDev->PciIo->Io.Read (
2408 IdeDev->PciIo,
2409 EfiPciIoWidthUint8,
2410 EFI_PCI_IO_PASS_THROUGH_BAR,
2411 IoPortForBmic,
2412 1,
2413 &RegisterValue
2414 );
2415
2416 RegisterValue &= ~((UINT8) BMIC_START);
2417
2418 IdeDev->PciIo->Io.Write (
2419 IdeDev->PciIo,
2420 EfiPciIoWidthUint8,
2421 EFI_PCI_IO_PASS_THROUGH_BAR,
2422 IoPortForBmic,
2423 1,
2424 &RegisterValue
2425 );
2426
2427 if (RegisterValue & BMIS_ERROR) {
2428 return EFI_DEVICE_ERROR;
2429 }
2430
2431 DataBuffer = (UINT8 *) DataBuffer + NumberOfBlocks * IdeDev->BlkIo.Media->BlockSize;
2432 StartLba += NumberOfBlocks;
2433 }
2434
2435 //
2436 // Disable interrupt of Select device
2437 //
2438 IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl);
2439 DeviceControl |= IEN_L;
2440 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
2441
2442 return EFI_SUCCESS;
2443 }
2444
2445 /**
2446 This function is called by the AtaBlkIoReadBlocks() to perform
2447 reading from media in block unit. The function has been enhanced to
2448 support >120GB access and transfer at most 65536 blocks per command
2449
2450 @param[in] *IdeDev
2451 pointer pointing to IDE_BLK_IO_DEV data structure, used
2452 to record all the information of the IDE device.
2453
2454 @param[in] *DataBuffer A pointer to the destination buffer for the data.
2455 @param[in] StartLba The starting logical block address to read from
2456 on the device media.
2457 @param[in] NumberOfBlocks The number of transfer data blocks.
2458
2459 @return The device status of UDMA operation. If the operation is
2460 successful, return EFI_SUCCESS.
2461
2462 TODO: EFI_UNSUPPORTED - add return value to function comment
2463 TODO: EFI_DEVICE_ERROR - add return value to function comment
2464 TODO: EFI_DEVICE_ERROR - add return value to function comment
2465 TODO: EFI_DEVICE_ERROR - add return value to function comment
2466 **/
2467 EFI_STATUS
2468 AtaUdmaRead (
2469 IN IDE_BLK_IO_DEV *IdeDev,
2470 IN VOID *DataBuffer,
2471 IN EFI_LBA StartLba,
2472 IN UINTN NumberOfBlocks
2473 )
2474 {
2475 IDE_DMA_PRD *PrdAddr;
2476 IDE_DMA_PRD *UsedPrdAddr;
2477 IDE_DMA_PRD *TempPrdAddr;
2478 UINT8 RegisterValue;
2479 UINT8 Device;
2480 UINT64 IoPortForBmic;
2481 UINT64 IoPortForBmis;
2482 UINT64 IoPortForBmid;
2483 EFI_STATUS Status;
2484 UINTN PrdTableNum;
2485 UINTN ByteCount;
2486 UINTN ByteAvailable;
2487 UINT8 *PrdBuffer;
2488 UINTN RemainBlockNum;
2489 UINT8 DeviceControl;
2490 UINT32 Count;
2491 UINTN PageCount;
2492 VOID *Map;
2493 VOID *MemPage;
2494 EFI_PHYSICAL_ADDRESS DeviceAddress;
2495
2496 //
2497 // Channel and device differential
2498 //
2499 Device = (UINT8) ((IdeDev->Device << 4) | 0xe0);
2500
2501 //
2502 // Enable interrupt to support UDMA and Select device
2503 //
2504 DeviceControl = 0;
2505 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
2506
2507 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Head, Device);
2508
2509 if (IdePrimary == IdeDev->Channel) {
2510 IoPortForBmic = IdeDev->IoPort->BusMasterBaseAddr + BMICP_OFFSET;
2511 IoPortForBmis = IdeDev->IoPort->BusMasterBaseAddr + BMISP_OFFSET;
2512 IoPortForBmid = IdeDev->IoPort->BusMasterBaseAddr + BMIDP_OFFSET;
2513 } else {
2514 if (IdeSecondary == IdeDev->Channel) {
2515 IoPortForBmic = IdeDev->IoPort->BusMasterBaseAddr + BMICS_OFFSET;
2516 IoPortForBmis = IdeDev->IoPort->BusMasterBaseAddr + BMISS_OFFSET;
2517 IoPortForBmid = IdeDev->IoPort->BusMasterBaseAddr + BMIDS_OFFSET;
2518 } else {
2519 return EFI_UNSUPPORTED;
2520 }
2521 }
2522
2523 RemainBlockNum = NumberOfBlocks;
2524 while (RemainBlockNum > 0) {
2525
2526 if (RemainBlockNum >= MAX_DMA_COMMAND_SECTORS) {
2527 //
2528 // SectorCount is used to record the number of sectors to be read
2529 // Max 256 sectors can be transfered at a time.
2530 //
2531 NumberOfBlocks = MAX_DMA_COMMAND_SECTORS;
2532 RemainBlockNum -= MAX_DMA_COMMAND_SECTORS;
2533 } else {
2534 NumberOfBlocks = (UINT16) RemainBlockNum;
2535 RemainBlockNum = 0;
2536 }
2537
2538 //
2539 // Calculate the number of PRD table to make sure the memory region
2540 // not cross 64K boundary
2541 //
2542 ByteCount = NumberOfBlocks * IdeDev->BlkIo.Media->BlockSize;
2543 PrdTableNum = ((ByteCount >> 16) + 1) + 1;
2544
2545 //
2546 // Build PRD table
2547 //
2548 PageCount = EFI_SIZE_TO_PAGES (2 * PrdTableNum * sizeof (IDE_DMA_PRD));
2549 Status = IdeDev->PciIo->AllocateBuffer (
2550 IdeDev->PciIo,
2551 AllocateAnyPages,
2552 EfiBootServicesData,
2553 PageCount,
2554 &MemPage,
2555 0
2556 );
2557 if (EFI_ERROR (Status)) {
2558 return EFI_OUT_OF_RESOURCES;
2559 }
2560 ZeroMem ((VOID *) ((UINTN) MemPage), EFI_PAGES_TO_SIZE (PageCount));
2561
2562 PrdAddr = (IDE_DMA_PRD *) ((UINTN) MemPage);
2563 //
2564 // To make sure PRD is allocated in one 64K page
2565 //
2566 if (((UINTN) PrdAddr & 0x0FFFF) > (((UINTN) PrdAddr + PrdTableNum * sizeof (IDE_DMA_PRD) - 1) & 0x0FFFF)) {
2567 UsedPrdAddr = (IDE_DMA_PRD *) ((UINTN) ((UINT8 *) PrdAddr + 0x10000) & 0xFFFF0000);
2568 } else {
2569 if ((UINTN) PrdAddr & 0x03) {
2570 UsedPrdAddr = (IDE_DMA_PRD *) ((UINTN) ((UINT8 *) PrdAddr + 0x04) & 0xFFFFFFFC);
2571 } else {
2572 UsedPrdAddr = PrdAddr;
2573 }
2574 }
2575
2576 //
2577 // Build the PRD table
2578 //
2579 Status = IdeDev->PciIo->Map (
2580 IdeDev->PciIo,
2581 EfiPciIoOperationBusMasterWrite,
2582 DataBuffer,
2583 &ByteCount,
2584 &DeviceAddress,
2585 &Map
2586 );
2587 if (EFI_ERROR (Status)) {
2588 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
2589 return EFI_OUT_OF_RESOURCES;
2590 }
2591 PrdBuffer = (UINT8 *) ((UINTN) DeviceAddress);
2592 TempPrdAddr = UsedPrdAddr;
2593 while (TRUE) {
2594
2595 ByteAvailable = 0x10000 - ((UINTN) PrdBuffer & 0xFFFF);
2596
2597 if (ByteCount <= ByteAvailable) {
2598 TempPrdAddr->RegionBaseAddr = (UINT32) ((UINTN) PrdBuffer);
2599 TempPrdAddr->ByteCount = (UINT16) ByteCount;
2600 TempPrdAddr->EndOfTable = 0x8000;
2601 break;
2602 }
2603
2604 TempPrdAddr->RegionBaseAddr = (UINT32) ((UINTN) PrdBuffer);
2605 TempPrdAddr->ByteCount = (UINT16) ByteAvailable;
2606
2607 ByteCount -= ByteAvailable;
2608 PrdBuffer += ByteAvailable;
2609 TempPrdAddr++;
2610 }
2611
2612 //
2613 // Set the base address to BMID register
2614 //
2615 IdeDev->PciIo->Io.Write (
2616 IdeDev->PciIo,
2617 EfiPciIoWidthUint32,
2618 EFI_PCI_IO_PASS_THROUGH_BAR,
2619 IoPortForBmid,
2620 1,
2621 &UsedPrdAddr
2622 );
2623
2624 //
2625 // Set BMIC register to identify the operation direction
2626 //
2627 IdeDev->PciIo->Io.Read (
2628 IdeDev->PciIo,
2629 EfiPciIoWidthUint8,
2630 EFI_PCI_IO_PASS_THROUGH_BAR,
2631 IoPortForBmic,
2632 1,
2633 &RegisterValue
2634 );
2635
2636 RegisterValue |= BMIC_nREAD;
2637
2638 IdeDev->PciIo->Io.Write (
2639 IdeDev->PciIo,
2640 EfiPciIoWidthUint8,
2641 EFI_PCI_IO_PASS_THROUGH_BAR,
2642 IoPortForBmic,
2643 1,
2644 &RegisterValue
2645 );
2646
2647 //
2648 // Read BMIS register and clear ERROR and INTR bit
2649 //
2650 IdeDev->PciIo->Io.Read (
2651 IdeDev->PciIo,
2652 EfiPciIoWidthUint8,
2653 EFI_PCI_IO_PASS_THROUGH_BAR,
2654 IoPortForBmis,
2655 1,
2656 &RegisterValue
2657 );
2658
2659 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
2660
2661 IdeDev->PciIo->Io.Write (
2662 IdeDev->PciIo,
2663 EfiPciIoWidthUint8,
2664 EFI_PCI_IO_PASS_THROUGH_BAR,
2665 IoPortForBmis,
2666 1,
2667 &RegisterValue
2668 );
2669
2670 //
2671 // Issue READ DMA command
2672 //
2673 Status = AtaCommandIssue (
2674 IdeDev,
2675 READ_DMA_CMD,
2676 Device,
2677 0,
2678 (UINT16) NumberOfBlocks,
2679 StartLba
2680 );
2681 if (EFI_ERROR (Status)) {
2682 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
2683 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
2684 return EFI_DEVICE_ERROR;
2685 }
2686
2687 //
2688 // Set START bit of BMIC register
2689 //
2690 IdeDev->PciIo->Io.Read (
2691 IdeDev->PciIo,
2692 EfiPciIoWidthUint8,
2693 EFI_PCI_IO_PASS_THROUGH_BAR,
2694 IoPortForBmic,
2695 1,
2696 &RegisterValue
2697 );
2698
2699 RegisterValue |= BMIC_START;
2700
2701 IdeDev->PciIo->Io.Write (
2702 IdeDev->PciIo,
2703 EfiPciIoWidthUint8,
2704 EFI_PCI_IO_PASS_THROUGH_BAR,
2705 IoPortForBmic,
2706 1,
2707 &RegisterValue
2708 );
2709
2710 //
2711 // Check the INTERRUPT and ERROR bit of BMIS
2712 // Max transfer number of sectors for one command is 65536(32Mbyte),
2713 // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).
2714 // So set the variable Count to 2000, for about 2 second timeout time.
2715 //
2716 Count = 2000;
2717 while (TRUE) {
2718
2719 IdeDev->PciIo->Io.Read (
2720 IdeDev->PciIo,
2721 EfiPciIoWidthUint8,
2722 EFI_PCI_IO_PASS_THROUGH_BAR,
2723 IoPortForBmis,
2724 1,
2725 &RegisterValue
2726 );
2727 if ((RegisterValue & (BMIS_INTERRUPT | BMIS_ERROR)) || (Count == 0)) {
2728 if ((RegisterValue & BMIS_ERROR) || (Count == 0)) {
2729 //
2730 // Clear START bit of BMIC register before return EFI_DEVICE_ERROR
2731 //
2732 IdeDev->PciIo->Io.Read (
2733 IdeDev->PciIo,
2734 EfiPciIoWidthUint8,
2735 EFI_PCI_IO_PASS_THROUGH_BAR,
2736 IoPortForBmic,
2737 1,
2738 &RegisterValue
2739 );
2740
2741 RegisterValue &= ~((UINT8)BMIC_START);
2742
2743 IdeDev->PciIo->Io.Write (
2744 IdeDev->PciIo,
2745 EfiPciIoWidthUint8,
2746 EFI_PCI_IO_PASS_THROUGH_BAR,
2747 IoPortForBmic,
2748 1,
2749 &RegisterValue
2750 );
2751 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
2752 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
2753 return EFI_DEVICE_ERROR;
2754 }
2755 break;
2756 }
2757
2758 gBS->Stall (1000);
2759 Count --;
2760 }
2761
2762 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
2763 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
2764 //
2765 // Read Status Register of IDE device to clear interrupt
2766 //
2767 RegisterValue = IDEReadPortB(IdeDev->PciIo,IdeDev->IoPort->Reg.Status);
2768 //
2769 // Clear START bit of BMIC register
2770 //
2771 IdeDev->PciIo->Io.Read (
2772 IdeDev->PciIo,
2773 EfiPciIoWidthUint8,
2774 EFI_PCI_IO_PASS_THROUGH_BAR,
2775 IoPortForBmic,
2776 1,
2777 &RegisterValue
2778 );
2779
2780 RegisterValue &= ~((UINT8) BMIC_START);
2781
2782 IdeDev->PciIo->Io.Write (
2783 IdeDev->PciIo,
2784 EfiPciIoWidthUint8,
2785 EFI_PCI_IO_PASS_THROUGH_BAR,
2786 IoPortForBmic,
2787 1,
2788 &RegisterValue
2789 );
2790
2791 if (RegisterValue & BMIS_ERROR) {
2792 return EFI_DEVICE_ERROR;
2793 }
2794
2795 DataBuffer = (UINT8 *) DataBuffer + NumberOfBlocks * IdeDev->BlkIo.Media->BlockSize;
2796 StartLba += NumberOfBlocks;
2797 }
2798
2799 //
2800 // Disable interrupt of Select device
2801 //
2802 IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl);
2803 DeviceControl |= IEN_L;
2804 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
2805
2806 return EFI_SUCCESS;
2807 }
2808
2809 /**
2810 This function is called by the AtaBlkIoWriteBlocks() to perform
2811 writing to media in block unit. The function has been enhanced to
2812 support >120GB access and transfer at most 65536 blocks per command
2813
2814 @param[in] *IdeDev pointer pointing to IDE_BLK_IO_DEV data structure, used
2815 to record all the information of the IDE device.
2816
2817 @param[in] *DataBuffer A pointer to the source buffer for the data.
2818
2819 @param[in] StartLba The starting logical block address to write to
2820 on the device media.
2821
2822 @param[in] NumberOfBlocks The number of transfer data blocks.
2823
2824 @return The device status of UDMA operation. If the operation is
2825 successful, return EFI_SUCCESS.
2826
2827 TODO: EFI_UNSUPPORTED - add return value to function comment
2828 TODO: EFI_DEVICE_ERROR - add return value to function comment
2829 TODO: EFI_DEVICE_ERROR - add return value to function comment
2830 **/
2831 EFI_STATUS
2832 AtaUdmaWriteExt (
2833 IN IDE_BLK_IO_DEV *IdeDev,
2834 IN VOID *DataBuffer,
2835 IN EFI_LBA StartLba,
2836 IN UINTN NumberOfBlocks
2837 )
2838 {
2839 IDE_DMA_PRD *PrdAddr;
2840 IDE_DMA_PRD *UsedPrdAddr;
2841 IDE_DMA_PRD *TempPrdAddr;
2842 UINT8 RegisterValue;
2843 UINT8 Device;
2844 UINT64 IoPortForBmic;
2845 UINT64 IoPortForBmis;
2846 UINT64 IoPortForBmid;
2847 EFI_STATUS Status;
2848 UINTN PrdTableNum;
2849 UINTN ByteCount;
2850 UINTN ByteAvailable;
2851 UINT8 *PrdBuffer;
2852 UINTN RemainBlockNum;
2853 UINT8 DeviceControl;
2854 UINT32 Count;
2855 UINTN PageCount;
2856 VOID *Map;
2857 VOID *MemPage;
2858 EFI_PHYSICAL_ADDRESS DeviceAddress;
2859
2860 //
2861 // Channel and device differential
2862 //
2863 Device = (UINT8) ((IdeDev->Device << 4) | 0xe0);
2864
2865 //
2866 // Enable interrupt to support UDMA and Select device
2867 //
2868 DeviceControl = 0;
2869 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
2870
2871 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Head, Device);
2872
2873 if (IdePrimary == IdeDev->Channel) {
2874 IoPortForBmic = IdeDev->IoPort->BusMasterBaseAddr + BMICP_OFFSET;
2875 IoPortForBmis = IdeDev->IoPort->BusMasterBaseAddr + BMISP_OFFSET;
2876 IoPortForBmid = IdeDev->IoPort->BusMasterBaseAddr + BMIDP_OFFSET;
2877 } else {
2878 if (IdeSecondary == IdeDev->Channel) {
2879 IoPortForBmic = IdeDev->IoPort->BusMasterBaseAddr + BMICS_OFFSET;
2880 IoPortForBmis = IdeDev->IoPort->BusMasterBaseAddr + BMISS_OFFSET;
2881 IoPortForBmid = IdeDev->IoPort->BusMasterBaseAddr + BMIDS_OFFSET;
2882 } else {
2883 return EFI_UNSUPPORTED;
2884 }
2885 }
2886
2887 RemainBlockNum = NumberOfBlocks;
2888 while (RemainBlockNum > 0) {
2889
2890 if (RemainBlockNum >= MAX_DMA_EXT_COMMAND_SECTORS) {
2891 //
2892 // SectorCount is used to record the number of sectors to be read
2893 // Max 65536 sectors can be transfered at a time.
2894 //
2895 NumberOfBlocks = MAX_DMA_EXT_COMMAND_SECTORS;
2896 RemainBlockNum -= MAX_DMA_EXT_COMMAND_SECTORS;
2897 } else {
2898 NumberOfBlocks = (UINT16) RemainBlockNum;
2899 RemainBlockNum = 0;
2900 }
2901
2902 //
2903 // Calculate the number of PRD table to make sure the memory region
2904 // not cross 64K boundary
2905 //
2906 ByteCount = NumberOfBlocks * IdeDev->BlkIo.Media->BlockSize;
2907 PrdTableNum = ((ByteCount >> 16) + 1) + 1;
2908
2909 //
2910 // Build PRD table
2911 //
2912 PageCount = EFI_SIZE_TO_PAGES (2 * PrdTableNum * sizeof (IDE_DMA_PRD));
2913 Status = IdeDev->PciIo->AllocateBuffer (
2914 IdeDev->PciIo,
2915 AllocateAnyPages,
2916 EfiBootServicesData,
2917 PageCount,
2918 &MemPage,
2919 0
2920 );
2921 if (EFI_ERROR (Status)) {
2922 return EFI_OUT_OF_RESOURCES;
2923 }
2924 ZeroMem ((VOID *) ((UINTN) MemPage), EFI_PAGES_TO_SIZE (PageCount));
2925
2926 PrdAddr = (IDE_DMA_PRD *) ((UINTN) MemPage);
2927 //
2928 // To make sure PRD is allocated in one 64K page
2929 //
2930 if (((UINTN) PrdAddr & 0x0FFFF) > (((UINTN) PrdAddr + PrdTableNum * sizeof (IDE_DMA_PRD) - 1) & 0x0FFFF)) {
2931 UsedPrdAddr = (IDE_DMA_PRD *) ((UINTN) ((UINT8 *) PrdAddr + 0x10000) & 0xFFFF0000);
2932 } else {
2933 if ((UINTN) PrdAddr & 0x03) {
2934 UsedPrdAddr = (IDE_DMA_PRD *) ((UINTN) ((UINT8 *) PrdAddr + 0x04) & 0xFFFFFFFC);
2935 } else {
2936 UsedPrdAddr = PrdAddr;
2937 }
2938 }
2939
2940 //
2941 // Build the PRD table
2942 //
2943 Status = IdeDev->PciIo->Map (
2944 IdeDev->PciIo,
2945 EfiPciIoOperationBusMasterRead,
2946 DataBuffer,
2947 &ByteCount,
2948 &DeviceAddress,
2949 &Map
2950 );
2951 if (EFI_ERROR (Status)) {
2952 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
2953 return EFI_OUT_OF_RESOURCES;
2954 }
2955 PrdBuffer = (UINT8 *) ((UINTN) DeviceAddress);
2956 TempPrdAddr = UsedPrdAddr;
2957 while (TRUE) {
2958
2959 ByteAvailable = 0x10000 - ((UINTN) PrdBuffer & 0xFFFF);
2960
2961 if (ByteCount <= ByteAvailable) {
2962 TempPrdAddr->RegionBaseAddr = (UINT32) ((UINTN) PrdBuffer);
2963 TempPrdAddr->ByteCount = (UINT16) ByteCount;
2964 TempPrdAddr->EndOfTable = 0x8000;
2965 break;
2966 }
2967
2968 TempPrdAddr->RegionBaseAddr = (UINT32) ((UINTN) PrdBuffer);
2969 TempPrdAddr->ByteCount = (UINT16) ByteAvailable;
2970
2971 ByteCount -= ByteAvailable;
2972 PrdBuffer += ByteAvailable;
2973 TempPrdAddr++;
2974 }
2975
2976 //
2977 // Set the base address to BMID register
2978 //
2979 IdeDev->PciIo->Io.Write (
2980 IdeDev->PciIo,
2981 EfiPciIoWidthUint32,
2982 EFI_PCI_IO_PASS_THROUGH_BAR,
2983 IoPortForBmid,
2984 1,
2985 &UsedPrdAddr
2986 );
2987
2988 //
2989 // Set BMIC register to identify the operation direction
2990 //
2991 IdeDev->PciIo->Io.Read (
2992 IdeDev->PciIo,
2993 EfiPciIoWidthUint8,
2994 EFI_PCI_IO_PASS_THROUGH_BAR,
2995 IoPortForBmic,
2996 1,
2997 &RegisterValue
2998 );
2999 //
3000 // 0000 1000
3001 //
3002 RegisterValue &= ~((UINT8) BMIC_nREAD);
3003
3004 IdeDev->PciIo->Io.Write (
3005 IdeDev->PciIo,
3006 EfiPciIoWidthUint8,
3007 EFI_PCI_IO_PASS_THROUGH_BAR,
3008 IoPortForBmic,
3009 1,
3010 &RegisterValue
3011 );
3012
3013 //
3014 // Read BMIS register and clear ERROR and INTR bit
3015 //
3016 IdeDev->PciIo->Io.Read (
3017 IdeDev->PciIo,
3018 EfiPciIoWidthUint8,
3019 EFI_PCI_IO_PASS_THROUGH_BAR,
3020 IoPortForBmis,
3021 1,
3022 &RegisterValue
3023 );
3024
3025 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
3026
3027 IdeDev->PciIo->Io.Write (
3028 IdeDev->PciIo,
3029 EfiPciIoWidthUint8,
3030 EFI_PCI_IO_PASS_THROUGH_BAR,
3031 IoPortForBmis,
3032 1,
3033 &RegisterValue
3034 );
3035
3036 //
3037 // Issue WRITE DMA EXT command
3038 //
3039 Status = AtaCommandIssueExt (
3040 IdeDev,
3041 WRITE_DMA_EXT_CMD,
3042 Device,
3043 0,
3044 (UINT16) NumberOfBlocks,
3045 StartLba
3046 );
3047 if (EFI_ERROR (Status)) {
3048 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
3049 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
3050 return EFI_DEVICE_ERROR;
3051 }
3052
3053 //
3054 // Set START bit of BMIC register
3055 //
3056 IdeDev->PciIo->Io.Read (
3057 IdeDev->PciIo,
3058 EfiPciIoWidthUint8,
3059 EFI_PCI_IO_PASS_THROUGH_BAR,
3060 IoPortForBmic,
3061 1,
3062 &RegisterValue
3063 );
3064
3065 RegisterValue |= BMIC_START;
3066
3067 IdeDev->PciIo->Io.Write (
3068 IdeDev->PciIo,
3069 EfiPciIoWidthUint8,
3070 EFI_PCI_IO_PASS_THROUGH_BAR,
3071 IoPortForBmic,
3072 1,
3073 &RegisterValue
3074 );
3075
3076 //
3077 // Check the INTERRUPT and ERROR bit of BMIS
3078 // Max transfer number of sectors for one command is 65536(32Mbyte),
3079 // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).
3080 // So set the variable Count to 2000, for about 2 second timeout time.
3081 //
3082 Count = 2000;
3083 while (TRUE) {
3084
3085 IdeDev->PciIo->Io.Read (
3086 IdeDev->PciIo,
3087 EfiPciIoWidthUint8,
3088 EFI_PCI_IO_PASS_THROUGH_BAR,
3089 IoPortForBmis,
3090 1,
3091 &RegisterValue
3092 );
3093 if ((RegisterValue & (BMIS_INTERRUPT | BMIS_ERROR)) || (Count == 0)) {
3094 if ((RegisterValue & BMIS_ERROR) || (Count == 0)) {
3095 //
3096 // Clear START bit of BMIC register before return EFI_DEVICE_ERROR
3097 //
3098 IdeDev->PciIo->Io.Read (
3099 IdeDev->PciIo,
3100 EfiPciIoWidthUint8,
3101 EFI_PCI_IO_PASS_THROUGH_BAR,
3102 IoPortForBmic,
3103 1,
3104 &RegisterValue
3105 );
3106
3107 RegisterValue &= ~((UINT8)BMIC_START);
3108
3109 IdeDev->PciIo->Io.Write (
3110 IdeDev->PciIo,
3111 EfiPciIoWidthUint8,
3112 EFI_PCI_IO_PASS_THROUGH_BAR,
3113 IoPortForBmic,
3114 1,
3115 &RegisterValue
3116 );
3117 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
3118 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
3119 return EFI_DEVICE_ERROR;
3120 }
3121 break;
3122 }
3123
3124 gBS->Stall (1000);
3125 Count --;
3126 }
3127
3128 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
3129 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
3130 //
3131 // Read Status Register of IDE device to clear interrupt
3132 //
3133 RegisterValue = IDEReadPortB(IdeDev->PciIo,IdeDev->IoPort->Reg.Status);
3134 //
3135 // Clear START bit of BMIC register
3136 //
3137 IdeDev->PciIo->Io.Read (
3138 IdeDev->PciIo,
3139 EfiPciIoWidthUint8,
3140 EFI_PCI_IO_PASS_THROUGH_BAR,
3141 IoPortForBmic,
3142 1,
3143 &RegisterValue
3144 );
3145
3146 RegisterValue &= ~((UINT8) BMIC_START);
3147
3148 IdeDev->PciIo->Io.Write (
3149 IdeDev->PciIo,
3150 EfiPciIoWidthUint8,
3151 EFI_PCI_IO_PASS_THROUGH_BAR,
3152 IoPortForBmic,
3153 1,
3154 &RegisterValue
3155 );
3156
3157 DataBuffer = (UINT8 *) DataBuffer + NumberOfBlocks * IdeDev->BlkIo.Media->BlockSize;
3158 StartLba += NumberOfBlocks;
3159 }
3160
3161 //
3162 // Disable interrupt of Select device
3163 //
3164 IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl);
3165 DeviceControl |= IEN_L;
3166 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
3167
3168 return EFI_SUCCESS;
3169 }
3170
3171 /**
3172 This function is called by the AtaBlkIoWriteBlocks() to perform
3173 writing to media in block unit. The function has been enhanced to
3174 support >120GB access and transfer at most 65536 blocks per command
3175
3176 @param[in] *IdeDev
3177 pointer pointing to IDE_BLK_IO_DEV data structure, used
3178 to record all the information of the IDE device.
3179
3180 @param[in] *DataBuffer
3181 A pointer to the source buffer for the data.
3182
3183 @param[in] StartLba
3184 The starting logical block address to write to
3185 on the device media.
3186
3187 @param[in] NumberOfBlocks
3188 The number of transfer data blocks.
3189
3190 @return The device status of UDMA operation. If the operation is
3191 successful, return EFI_SUCCESS.
3192
3193 TODO: EFI_UNSUPPORTED - add return value to function comment
3194 TODO: EFI_DEVICE_ERROR - add return value to function comment
3195 TODO: EFI_DEVICE_ERROR - add return value to function comment
3196 **/
3197 EFI_STATUS
3198 AtaUdmaWrite (
3199 IN IDE_BLK_IO_DEV *IdeDev,
3200 IN VOID *DataBuffer,
3201 IN EFI_LBA StartLba,
3202 IN UINTN NumberOfBlocks
3203 )
3204 {
3205 IDE_DMA_PRD *PrdAddr;
3206 IDE_DMA_PRD *UsedPrdAddr;
3207 IDE_DMA_PRD *TempPrdAddr;
3208 UINT8 RegisterValue;
3209 UINT8 Device;
3210 UINT64 IoPortForBmic;
3211 UINT64 IoPortForBmis;
3212 UINT64 IoPortForBmid;
3213 EFI_STATUS Status;
3214 UINTN PrdTableNum;
3215 UINTN ByteCount;
3216 UINTN ByteAvailable;
3217 UINT8 *PrdBuffer;
3218 UINTN RemainBlockNum;
3219 UINT8 DeviceControl;
3220 UINT32 Count;
3221 UINTN PageCount;
3222 VOID *Map;
3223 VOID *MemPage;
3224 EFI_PHYSICAL_ADDRESS DeviceAddress;
3225
3226 //
3227 // Channel and device differential
3228 //
3229 Device = (UINT8) ((IdeDev->Device << 4) | 0xe0);
3230
3231 //
3232 // Enable interrupt to support UDMA
3233 //
3234 DeviceControl = 0;
3235 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
3236
3237 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Head, Device);
3238
3239 if (IdePrimary == IdeDev->Channel) {
3240 IoPortForBmic = IdeDev->IoPort->BusMasterBaseAddr + BMICP_OFFSET;
3241 IoPortForBmis = IdeDev->IoPort->BusMasterBaseAddr + BMISP_OFFSET;
3242 IoPortForBmid = IdeDev->IoPort->BusMasterBaseAddr + BMIDP_OFFSET;
3243 } else {
3244 if (IdeSecondary == IdeDev->Channel) {
3245 IoPortForBmic = IdeDev->IoPort->BusMasterBaseAddr + BMICS_OFFSET;
3246 IoPortForBmis = IdeDev->IoPort->BusMasterBaseAddr + BMISS_OFFSET;
3247 IoPortForBmid = IdeDev->IoPort->BusMasterBaseAddr + BMIDS_OFFSET;
3248 } else {
3249 return EFI_UNSUPPORTED;
3250 }
3251 }
3252
3253 RemainBlockNum = NumberOfBlocks;
3254 while (RemainBlockNum > 0) {
3255
3256 if (RemainBlockNum >= MAX_DMA_COMMAND_SECTORS) {
3257 //
3258 // SectorCount is used to record the number of sectors to be read
3259 // Max 256 sectors can be transfered at a time.
3260 //
3261 NumberOfBlocks = MAX_DMA_COMMAND_SECTORS;
3262 RemainBlockNum -= MAX_DMA_COMMAND_SECTORS;
3263 } else {
3264 NumberOfBlocks = (UINT16) RemainBlockNum;
3265 RemainBlockNum = 0;
3266 }
3267
3268 //
3269 // Calculate the number of PRD table to make sure the memory region
3270 // not cross 64K boundary
3271 //
3272 ByteCount = NumberOfBlocks * IdeDev->BlkIo.Media->BlockSize;
3273 PrdTableNum = ((ByteCount >> 16) + 1) + 1;
3274
3275 //
3276 // Build PRD table
3277 //
3278 PageCount = EFI_SIZE_TO_PAGES (2 * PrdTableNum * sizeof (IDE_DMA_PRD));
3279 Status = IdeDev->PciIo->AllocateBuffer (
3280 IdeDev->PciIo,
3281 AllocateAnyPages,
3282 EfiBootServicesData,
3283 PageCount,
3284 &MemPage,
3285 0
3286 );
3287 if (EFI_ERROR (Status)) {
3288 return EFI_OUT_OF_RESOURCES;
3289 }
3290 ZeroMem ((VOID *) ((UINTN) MemPage), EFI_PAGES_TO_SIZE (PageCount));
3291
3292 PrdAddr = (IDE_DMA_PRD *) ((UINTN) MemPage);
3293
3294 //
3295 // To make sure PRD is allocated in one 64K page
3296 //
3297 if (((UINTN) PrdAddr & 0x0FFFF) > (((UINTN) PrdAddr + PrdTableNum * sizeof (IDE_DMA_PRD) - 1) & 0x0FFFF)) {
3298 UsedPrdAddr = (IDE_DMA_PRD *) ((UINTN) ((UINT8 *) PrdAddr + 0x10000) & 0xFFFF0000);
3299 } else {
3300 if ((UINTN) PrdAddr & 0x03) {
3301 UsedPrdAddr = (IDE_DMA_PRD *) ((UINTN) ((UINT8 *) PrdAddr + 0x04) & 0xFFFFFFFC);
3302 } else {
3303 UsedPrdAddr = PrdAddr;
3304 }
3305 }
3306
3307 //
3308 // Build the PRD table
3309 //
3310 Status = IdeDev->PciIo->Map (
3311 IdeDev->PciIo,
3312 EfiPciIoOperationBusMasterRead,
3313 DataBuffer,
3314 &ByteCount,
3315 &DeviceAddress,
3316 &Map
3317 );
3318 if (EFI_ERROR (Status)) {
3319 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
3320 return EFI_OUT_OF_RESOURCES;
3321 }
3322 PrdBuffer = (UINT8 *) ((UINTN) DeviceAddress);
3323 TempPrdAddr = UsedPrdAddr;
3324 while (TRUE) {
3325
3326 ByteAvailable = 0x10000 - ((UINTN) PrdBuffer & 0xFFFF);
3327
3328 if (ByteCount <= ByteAvailable) {
3329 TempPrdAddr->RegionBaseAddr = (UINT32) ((UINTN) PrdBuffer);
3330 TempPrdAddr->ByteCount = (UINT16) ByteCount;
3331 TempPrdAddr->EndOfTable = 0x8000;
3332 break;
3333 }
3334
3335 TempPrdAddr->RegionBaseAddr = (UINT32) ((UINTN) PrdBuffer);
3336 TempPrdAddr->ByteCount = (UINT16) ByteAvailable;
3337
3338 ByteCount -= ByteAvailable;
3339 PrdBuffer += ByteAvailable;
3340 TempPrdAddr++;
3341 }
3342
3343 //
3344 // Set the base address to BMID register
3345 //
3346 IdeDev->PciIo->Io.Write (
3347 IdeDev->PciIo,
3348 EfiPciIoWidthUint32,
3349 EFI_PCI_IO_PASS_THROUGH_BAR,
3350 IoPortForBmid,
3351 1,
3352 &UsedPrdAddr
3353 );
3354
3355 //
3356 // Set BMIC register to identify the operation direction
3357 //
3358 IdeDev->PciIo->Io.Read (
3359 IdeDev->PciIo,
3360 EfiPciIoWidthUint8,
3361 EFI_PCI_IO_PASS_THROUGH_BAR,
3362 IoPortForBmic,
3363 1,
3364 &RegisterValue
3365 );
3366 //
3367 // 0000 1000
3368 //
3369 RegisterValue &= ~((UINT8) BMIC_nREAD);
3370
3371 IdeDev->PciIo->Io.Write (
3372 IdeDev->PciIo,
3373 EfiPciIoWidthUint8,
3374 EFI_PCI_IO_PASS_THROUGH_BAR,
3375 IoPortForBmic,
3376 1,
3377 &RegisterValue
3378 );
3379
3380 //
3381 // Read BMIS register and clear ERROR and INTR bit
3382 //
3383 IdeDev->PciIo->Io.Read (
3384 IdeDev->PciIo,
3385 EfiPciIoWidthUint8,
3386 EFI_PCI_IO_PASS_THROUGH_BAR,
3387 IoPortForBmis,
3388 1,
3389 &RegisterValue
3390 );
3391
3392 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
3393
3394 IdeDev->PciIo->Io.Write (
3395 IdeDev->PciIo,
3396 EfiPciIoWidthUint8,
3397 EFI_PCI_IO_PASS_THROUGH_BAR,
3398 IoPortForBmis,
3399 1,
3400 &RegisterValue
3401 );
3402
3403 //
3404 // Issue WRITE DMA command
3405 //
3406 Status = AtaCommandIssue (
3407 IdeDev,
3408 WRITE_DMA_CMD,
3409 Device,
3410 0,
3411 (UINT16) NumberOfBlocks,
3412 StartLba
3413 );
3414 if (EFI_ERROR (Status)) {
3415 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
3416 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
3417 return EFI_DEVICE_ERROR;
3418 }
3419
3420 //
3421 // Set START bit of BMIC register
3422 //
3423 IdeDev->PciIo->Io.Read (
3424 IdeDev->PciIo,
3425 EfiPciIoWidthUint8,
3426 EFI_PCI_IO_PASS_THROUGH_BAR,
3427 IoPortForBmic,
3428 1,
3429 &RegisterValue
3430 );
3431
3432 RegisterValue |= BMIC_START;
3433
3434 IdeDev->PciIo->Io.Write (
3435 IdeDev->PciIo,
3436 EfiPciIoWidthUint8,
3437 EFI_PCI_IO_PASS_THROUGH_BAR,
3438 IoPortForBmic,
3439 1,
3440 &RegisterValue
3441 );
3442
3443 //
3444 // Check the INTERRUPT and ERROR bit of BMIS
3445 // Max transfer number of sectors for one command is 65536(32Mbyte),
3446 // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).
3447 // So set the variable Count to 2000, for about 2 second timeout time.
3448 //
3449 Count = 2000;
3450 while (TRUE) {
3451
3452 IdeDev->PciIo->Io.Read (
3453 IdeDev->PciIo,
3454 EfiPciIoWidthUint8,
3455 EFI_PCI_IO_PASS_THROUGH_BAR,
3456 IoPortForBmis,
3457 1,
3458 &RegisterValue
3459 );
3460 if ((RegisterValue & (BMIS_INTERRUPT | BMIS_ERROR)) || (Count == 0)) {
3461 if ((RegisterValue & BMIS_ERROR) || (Count == 0)) {
3462 //
3463 // Clear START bit of BMIC register before return EFI_DEVICE_ERROR
3464 //
3465 IdeDev->PciIo->Io.Read (
3466 IdeDev->PciIo,
3467 EfiPciIoWidthUint8,
3468 EFI_PCI_IO_PASS_THROUGH_BAR,
3469 IoPortForBmic,
3470 1,
3471 &RegisterValue
3472 );
3473
3474 RegisterValue &= ~((UINT8)BMIC_START);
3475
3476 IdeDev->PciIo->Io.Write (
3477 IdeDev->PciIo,
3478 EfiPciIoWidthUint8,
3479 EFI_PCI_IO_PASS_THROUGH_BAR,
3480 IoPortForBmic,
3481 1,
3482 &RegisterValue
3483 );
3484 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
3485 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
3486 return EFI_DEVICE_ERROR;
3487 }
3488 break;
3489 }
3490
3491 gBS->Stall (1000);
3492 Count --;
3493 }
3494
3495 IdeDev->PciIo->FreeBuffer (IdeDev->PciIo, PageCount, MemPage);
3496 IdeDev->PciIo->Unmap (IdeDev->PciIo, Map);
3497
3498 //
3499 // Read Status Register of IDE device to clear interrupt
3500 //
3501 RegisterValue = IDEReadPortB(IdeDev->PciIo,IdeDev->IoPort->Reg.Status);
3502 //
3503 // Clear START bit of BMIC register
3504 //
3505 IdeDev->PciIo->Io.Read (
3506 IdeDev->PciIo,
3507 EfiPciIoWidthUint8,
3508 EFI_PCI_IO_PASS_THROUGH_BAR,
3509 IoPortForBmic,
3510 1,
3511 &RegisterValue
3512 );
3513
3514 RegisterValue &= ~((UINT8) BMIC_START);
3515
3516 IdeDev->PciIo->Io.Write (
3517 IdeDev->PciIo,
3518 EfiPciIoWidthUint8,
3519 EFI_PCI_IO_PASS_THROUGH_BAR,
3520 IoPortForBmic,
3521 1,
3522 &RegisterValue
3523 );
3524
3525 DataBuffer = (UINT8 *) DataBuffer + NumberOfBlocks * IdeDev->BlkIo.Media->BlockSize;
3526 StartLba += NumberOfBlocks;
3527 }
3528
3529 //
3530 // Disable interrupt of Select device
3531 //
3532 IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl);
3533 DeviceControl |= IEN_L;
3534 IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
3535
3536 return EFI_SUCCESS;
3537 }
EFI Development Kit II mirror for PVE