EdkModulePkg/Bus/Pci/IdeBus/Dxe/idedata.h

   1 /*++
   2 Copyright (c) 2006, Intel Corporation
   3 All rights reserved. This program and the accompanying materials
   4 are licensed and made available under the terms and conditions of the BSD License
   5 which accompanies this distribution.  The full text of the license may be found at
   6 http://opensource.org/licenses/bsd-license.php
   7
   8 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10
  11 Module Name:
  12
  13     idedata.h
  14
  15 Abstract:
  16
  17     Header file for IDE Bus Driver's Data Structures
  18
  19 Revision History
  20 ++*/
  21
  22 // TODO: fix comment to end with --*/
  23 #ifndef _IDE_DATA_H
  24 #define _IDE_DATA_H
  25
  26 //
  27 // bit definition
  28 //
  29 #define bit0  (1 << 0)
  30 #define bit1  (1 << 1)
  31 #define bit2  (1 << 2)
  32 #define bit3  (1 << 3)
  33 #define bit4  (1 << 4)
  34 #define bit5  (1 << 5)
  35 #define bit6  (1 << 6)
  36 #define bit7  (1 << 7)
  37 #define bit8  (1 << 8)
  38 #define bit9  (1 << 9)
  39 #define bit10 (1 << 10)
  40 #define bit11 (1 << 11)
  41 #define bit12 (1 << 12)
  42 #define bit13 (1 << 13)
  43 #define bit14 (1 << 14)
  44 #define bit15 (1 << 15)
  45 #define bit16 (1 << 16)
  46 #define bit17 (1 << 17)
  47 #define bit18 (1 << 18)
  48 #define bit19 (1 << 19)
  49 #define bit20 (1 << 20)
  50 #define bit21 (1 << 21)
  51 #define bit22 (1 << 22)
  52 #define bit23 (1 << 23)
  53 #define bit24 (1 << 24)
  54 #define bit25 (1 << 25)
  55 #define bit26 (1 << 26)
  56 #define bit27 (1 << 27)
  57 #define bit28 (1 << 28)
  58 #define bit29 (1 << 29)
  59 #define bit30 (1 << 30)
  60 #define bit31 (1 << 31)
  61
  62 //
  63 // common constants
  64 //
  65 #define STALL_1_MILLI_SECOND  1000    // stall 1 ms
  66 #define STALL_1_SECOND        1000000 // stall 1 second
  67 typedef enum {
  68   IdePrimary    = 0,
  69   IdeSecondary  = 1,
  70   IdeMaxChannel = 2
  71 } EFI_IDE_CHANNEL;
  72
  73 typedef enum {
  74   IdeMaster     = 0,
  75   IdeSlave      = 1,
  76   IdeMaxDevice  = 2
  77 } EFI_IDE_DEVICE;
  78
  79 typedef enum {
  80   IdeMagnetic,                        /* ZIP Drive or LS120 Floppy Drive */
  81   IdeCdRom,                           /* ATAPI CDROM */
  82   IdeHardDisk,                        /* Hard Disk */
  83   Ide48bitAddressingHardDisk,         /* Hard Disk larger than 120GB */
  84   IdeUnknown
  85 } IDE_DEVICE_TYPE;
  86
  87 //
  88 // IDE Registers
  89 //
  90 typedef union {
  91   UINT16  Command;        /* when write */
  92   UINT16  Status;         /* when read */
  93 } IDE_CMD_OR_STATUS;
  94
  95 typedef union {
  96   UINT16  Error;          /* when read */
  97   UINT16  Feature;        /* when write */
  98 } IDE_ERROR_OR_FEATURE;
  99
 100 typedef union {
 101   UINT16  AltStatus;      /* when read */
 102   UINT16  DeviceControl;  /* when write */
 103 } IDE_AltStatus_OR_DeviceControl;
 104
 105 //
 106 // IDE registers set
 107 //
 108 typedef struct {
 109   UINT16                          Data;
 110   IDE_ERROR_OR_FEATURE            Reg1;
 111   UINT16                          SectorCount;
 112   UINT16                          SectorNumber;
 113   UINT16                          CylinderLsb;
 114   UINT16                          CylinderMsb;
 115   UINT16                          Head;
 116   IDE_CMD_OR_STATUS               Reg;
 117
 118   IDE_AltStatus_OR_DeviceControl  Alt;
 119   UINT16                          DriveAddress;
 120
 121   UINT16                          MasterSlave;
 122   UINT16                          BusMasterBaseAddr;
 123 } IDE_BASE_REGISTERS;
 124
 125 //
 126 // IDE registers' base addresses
 127 //
 128 typedef struct {
 129   UINT16  CommandBlockBaseAddr;
 130   UINT16  ControlBlockBaseAddr;
 131   UINT16  BusMasterBaseAddr;
 132 } IDE_REGISTERS_BASE_ADDR;
 133
 134 //
 135 // Bit definitions in Programming Interface byte of the Class Code field
 136 // in PCI IDE controller's Configuration Space
 137 //
 138 #define IDE_PRIMARY_OPERATING_MODE            bit0
 139 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR    bit1
 140 #define IDE_SECONDARY_OPERATING_MODE          bit2
 141 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR  bit3
 142
 143 //
 144 // IDE registers bit definitions
 145 //
 146
 147 //
 148 // Err Reg
 149 //
 150 #define BBK_ERR   bit7  /* Bad block detected */
 151 #define UNC_ERR   bit6  /* Uncorrectable Data */
 152 #define MC_ERR    bit5  /* Media Change */
 153 #define IDNF_ERR  bit4  /* ID Not Found */
 154 #define MCR_ERR   bit3  /* Media Change Requested */
 155 #define ABRT_ERR  bit2  /* Aborted Command */
 156 #define TK0NF_ERR bit1  /* Track 0 Not Found */
 157 #define AMNF_ERR  bit0  /* Address Mark Not Found */
 158
 159 //
 160 // Device/Head Reg
 161 //
 162 #define LBA_MODE  bit6
 163 #define DEV       bit4
 164 #define HS3       bit3
 165 #define HS2       bit2
 166 #define HS1       bit1
 167 #define HS0       bit0
 168 #define CHS_MODE  (0)
 169 #define DRV0      (0)
 170 #define DRV1      (1)
 171 #define MST_DRV   DRV0
 172 #define SLV_DRV   DRV1
 173
 174 //
 175 // Status Reg
 176 //
 177 #define BSY   bit7  /* Controller Busy */
 178 #define DRDY  bit6  /* Drive Ready */
 179 #define DWF   bit5  /* Drive Write Fault */
 180 #define DSC   bit4  /* Disk Seek Complete */
 181 #define DRQ   bit3  /* Data Request */
 182 #define CORR  bit2  /* Corrected Data */
 183 #define IDX   bit1  /* Index */
 184 #define ERR   bit0  /* Error */
 185
 186 //
 187 // Device Control Reg
 188 //
 189 #define SRST  bit2  /* Software Reset */
 190 #define IEN_L bit1  /* Interrupt Enable #*/
 191
 192 //
 193 // Bus Master Reg
 194 //
 195 #define BMIC_nREAD      bit3
 196 #define BMIC_START      bit0
 197 #define BMIS_INTERRUPT  bit2
 198 #define BMIS_ERROR      bit1
 199
 200 #define BMICP_OFFSET    0x00
 201 #define BMISP_OFFSET    0x02
 202 #define BMIDP_OFFSET    0x04
 203 #define BMICS_OFFSET    0x08
 204 #define BMISS_OFFSET    0x0A
 205 #define BMIDS_OFFSET    0x0C
 206
 207 //
 208 // Time Out Value For IDE Device Polling
 209 //
 210
 211 //
 212 // ATATIMEOUT is used for waiting time out for ATA device
 213 //
 214
 215 //
 216 // 1 second
 217 //
 218 #define ATATIMEOUT  1000
 219
 220 //
 221 // ATAPITIMEOUT is used for waiting operation
 222 // except read and write time out for ATAPI device
 223 //
 224
 225 //
 226 // 1 second
 227 //
 228 #define ATAPITIMEOUT  1000
 229
 230 //
 231 // ATAPILONGTIMEOUT is used for waiting read and
 232 // write operation timeout for ATAPI device
 233 //
 234
 235 //
 236 // 2 seconds
 237 //
 238 #define CDROMLONGTIMEOUT  2000
 239
 240 //
 241 // 5 seconds
 242 //
 243 #define ATAPILONGTIMEOUT  5000
 244
 245 //
 246 // ATA Commands Code
 247 //
 248 #define ATA_INITIALIZE_DEVICE 0x91
 249
 250 //
 251 // Class 1
 252 //
 253 #define IDENTIFY_DRIVE_CMD          0xec
 254 #define READ_BUFFER_CMD             0xe4
 255 #define READ_SECTORS_CMD            0x20
 256 #define READ_SECTORS_WITH_RETRY_CMD 0x21
 257 #define READ_LONG_CMD               0x22
 258 #define READ_LONG_WITH_RETRY_CMD    0x23
 259 //
 260 // Class 1 - Atapi6 enhanced commands
 261 //
 262 #define READ_SECTORS_EXT_CMD  0x24
 263
 264 //
 265 // Class 2
 266 //
 267 #define FORMAT_TRACK_CMD              0x50
 268 #define WRITE_BUFFER_CMD              0xe8
 269 #define WRITE_SECTORS_CMD             0x30
 270 #define WRITE_SECTORS_WITH_RETRY_CMD  0x31
 271 #define WRITE_LONG_CMD                0x32
 272 #define WRITE_LONG_WITH_RETRY_CMD     0x33
 273 #define WRITE_VERIFY_CMD              0x3c
 274 //
 275 // Class 2 - Atapi6 enhanced commands
 276 //
 277 #define WRITE_SECTORS_EXT_CMD 0x34
 278
 279 //
 280 // Class 3
 281 //
 282 #define ACK_MEDIA_CHANGE_CMD        0xdb
 283 #define BOOT_POST_BOOT_CMD          0xdc
 284 #define BOOT_PRE_BOOT_CMD           0xdd
 285 #define CHECK_POWER_MODE_CMD        0x98
 286 #define CHECK_POWER_MODE_CMD_ALIAS  0xe5
 287 #define DOOR_LOCK_CMD               0xde
 288 #define DOOR_UNLOCK_CMD             0xdf
 289 #define EXEC_DRIVE_DIAG_CMD         0x90
 290 #define IDLE_CMD_ALIAS              0x97
 291 #define IDLE_CMD                    0xe3
 292 #define IDLE_IMMEDIATE_CMD          0x95
 293 #define IDLE_IMMEDIATE_CMD_ALIAS    0xe1
 294 #define INIT_DRIVE_PARAM_CMD        0x91
 295 #define RECALIBRATE_CMD             0x10  /* aliased to 1x */
 296 #define READ_DRIVE_STATE_CMD        0xe9
 297 #define SET_MULTIPLE_MODE_CMD       0xC6
 298 #define READ_DRIVE_STATE_CMD        0xe9
 299 #define READ_VERIFY_CMD             0x40
 300 #define READ_VERIFY_WITH_RETRY_CMD  0x41
 301 #define SEEK_CMD                    0x70  /* aliased to 7x */
 302 #define SET_FEATURES_CMD            0xef
 303 #define STANDBY_CMD                 0x96
 304 #define STANDBY_CMD_ALIAS           0xe2
 305 #define STANDBY_IMMEDIATE_CMD       0x94
 306 #define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0
 307
 308 //
 309 // Class 4
 310 //
 311 #define READ_DMA_CMD              0xc8
 312 #define READ_DMA_WITH_RETRY_CMD   0xc9
 313 #define READ_DMA_EXT_CMD          0x25
 314 #define WRITE_DMA_CMD             0xca
 315 #define WRITE_DMA_WITH_RETRY_CMD  0xcb
 316 #define WRITE_DMA_EXT_CMD         0x35
 317
 318 //
 319 // Class 5
 320 //
 321 #define READ_MULTIPLE_CMD         0xc4
 322 #define REST_CMD                  0xe7
 323 #define RESTORE_DRIVE_STATE_CMD   0xea
 324 #define SET_SLEEP_MODE_CMD        0x99
 325 #define SET_SLEEP_MODE_CMD_ALIAS  0xe6
 326 #define WRITE_MULTIPLE_CMD        0xc5
 327 #define WRITE_SAME_CMD            0xe9
 328
 329 //
 330 // Class 6 - Host protected area access feature set
 331 //
 332 #define READ_NATIVE_MAX_ADDRESS_CMD 0xf8
 333 #define SET_MAX_ADDRESS_CMD         0xf9
 334
 335 //
 336 // Class 6 - ATA/ATAPI-6 enhanced commands
 337 //
 338 #define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27
 339 #define SET_MAX_ADDRESS_CMD_EXT         0x37
 340
 341 //
 342 // Class 6 - SET_MAX related sub command (in feature register)
 343 //
 344 #define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00
 345 #define PARTIES_SET_PASSWORD_SUB_CMD    0x01
 346 #define PARTIES_LOCK_SUB_CMD            0x02
 347 #define PARTIES_UNLOCK_SUB_CMD          0x03
 348 #define PARTIES_FREEZE_SUB_CMD          0x04
 349
 350 //
 351 // S.M.A.R.T
 352 //
 353 #define ATA_SMART_CMD               0xb0
 354 #define ATA_CONSTANT_C2             0xc2
 355 #define ATA_CONSTANT_4F             0x4f
 356 #define ATA_SMART_ENABLE_OPERATION  0xd8
 357 #define ATA_SMART_RETURN_STATUS     0xda
 358
 359 //
 360 // Error codes for Exec Drive Diag
 361 //
 362 #define DRIV_DIAG_NO_ERROR          (0x01)
 363 #define DRIV_DIAG_FORMATTER_ERROR   (0x02)
 364 #define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)
 365 #define DRIV_DIAG_ECC_CKT_ERRROR    (0x04)
 366 #define DRIV_DIAG_UP_ERROR          (0x05)
 367 #define DRIV_DIAG_SLAVE_DRV_ERROR   (0x80)  /* aliased to 0x8x */
 368
 369 //
 370 // Codes for Format Track
 371 //
 372 #define FORMAT_GOOD_SECTOR            (0x00)
 373 #define FORMAT_SUSPEND_ALLOC          (0x01)
 374 #define FORMAT_REALLOC_SECTOR         (0x02)
 375 #define FORMAT_MARK_SECTOR_DEFECTIVE  (0x03)
 376
 377 //
 378 // IDE_IDENTIFY bits
 379 // config bits :
 380 //
 381 #define ID_CONFIG_RESERVED0                             bit0
 382 #define ID_CONFIG_HARD_SECTORED_DRIVE                   bit1
 383 #define ID_CONFIG_SOFT_SECTORED_DRIVE                   bit2
 384 #define ID_CONFIG_NON_MFM                               bit3
 385 #define ID_CONFIG_15uS_HEAD_SWITCHING                   bit4
 386 #define ID_CONFIG_SPINDLE_MOTOR_CONTROL                 bit5
 387 #define ID_CONFIG_HARD_DRIVE                            bit6
 388 #define ID_CONFIG_CHANGEABLE_MEDIUM                     bit7
 389 #define ID_CONFIG_DATA_RATE_TO_5MHZ                     bit8
 390 #define ID_CONFIG_DATA_RATE_5_TO_10MHZ                  bit9
 391 #define ID_CONFIG_DATA_RATE_ABOVE_10MHZ                 bit10
 392 #define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC  bit11
 393 #define ID_CONFIG_DATA_CLK_OFFSET_AVAIL                 bit12
 394 #define ID_CONFIG_TRACK_OFFSET_AVAIL                    bit13
 395 #define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY         bit14
 396 #define ID_CONFIG_RESERVED1                             bit15
 397
 398 #define ID_DOUBLE_WORD_IO_POSSIBLE                      bit01
 399 #define ID_LBA_SUPPORTED                                bit9
 400 #define ID_DMA_SUPPORTED                                bit8
 401
 402 #define SET_FEATURE_ENABLE_8BIT_TRANSFER                (0x01)
 403 #define SET_FEATURE_ENABLE_WRITE_CACHE                  (0x02)
 404 #define SET_FEATURE_TRANSFER_MODE                       (0x03)
 405 #define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA      (0x22)
 406 #define SET_FEATURE_DISABLE_RETRIES                     (0x33)
 407 //
 408 // for Read & Write Longs
 409 //
 410 #define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH                          (0x44)
 411 #define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG     (0x54)
 412 #define SET_FEATURE_DISABLE_READ_AHEAD                              (0x55)
 413 #define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET                      (0x66)
 414 #define SET_FEATURE_DISABLE_ECC                                     (0x77)
 415 #define SET_FEATURE_DISABLE_8BIT_TRANSFER                           (0x81)
 416 #define SET_FEATURE_DISABLE_WRITE_CACHE                             (0x82)
 417 #define SET_FEATURE_ENABLE_ECC                                      (0x88)
 418 #define SET_FEATURE_ENABLE_RETRIES                                  (0x99)
 419 #define SET_FEATURE_ENABLE_READ_AHEAD                               (0xaa)
 420 #define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS  (0xab)
 421 #define SET_FEATURE_ALLOW_REST_MODE                                 (0xac)
 422 //
 423 // for Read & Write Longs
 424 //
 425 #define SET_FEATURE_4BYTE_ECC                           (0xbb)
 426 #define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET  (0xcc)
 427 #define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM   (0xdd)
 428
 429 #define BLOCK_TRANSFER_MODE                             (0x00)
 430 #define SINGLE_WORD_DMA_TRANSFER_MODE                   (0x10)
 431 #define MULTI_WORD_DMA_TRANSFER_MODE                    (0x20)
 432 #define TRANSFER_MODE_MASK                              (0x07)  // 3 LSBs
 433
 434 //
 435 // Drive 0 - Head 0
 436 //
 437 #define DEFAULT_DRIVE (0x00)
 438 #define DEFAULT_CMD   (0xa0)
 439 //
 440 // default content of device control register, disable INT
 441 //
 442 #define DEFAULT_CTL                 (0x0a)
 443 #define DEFAULT_IDE_BM_IO_BASE_ADR  (0xffa0)
 444
 445 //
 446 // ATAPI6 related data structure definition
 447 //
 448
 449 //
 450 // The maximum sectors count in 28 bit addressing mode
 451 //
 452 #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
 453
 454 //
 455 // Move the IDENTIFY section to DXE\Protocol\IdeControllerInit
 456 //
 457
 458 //
 459 // ATAPI Command
 460 //
 461 #define ATAPI_SOFT_RESET_CMD      0x08
 462 #define ATAPI_PACKET_CMD          0xA0
 463 #define PACKET_CMD                0xA0
 464 #define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
 465 #define ATAPI_SERVICE_CMD         0xA2
 466
 467 //
 468 // ATAPI Packet Command
 469 //
 470 #pragma pack(1)
 471
 472 typedef struct {
 473   UINT8 opcode;
 474   UINT8 reserved_1;
 475   UINT8 reserved_2;
 476   UINT8 reserved_3;
 477   UINT8 reserved_4;
 478   UINT8 reserved_5;
 479   UINT8 reserved_6;
 480   UINT8 reserved_7;
 481   UINT8 reserved_8;
 482   UINT8 reserved_9;
 483   UINT8 reserved_10;
 484   UINT8 reserved_11;
 485 } TEST_UNIT_READY_CMD;
 486
 487 typedef struct {
 488   UINT8 opcode;
 489   UINT8 reserved_1 : 4;
 490   UINT8 lun : 4;
 491   UINT8 page_code;
 492   UINT8 reserved_3;
 493   UINT8 allocation_length;
 494   UINT8 reserved_5;
 495   UINT8 reserved_6;
 496   UINT8 reserved_7;
 497   UINT8 reserved_8;
 498   UINT8 reserved_9;
 499   UINT8 reserved_10;
 500   UINT8 reserved_11;
 501 } INQUIRY_CMD;
 502
 503 typedef struct {
 504   UINT8 opcode;
 505   UINT8 reserved_1 : 4;
 506   UINT8 lun : 4;
 507   UINT8 reserved_2;
 508   UINT8 reserved_3;
 509   UINT8 allocation_length;
 510   UINT8 reserved_5;
 511   UINT8 reserved_6;
 512   UINT8 reserved_7;
 513   UINT8 reserved_8;
 514   UINT8 reserved_9;
 515   UINT8 reserved_10;
 516   UINT8 reserved_11;
 517 } REQUEST_SENSE_CMD;
 518
 519 typedef struct {
 520   UINT8 opcode;
 521   UINT8 reserved_1 : 4;
 522   UINT8 lun : 4;
 523   UINT8 page_code : 4;
 524   UINT8 page_control : 4;
 525   UINT8 reserved_3;
 526   UINT8 reserved_4;
 527   UINT8 reserved_5;
 528   UINT8 reserved_6;
 529   UINT8 parameter_list_length_hi;
 530   UINT8 parameter_list_length_lo;
 531   UINT8 reserved_9;
 532   UINT8 reserved_10;
 533   UINT8 reserved_11;
 534 } MODE_SENSE_CMD;
 535
 536 typedef struct {
 537   UINT8 opcode;
 538   UINT8 reserved_1 : 5;
 539   UINT8 lun : 3;
 540   UINT8 Lba0;
 541   UINT8 Lba1;
 542   UINT8 Lba2;
 543   UINT8 Lba3;
 544   UINT8 reserved_6;
 545   UINT8 TranLen0;
 546   UINT8 TranLen1;
 547   UINT8 reserved_9;
 548   UINT8 reserved_10;
 549   UINT8 reserved_11;
 550 } READ10_CMD;
 551
 552 typedef struct {
 553   UINT8 opcode;
 554   UINT8 reserved_1;
 555   UINT8 reserved_2;
 556   UINT8 reserved_3;
 557   UINT8 reserved_4;
 558   UINT8 reserved_5;
 559   UINT8 reserved_6;
 560   UINT8 allocation_length_hi;
 561   UINT8 allocation_length_lo;
 562   UINT8 reserved_9;
 563   UINT8 reserved_10;
 564   UINT8 reserved_11;
 565 } READ_FORMAT_CAP_CMD;
 566
 567 typedef union {
 568   UINT16              Data16[6];
 569   TEST_UNIT_READY_CMD TestUnitReady;
 570   READ10_CMD          Read10;
 571   REQUEST_SENSE_CMD   RequestSence;
 572   INQUIRY_CMD         Inquiry;
 573   MODE_SENSE_CMD      ModeSense;
 574   READ_FORMAT_CAP_CMD ReadFormatCapacity;
 575 } ATAPI_PACKET_COMMAND;
 576
 577 typedef struct {
 578   UINT32  RegionBaseAddr;
 579   UINT16  ByteCount;
 580   UINT16  EndOfTable;
 581 } IDE_DMA_PRD;
 582
 583 #define MAX_DMA_EXT_COMMAND_SECTORS 0x10000
 584 #define MAX_DMA_COMMAND_SECTORS     0x100
 585
 586 #pragma pack()
 587
 588 //
 589 // Packet Command Code
 590 //
 591 #define TEST_UNIT_READY             0x00
 592 #define REZERO                      0x01
 593 #define REQUEST_SENSE               0x03
 594 #define FORMAT_UNIT                 0x04
 595 #define REASSIGN_BLOCKS             0x07
 596 #define INQUIRY                     0x12
 597 #define START_STOP_UNIT             0x1B
 598 #define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E
 599 #define READ_FORMAT_CAPACITY        0x23
 600 #define OLD_FORMAT_UNIT             0x24
 601 #define READ_CAPACITY               0x25
 602 #define READ_10                     0x28
 603 #define WRITE_10                    0x2A
 604 #define SEEK                        0x2B
 605 #define SEND_DIAGNOSTICS            0x3D
 606 #define WRITE_VERIFY                0x2E
 607 #define VERIFY                      0x2F
 608 #define READ_DEFECT_DATA            0x37
 609 #define WRITE_BUFFER                0x38
 610 #define READ_BUFFER                 0x3C
 611 #define READ_LONG                   0x3E
 612 #define WRITE_LONG                  0x3F
 613 #define MODE_SELECT                 0x55
 614 #define MODE_SENSE                  0x5A
 615 #define READ_12                     0xA8
 616 #define WRITE_12                    0xAA
 617 #define MAX_ATAPI_BYTE_COUNT        (0xfffe)
 618
 619 //
 620 // Sense Key
 621 //
 622 #define REQUEST_SENSE_ERROR (0x70)
 623 #define SK_NO_SENSE         (0x0)
 624 #define SK_RECOVERY_ERROR   (0x1)
 625 #define SK_NOT_READY        (0x2)
 626 #define SK_MEDIUM_ERROR     (0x3)
 627 #define SK_HARDWARE_ERROR   (0x4)
 628 #define SK_ILLEGAL_REQUEST  (0x5)
 629 #define SK_UNIT_ATTENTION   (0x6)
 630 #define SK_DATA_PROTECT     (0x7)
 631 #define SK_BLANK_CHECK      (0x8)
 632 #define SK_VENDOR_SPECIFIC  (0x9)
 633 #define SK_RESERVED_A       (0xA)
 634 #define SK_ABORT            (0xB)
 635 #define SK_RESERVED_C       (0xC)
 636 #define SK_OVERFLOW         (0xD)
 637 #define SK_MISCOMPARE       (0xE)
 638 #define SK_RESERVED_F       (0xF)
 639
 640 //
 641 // Additional Sense Codes
 642 //
 643 #define ASC_NOT_READY                   (0x04)
 644 #define ASC_MEDIA_ERR1                  (0x10)
 645 #define ASC_MEDIA_ERR2                  (0x11)
 646 #define ASC_MEDIA_ERR3                  (0x14)
 647 #define ASC_MEDIA_ERR4                  (0x30)
 648 #define ASC_MEDIA_UPSIDE_DOWN           (0x06)
 649 #define ASC_INVALID_CMD                 (0x20)
 650 #define ASC_LBA_OUT_OF_RANGE            (0x21)
 651 #define ASC_INVALID_FIELD               (0x24)
 652 #define ASC_WRITE_PROTECTED             (0x27)
 653 #define ASC_MEDIA_CHANGE                (0x28)
 654 #define ASC_RESET                       (0x29)  /* Power On Reset or Bus Reset occurred */
 655 #define ASC_ILLEGAL_FIELD               (0x26)
 656 #define ASC_NO_MEDIA                    (0x3A)
 657 #define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
 658
 659 //
 660 // Additional Sense Code Qualifier
 661 //
 662 #define ASCQ_IN_PROGRESS  (0x01)
 663
 664 #define SETFEATURE        TRUE
 665 #define CLEARFEATURE      FALSE
 666
 667 //
 668 //  ATAPI Data structure
 669 //
 670 #pragma pack(1)
 671
 672 typedef struct {
 673   UINT8 peripheral_type;
 674   UINT8 RMB;
 675   UINT8 version;
 676   UINT8 response_data_format;
 677   UINT8 addnl_length;
 678   UINT8 reserved_5;
 679   UINT8 reserved_6;
 680   UINT8 reserved_7;
 681   UINT8 vendor_info[8];
 682   UINT8 product_id[12];
 683   UINT8 eeprom_product_code[4];
 684   UINT8 firmware_rev_level[4];
 685   UINT8 firmware_sub_rev_level[1];
 686   UINT8 reserved_37;
 687   UINT8 reserved_38;
 688   UINT8 reserved_39;
 689   UINT8 max_capacity_hi;
 690   UINT8 max_capacity_mid;
 691   UINT8 max_capacity_lo;
 692   UINT8 reserved_43_95[95 - 43 + 1];
 693 } INQUIRY_DATA;
 694
 695 typedef struct {
 696   UINT8 peripheral_type;
 697   UINT8 RMB;
 698   UINT8 version;
 699   UINT8 response_data_format;
 700   UINT8 addnl_length;
 701   UINT8 reserved_5;
 702   UINT8 reserved_6;
 703   UINT8 reserved_7;
 704   UINT8 vendor_info[8];
 705   UINT8 product_id[16];
 706   UINT8 product_revision_level[4];
 707   UINT8 vendor_specific[20];
 708   UINT8 reserved_56_95[40];
 709 } CDROM_INQUIRY_DATA;
 710
 711 typedef struct {
 712   UINT8 error_code : 7;
 713   UINT8 valid : 1;
 714   UINT8 reserved_1;
 715   UINT8 sense_key : 4;
 716   UINT8 reserved_21 : 1;
 717   UINT8 ILI : 1;
 718   UINT8 reserved_22 : 2;
 719   UINT8 vendor_specific_3;
 720   UINT8 vendor_specific_4;
 721   UINT8 vendor_specific_5;
 722   UINT8 vendor_specific_6;
 723   UINT8 addnl_sense_length;           // n - 7
 724   UINT8 vendor_specific_8;
 725   UINT8 vendor_specific_9;
 726   UINT8 vendor_specific_10;
 727   UINT8 vendor_specific_11;
 728   UINT8 addnl_sense_code;             // mandatory
 729   UINT8 addnl_sense_code_qualifier;   // mandatory
 730   UINT8 field_replaceable_unit_code;  // optional
 731   UINT8 reserved_15;
 732   UINT8 reserved_16;
 733   UINT8 reserved_17;
 734   //
 735   // Followed by additional sense bytes     : FIXME
 736   //
 737 } REQUEST_SENSE_DATA;
 738
 739 typedef struct {
 740   UINT8 LastLba3;
 741   UINT8 LastLba2;
 742   UINT8 LastLba1;
 743   UINT8 LastLba0;
 744   UINT8 BlockSize3;
 745   UINT8 BlockSize2;
 746   UINT8 BlockSize1;
 747   UINT8 BlockSize0;
 748 } READ_CAPACITY_DATA;
 749
 750 typedef struct {
 751   UINT8 reserved_0;
 752   UINT8 reserved_1;
 753   UINT8 reserved_2;
 754   UINT8 Capacity_Length;
 755   UINT8 LastLba3;
 756   UINT8 LastLba2;
 757   UINT8 LastLba1;
 758   UINT8 LastLba0;
 759   UINT8 DesCode : 2;
 760   UINT8 reserved_9 : 6;
 761   UINT8 BlockSize2;
 762   UINT8 BlockSize1;
 763   UINT8 BlockSize0;
 764 } READ_FORMAT_CAPACITY_DATA;
 765
 766 #pragma pack()
 767
 768 //
 769 // PIO mode definition
 770 //
 771 typedef enum {
 772   ATA_PIO_MODE_BELOW_2,
 773   ATA_PIO_MODE_2,
 774   ATA_PIO_MODE_3,
 775   ATA_PIO_MODE_4
 776 } ATA_PIO_MODE;
 777
 778 //
 779 // Multi word DMA definition
 780 //
 781 typedef enum {
 782   ATA_MDMA_MODE_0,
 783   ATA_MDMA_MODE_1,
 784   ATA_MDMA_MODE_2
 785 } ATA_MDMA_MODE;
 786
 787 //
 788 // UDMA mode definition
 789 //
 790 typedef enum {
 791   ATA_UDMA_MODE_0,
 792   ATA_UDMA_MODE_1,
 793   ATA_UDMA_MODE_2,
 794   ATA_UDMA_MODE_3,
 795   ATA_UDMA_MODE_4,
 796   ATA_UDMA_MODE_5
 797 } ATA_UDMA_MODE;
 798
 799 #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
 800 #define ATA_MODE_CATEGORY_FLOW_PIO    0x01
 801 #define ATA_MODE_CATEGORY_MDMA        0x04
 802 #define ATA_MODE_CATEGORY_UDMA        0x08
 803
 804 #pragma pack(1)
 805
 806 typedef struct {
 807   UINT8 ModeNumber : 3;
 808   UINT8 ModeCategory : 5;
 809 } ATA_TRANSFER_MODE;
 810
 811 typedef struct {
 812   UINT8 Sector;
 813   UINT8 Heads;
 814   UINT8 MultipleSector;
 815 } ATA_DRIVE_PARMS;
 816
 817 #pragma pack()
 818 //
 819 // IORDY Sample Point field value
 820 //
 821 #define ISP_5_CLK 0
 822 #define ISP_4_CLK 1
 823 #define ISP_3_CLK 2
 824 #define ISP_2_CLK 3
 825
 826 //
 827 // Recovery Time field value
 828 //
 829 #define RECVY_4_CLK 0
 830 #define RECVY_3_CLK 1
 831 #define RECVY_2_CLK 2
 832 #define RECVY_1_CLK 3
 833
 834 //
 835 // Slave IDE Timing Register Enable
 836 //
 837 #define SITRE bit14
 838
 839 //
 840 // DMA Timing Enable Only Select 1
 841 //
 842 #define DTE1  bit7
 843
 844 //
 845 // Pre-fetch and Posting Enable Select 1
 846 //
 847 #define PPE1  bit6
 848
 849 //
 850 // IORDY Sample Point Enable Select 1
 851 //
 852 #define IE1 bit5
 853
 854 //
 855 // Fast Timing Bank Drive Select 1
 856 //
 857 #define TIME1 bit4
 858
 859 //
 860 // DMA Timing Enable Only Select 0
 861 //
 862 #define DTE0  bit3
 863
 864 //
 865 // Pre-fetch and Posting Enable Select 0
 866 //
 867 #define PPE0  bit2
 868
 869 //
 870 // IOREY Sample Point Enable Select 0
 871 //
 872 #define IE0 bit1
 873
 874 //
 875 // Fast Timing Bank Drive Select 0
 876 //
 877 #define TIME0 bit0
 878
 879 #endif