ec088dcfa6356b968d36f6d3e0cd4eb4ef5a93d8
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / IdeBus / Dxe / idedata.h
1 /** @file
2 Header file for IDE Bus Driver's Data Structures
3
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef _IDE_DATA_H
16 #define _IDE_DATA_H
17
18 //
19 // bit definition
20 //
21 #define bit0 (1 << 0)
22 #define bit1 (1 << 1)
23 #define bit2 (1 << 2)
24 #define bit3 (1 << 3)
25 #define bit4 (1 << 4)
26 #define bit5 (1 << 5)
27 #define bit6 (1 << 6)
28 #define bit7 (1 << 7)
29 #define bit8 (1 << 8)
30 #define bit9 (1 << 9)
31 #define bit10 (1 << 10)
32 #define bit11 (1 << 11)
33 #define bit12 (1 << 12)
34 #define bit13 (1 << 13)
35 #define bit14 (1 << 14)
36 #define bit15 (1 << 15)
37 #define bit16 (1 << 16)
38 #define bit17 (1 << 17)
39 #define bit18 (1 << 18)
40 #define bit19 (1 << 19)
41 #define bit20 (1 << 20)
42 #define bit21 (1 << 21)
43 #define bit22 (1 << 22)
44 #define bit23 (1 << 23)
45 #define bit24 (1 << 24)
46 #define bit25 (1 << 25)
47 #define bit26 (1 << 26)
48 #define bit27 (1 << 27)
49 #define bit28 (1 << 28)
50 #define bit29 (1 << 29)
51 #define bit30 (1 << 30)
52 #define bit31 (1 << 31)
53
54 //
55 // common constants
56 //
57 #define STALL_1_MILLI_SECOND 1000 // stall 1 ms
58 #define STALL_1_SECOND 1000000 // stall 1 second
59 typedef enum {
60 IdePrimary = 0,
61 IdeSecondary = 1,
62 IdeMaxChannel = 2
63 } EFI_IDE_CHANNEL;
64
65 typedef enum {
66 IdeMaster = 0,
67 IdeSlave = 1,
68 IdeMaxDevice = 2
69 } EFI_IDE_DEVICE;
70
71 typedef enum {
72 IdeMagnetic, /* ZIP Drive or LS120 Floppy Drive */
73 IdeCdRom, /* ATAPI CDROM */
74 IdeHardDisk, /* Hard Disk */
75 Ide48bitAddressingHardDisk, /* Hard Disk larger than 120GB */
76 IdeUnknown
77 } IDE_DEVICE_TYPE;
78
79 typedef enum {
80 SenseNoSenseKey,
81 SenseDeviceNotReadyNoRetry,
82 SenseDeviceNotReadyNeedRetry,
83 SenseNoMedia,
84 SenseMediaChange,
85 SenseMediaError,
86 SenseOtherSense
87 } SENSE_RESULT;
88
89 //
90 // IDE Registers
91 //
92 typedef union {
93 UINT16 Command; /* when write */
94 UINT16 Status; /* when read */
95 } IDE_CMD_OR_STATUS;
96
97 typedef union {
98 UINT16 Error; /* when read */
99 UINT16 Feature; /* when write */
100 } IDE_ERROR_OR_FEATURE;
101
102 typedef union {
103 UINT16 AltStatus; /* when read */
104 UINT16 DeviceControl; /* when write */
105 } IDE_AltStatus_OR_DeviceControl;
106
107 //
108 // IDE registers set
109 //
110 typedef struct {
111 UINT16 Data;
112 IDE_ERROR_OR_FEATURE Reg1;
113 UINT16 SectorCount;
114 UINT16 SectorNumber;
115 UINT16 CylinderLsb;
116 UINT16 CylinderMsb;
117 UINT16 Head;
118 IDE_CMD_OR_STATUS Reg;
119
120 IDE_AltStatus_OR_DeviceControl Alt;
121 UINT16 DriveAddress;
122
123 UINT16 MasterSlave;
124 UINT16 BusMasterBaseAddr;
125 } IDE_BASE_REGISTERS;
126
127 //
128 // IDE registers' base addresses
129 //
130 typedef struct {
131 UINT16 CommandBlockBaseAddr;
132 UINT16 ControlBlockBaseAddr;
133 UINT16 BusMasterBaseAddr;
134 } IDE_REGISTERS_BASE_ADDR;
135
136 //
137 // Bit definitions in Programming Interface byte of the Class Code field
138 // in PCI IDE controller's Configuration Space
139 //
140 #define IDE_PRIMARY_OPERATING_MODE bit0
141 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR bit1
142 #define IDE_SECONDARY_OPERATING_MODE bit2
143 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR bit3
144
145 //
146 // IDE registers bit definitions
147 //
148
149 //
150 // Err Reg
151 //
152 #define BBK_ERR bit7 /* Bad block detected */
153 #define UNC_ERR bit6 /* Uncorrectable Data */
154 #define MC_ERR bit5 /* Media Change */
155 #define IDNF_ERR bit4 /* ID Not Found */
156 #define MCR_ERR bit3 /* Media Change Requested */
157 #define ABRT_ERR bit2 /* Aborted Command */
158 #define TK0NF_ERR bit1 /* Track 0 Not Found */
159 #define AMNF_ERR bit0 /* Address Mark Not Found */
160
161 //
162 // Device/Head Reg
163 //
164 #define LBA_MODE bit6
165 #define DEV bit4
166 #define HS3 bit3
167 #define HS2 bit2
168 #define HS1 bit1
169 #define HS0 bit0
170 #define CHS_MODE (0)
171 #define DRV0 (0)
172 #define DRV1 (1)
173 #define MST_DRV DRV0
174 #define SLV_DRV DRV1
175
176 //
177 // Status Reg
178 //
179 #define BSY bit7 /* Controller Busy */
180 #define DRDY bit6 /* Drive Ready */
181 #define DWF bit5 /* Drive Write Fault */
182 #define DSC bit4 /* Disk Seek Complete */
183 #define DRQ bit3 /* Data Request */
184 #define CORR bit2 /* Corrected Data */
185 #define IDX bit1 /* Index */
186 #define ERR bit0 /* Error */
187
188 //
189 // Device Control Reg
190 //
191 #define SRST bit2 /* Software Reset */
192 #define IEN_L bit1 /* Interrupt Enable #*/
193
194 //
195 // Bus Master Reg
196 //
197 #define BMIC_nREAD bit3
198 #define BMIC_START bit0
199 #define BMIS_INTERRUPT bit2
200 #define BMIS_ERROR bit1
201
202 #define BMICP_OFFSET 0x00
203 #define BMISP_OFFSET 0x02
204 #define BMIDP_OFFSET 0x04
205 #define BMICS_OFFSET 0x08
206 #define BMISS_OFFSET 0x0A
207 #define BMIDS_OFFSET 0x0C
208
209 //
210 // Time Out Value For IDE Device Polling
211 //
212
213 //
214 // ATATIMEOUT is used for waiting time out for ATA device
215 //
216
217 //
218 // 1 second
219 //
220 #define ATATIMEOUT 1000
221
222 //
223 // ATAPITIMEOUT is used for waiting operation
224 // except read and write time out for ATAPI device
225 //
226
227 //
228 // 1 second
229 //
230 #define ATAPITIMEOUT 1000
231
232 //
233 // ATAPILONGTIMEOUT is used for waiting read and
234 // write operation timeout for ATAPI device
235 //
236
237 //
238 // 2 seconds
239 //
240 #define CDROMLONGTIMEOUT 2000
241
242 //
243 // 5 seconds
244 //
245 #define ATAPILONGTIMEOUT 5000
246
247 //
248 // 10 seconds
249 //
250 #define ATASMARTTIMEOUT 10000
251
252 //
253 // ATA Commands Code
254 //
255 #define ATA_INITIALIZE_DEVICE 0x91
256
257 //
258 // Class 1
259 //
260 #define IDENTIFY_DRIVE_CMD 0xec
261 #define READ_BUFFER_CMD 0xe4
262 #define READ_SECTORS_CMD 0x20
263 #define READ_SECTORS_WITH_RETRY_CMD 0x21
264 #define READ_LONG_CMD 0x22
265 #define READ_LONG_WITH_RETRY_CMD 0x23
266 //
267 // Class 1 - Atapi6 enhanced commands
268 //
269 #define READ_SECTORS_EXT_CMD 0x24
270
271 //
272 // Class 2
273 //
274 #define FORMAT_TRACK_CMD 0x50
275 #define WRITE_BUFFER_CMD 0xe8
276 #define WRITE_SECTORS_CMD 0x30
277 #define WRITE_SECTORS_WITH_RETRY_CMD 0x31
278 #define WRITE_LONG_CMD 0x32
279 #define WRITE_LONG_WITH_RETRY_CMD 0x33
280 #define WRITE_VERIFY_CMD 0x3c
281 //
282 // Class 2 - Atapi6 enhanced commands
283 //
284 #define WRITE_SECTORS_EXT_CMD 0x34
285
286 //
287 // Class 3
288 //
289 #define ACK_MEDIA_CHANGE_CMD 0xdb
290 #define BOOT_POST_BOOT_CMD 0xdc
291 #define BOOT_PRE_BOOT_CMD 0xdd
292 #define CHECK_POWER_MODE_CMD 0x98
293 #define CHECK_POWER_MODE_CMD_ALIAS 0xe5
294 #define DOOR_LOCK_CMD 0xde
295 #define DOOR_UNLOCK_CMD 0xdf
296 #define EXEC_DRIVE_DIAG_CMD 0x90
297 #define IDLE_CMD_ALIAS 0x97
298 #define IDLE_CMD 0xe3
299 #define IDLE_IMMEDIATE_CMD 0x95
300 #define IDLE_IMMEDIATE_CMD_ALIAS 0xe1
301 #define INIT_DRIVE_PARAM_CMD 0x91
302 #define RECALIBRATE_CMD 0x10 /* aliased to 1x */
303 #define READ_DRIVE_STATE_CMD 0xe9
304 #define SET_MULTIPLE_MODE_CMD 0xC6
305 #define READ_DRIVE_STATE_CMD 0xe9
306 #define READ_VERIFY_CMD 0x40
307 #define READ_VERIFY_WITH_RETRY_CMD 0x41
308 #define SEEK_CMD 0x70 /* aliased to 7x */
309 #define SET_FEATURES_CMD 0xef
310 #define STANDBY_CMD 0x96
311 #define STANDBY_CMD_ALIAS 0xe2
312 #define STANDBY_IMMEDIATE_CMD 0x94
313 #define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0
314
315 //
316 // Class 4
317 //
318 #define READ_DMA_CMD 0xc8
319 #define READ_DMA_WITH_RETRY_CMD 0xc9
320 #define READ_DMA_EXT_CMD 0x25
321 #define WRITE_DMA_CMD 0xca
322 #define WRITE_DMA_WITH_RETRY_CMD 0xcb
323 #define WRITE_DMA_EXT_CMD 0x35
324
325 //
326 // Class 5
327 //
328 #define READ_MULTIPLE_CMD 0xc4
329 #define REST_CMD 0xe7
330 #define RESTORE_DRIVE_STATE_CMD 0xea
331 #define SET_SLEEP_MODE_CMD 0x99
332 #define SET_SLEEP_MODE_CMD_ALIAS 0xe6
333 #define WRITE_MULTIPLE_CMD 0xc5
334 #define WRITE_SAME_CMD 0xe9
335
336 //
337 // Class 6 - Host protected area access feature set
338 //
339 #define READ_NATIVE_MAX_ADDRESS_CMD 0xf8
340 #define SET_MAX_ADDRESS_CMD 0xf9
341
342 //
343 // Class 6 - ATA/ATAPI-6 enhanced commands
344 //
345 #define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27
346 #define SET_MAX_ADDRESS_CMD_EXT 0x37
347
348 //
349 // Class 6 - SET_MAX related sub command (in feature register)
350 //
351 #define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00
352 #define PARTIES_SET_PASSWORD_SUB_CMD 0x01
353 #define PARTIES_LOCK_SUB_CMD 0x02
354 #define PARTIES_UNLOCK_SUB_CMD 0x03
355 #define PARTIES_FREEZE_SUB_CMD 0x04
356
357 //
358 // S.M.A.R.T
359 //
360 #define ATA_SMART_CMD 0xb0
361 #define ATA_CONSTANT_C2 0xc2
362 #define ATA_CONSTANT_4F 0x4f
363 #define ATA_SMART_ENABLE_OPERATION 0xd8
364 #define ATA_SMART_RETURN_STATUS 0xda
365
366 //
367 // Error codes for Exec Drive Diag
368 //
369 #define DRIV_DIAG_NO_ERROR (0x01)
370 #define DRIV_DIAG_FORMATTER_ERROR (0x02)
371 #define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)
372 #define DRIV_DIAG_ECC_CKT_ERRROR (0x04)
373 #define DRIV_DIAG_UP_ERROR (0x05)
374 #define DRIV_DIAG_SLAVE_DRV_ERROR (0x80) /* aliased to 0x8x */
375
376 //
377 // Codes for Format Track
378 //
379 #define FORMAT_GOOD_SECTOR (0x00)
380 #define FORMAT_SUSPEND_ALLOC (0x01)
381 #define FORMAT_REALLOC_SECTOR (0x02)
382 #define FORMAT_MARK_SECTOR_DEFECTIVE (0x03)
383
384 //
385 // IDE_IDENTIFY bits
386 // config bits :
387 //
388 #define ID_CONFIG_RESERVED0 bit0
389 #define ID_CONFIG_HARD_SECTORED_DRIVE bit1
390 #define ID_CONFIG_SOFT_SECTORED_DRIVE bit2
391 #define ID_CONFIG_NON_MFM bit3
392 #define ID_CONFIG_15uS_HEAD_SWITCHING bit4
393 #define ID_CONFIG_SPINDLE_MOTOR_CONTROL bit5
394 #define ID_CONFIG_HARD_DRIVE bit6
395 #define ID_CONFIG_CHANGEABLE_MEDIUM bit7
396 #define ID_CONFIG_DATA_RATE_TO_5MHZ bit8
397 #define ID_CONFIG_DATA_RATE_5_TO_10MHZ bit9
398 #define ID_CONFIG_DATA_RATE_ABOVE_10MHZ bit10
399 #define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC bit11
400 #define ID_CONFIG_DATA_CLK_OFFSET_AVAIL bit12
401 #define ID_CONFIG_TRACK_OFFSET_AVAIL bit13
402 #define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY bit14
403 #define ID_CONFIG_RESERVED1 bit15
404
405 #define ID_DOUBLE_WORD_IO_POSSIBLE bit01
406 #define ID_LBA_SUPPORTED bit9
407 #define ID_DMA_SUPPORTED bit8
408
409 #define SET_FEATURE_ENABLE_8BIT_TRANSFER (0x01)
410 #define SET_FEATURE_ENABLE_WRITE_CACHE (0x02)
411 #define SET_FEATURE_TRANSFER_MODE (0x03)
412 #define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA (0x22)
413 #define SET_FEATURE_DISABLE_RETRIES (0x33)
414 //
415 // for Read & Write Longs
416 //
417 #define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH (0x44)
418 #define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG (0x54)
419 #define SET_FEATURE_DISABLE_READ_AHEAD (0x55)
420 #define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET (0x66)
421 #define SET_FEATURE_DISABLE_ECC (0x77)
422 #define SET_FEATURE_DISABLE_8BIT_TRANSFER (0x81)
423 #define SET_FEATURE_DISABLE_WRITE_CACHE (0x82)
424 #define SET_FEATURE_ENABLE_ECC (0x88)
425 #define SET_FEATURE_ENABLE_RETRIES (0x99)
426 #define SET_FEATURE_ENABLE_READ_AHEAD (0xaa)
427 #define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS (0xab)
428 #define SET_FEATURE_ALLOW_REST_MODE (0xac)
429 //
430 // for Read & Write Longs
431 //
432 #define SET_FEATURE_4BYTE_ECC (0xbb)
433 #define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET (0xcc)
434 #define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM (0xdd)
435
436 #define BLOCK_TRANSFER_MODE (0x00)
437 #define SINGLE_WORD_DMA_TRANSFER_MODE (0x10)
438 #define MULTI_WORD_DMA_TRANSFER_MODE (0x20)
439 #define TRANSFER_MODE_MASK (0x07) // 3 LSBs
440
441 //
442 // Drive 0 - Head 0
443 //
444 #define DEFAULT_DRIVE (0x00)
445 #define DEFAULT_CMD (0xa0)
446 //
447 // default content of device control register, disable INT
448 //
449 #define DEFAULT_CTL (0x0a)
450 #define DEFAULT_IDE_BM_IO_BASE_ADR (0xffa0)
451
452 //
453 // ATAPI6 related data structure definition
454 //
455
456 //
457 // The maximum sectors count in 28 bit addressing mode
458 //
459 #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
460
461 //
462 // Move the IDENTIFY section to DXE\Protocol\IdeControllerInit
463 //
464
465 //
466 // ATAPI Command
467 //
468 #define ATAPI_SOFT_RESET_CMD 0x08
469 #define ATAPI_PACKET_CMD 0xA0
470 #define PACKET_CMD 0xA0
471 #define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
472 #define ATAPI_SERVICE_CMD 0xA2
473
474 //
475 // ATAPI Packet Command
476 //
477 #pragma pack(1)
478
479 typedef struct {
480 UINT8 opcode;
481 UINT8 reserved_1;
482 UINT8 reserved_2;
483 UINT8 reserved_3;
484 UINT8 reserved_4;
485 UINT8 reserved_5;
486 UINT8 reserved_6;
487 UINT8 reserved_7;
488 UINT8 reserved_8;
489 UINT8 reserved_9;
490 UINT8 reserved_10;
491 UINT8 reserved_11;
492 } TEST_UNIT_READY_CMD;
493
494 typedef struct {
495 UINT8 opcode;
496 UINT8 reserved_1 : 4;
497 UINT8 lun : 4;
498 UINT8 page_code;
499 UINT8 reserved_3;
500 UINT8 allocation_length;
501 UINT8 reserved_5;
502 UINT8 reserved_6;
503 UINT8 reserved_7;
504 UINT8 reserved_8;
505 UINT8 reserved_9;
506 UINT8 reserved_10;
507 UINT8 reserved_11;
508 } INQUIRY_CMD;
509
510 typedef struct {
511 UINT8 opcode;
512 UINT8 reserved_1 : 4;
513 UINT8 lun : 4;
514 UINT8 reserved_2;
515 UINT8 reserved_3;
516 UINT8 allocation_length;
517 UINT8 reserved_5;
518 UINT8 reserved_6;
519 UINT8 reserved_7;
520 UINT8 reserved_8;
521 UINT8 reserved_9;
522 UINT8 reserved_10;
523 UINT8 reserved_11;
524 } REQUEST_SENSE_CMD;
525
526 typedef struct {
527 UINT8 opcode;
528 UINT8 reserved_1 : 4;
529 UINT8 lun : 4;
530 UINT8 page_code : 4;
531 UINT8 page_control : 4;
532 UINT8 reserved_3;
533 UINT8 reserved_4;
534 UINT8 reserved_5;
535 UINT8 reserved_6;
536 UINT8 parameter_list_length_hi;
537 UINT8 parameter_list_length_lo;
538 UINT8 reserved_9;
539 UINT8 reserved_10;
540 UINT8 reserved_11;
541 } MODE_SENSE_CMD;
542
543 typedef struct {
544 UINT8 opcode;
545 UINT8 reserved_1 : 5;
546 UINT8 lun : 3;
547 UINT8 Lba0;
548 UINT8 Lba1;
549 UINT8 Lba2;
550 UINT8 Lba3;
551 UINT8 reserved_6;
552 UINT8 TranLen0;
553 UINT8 TranLen1;
554 UINT8 reserved_9;
555 UINT8 reserved_10;
556 UINT8 reserved_11;
557 } READ10_CMD;
558
559 typedef struct {
560 UINT8 opcode;
561 UINT8 reserved_1;
562 UINT8 reserved_2;
563 UINT8 reserved_3;
564 UINT8 reserved_4;
565 UINT8 reserved_5;
566 UINT8 reserved_6;
567 UINT8 allocation_length_hi;
568 UINT8 allocation_length_lo;
569 UINT8 reserved_9;
570 UINT8 reserved_10;
571 UINT8 reserved_11;
572 } READ_FORMAT_CAP_CMD;
573
574 typedef union {
575 UINT16 Data16[6];
576 TEST_UNIT_READY_CMD TestUnitReady;
577 READ10_CMD Read10;
578 REQUEST_SENSE_CMD RequestSence;
579 INQUIRY_CMD Inquiry;
580 MODE_SENSE_CMD ModeSense;
581 READ_FORMAT_CAP_CMD ReadFormatCapacity;
582 } ATAPI_PACKET_COMMAND;
583
584 typedef struct {
585 UINT32 RegionBaseAddr;
586 UINT16 ByteCount;
587 UINT16 EndOfTable;
588 } IDE_DMA_PRD;
589
590 #define MAX_DMA_EXT_COMMAND_SECTORS 0x10000
591 #define MAX_DMA_COMMAND_SECTORS 0x100
592
593 #pragma pack()
594
595 //
596 // Packet Command Code
597 //
598 #define TEST_UNIT_READY 0x00
599 #define REZERO 0x01
600 #define REQUEST_SENSE 0x03
601 #define FORMAT_UNIT 0x04
602 #define REASSIGN_BLOCKS 0x07
603 #define INQUIRY 0x12
604 #define START_STOP_UNIT 0x1B
605 #define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E
606 #define READ_FORMAT_CAPACITY 0x23
607 #define OLD_FORMAT_UNIT 0x24
608 #define READ_CAPACITY 0x25
609 #define READ_10 0x28
610 #define WRITE_10 0x2A
611 #define SEEK 0x2B
612 #define SEND_DIAGNOSTICS 0x3D
613 #define WRITE_VERIFY 0x2E
614 #define VERIFY 0x2F
615 #define READ_DEFECT_DATA 0x37
616 #define WRITE_BUFFER 0x38
617 #define READ_BUFFER 0x3C
618 #define READ_LONG 0x3E
619 #define WRITE_LONG 0x3F
620 #define MODE_SELECT 0x55
621 #define MODE_SENSE 0x5A
622 #define READ_12 0xA8
623 #define WRITE_12 0xAA
624 #define MAX_ATAPI_BYTE_COUNT (0xfffe)
625
626 //
627 // Sense Key
628 //
629 #define REQUEST_SENSE_ERROR (0x70)
630 #define SK_NO_SENSE (0x0)
631 #define SK_RECOVERY_ERROR (0x1)
632 #define SK_NOT_READY (0x2)
633 #define SK_MEDIUM_ERROR (0x3)
634 #define SK_HARDWARE_ERROR (0x4)
635 #define SK_ILLEGAL_REQUEST (0x5)
636 #define SK_UNIT_ATTENTION (0x6)
637 #define SK_DATA_PROTECT (0x7)
638 #define SK_BLANK_CHECK (0x8)
639 #define SK_VENDOR_SPECIFIC (0x9)
640 #define SK_RESERVED_A (0xA)
641 #define SK_ABORT (0xB)
642 #define SK_RESERVED_C (0xC)
643 #define SK_OVERFLOW (0xD)
644 #define SK_MISCOMPARE (0xE)
645 #define SK_RESERVED_F (0xF)
646
647 //
648 // Additional Sense Codes
649 //
650 #define ASC_NOT_READY (0x04)
651 #define ASC_MEDIA_ERR1 (0x10)
652 #define ASC_MEDIA_ERR2 (0x11)
653 #define ASC_MEDIA_ERR3 (0x14)
654 #define ASC_MEDIA_ERR4 (0x30)
655 #define ASC_MEDIA_UPSIDE_DOWN (0x06)
656 #define ASC_INVALID_CMD (0x20)
657 #define ASC_LBA_OUT_OF_RANGE (0x21)
658 #define ASC_INVALID_FIELD (0x24)
659 #define ASC_WRITE_PROTECTED (0x27)
660 #define ASC_MEDIA_CHANGE (0x28)
661 #define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
662 #define ASC_ILLEGAL_FIELD (0x26)
663 #define ASC_NO_MEDIA (0x3A)
664 #define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
665
666 //
667 // Additional Sense Code Qualifier
668 //
669 #define ASCQ_IN_PROGRESS (0x01)
670
671 #define SETFEATURE TRUE
672 #define CLEARFEATURE FALSE
673
674 //
675 // ATAPI Data structure
676 //
677 #pragma pack(1)
678
679 typedef struct {
680 UINT8 peripheral_type;
681 UINT8 RMB;
682 UINT8 version;
683 UINT8 response_data_format;
684 UINT8 addnl_length;
685 UINT8 reserved_5;
686 UINT8 reserved_6;
687 UINT8 reserved_7;
688 UINT8 vendor_info[8];
689 UINT8 product_id[12];
690 UINT8 eeprom_product_code[4];
691 UINT8 firmware_rev_level[4];
692 UINT8 firmware_sub_rev_level[1];
693 UINT8 reserved_37;
694 UINT8 reserved_38;
695 UINT8 reserved_39;
696 UINT8 max_capacity_hi;
697 UINT8 max_capacity_mid;
698 UINT8 max_capacity_lo;
699 UINT8 reserved_43_95[95 - 43 + 1];
700 } INQUIRY_DATA;
701
702 typedef struct {
703 UINT8 peripheral_type;
704 UINT8 RMB;
705 UINT8 version;
706 UINT8 response_data_format;
707 UINT8 addnl_length;
708 UINT8 reserved_5;
709 UINT8 reserved_6;
710 UINT8 reserved_7;
711 UINT8 vendor_info[8];
712 UINT8 product_id[16];
713 UINT8 product_revision_level[4];
714 UINT8 vendor_specific[20];
715 UINT8 reserved_56_95[40];
716 } CDROM_INQUIRY_DATA;
717
718 typedef struct {
719 UINT8 error_code : 7;
720 UINT8 valid : 1;
721 UINT8 reserved_1;
722 UINT8 sense_key : 4;
723 UINT8 reserved_21 : 1;
724 UINT8 ILI : 1;
725 UINT8 reserved_22 : 2;
726 UINT8 vendor_specific_3;
727 UINT8 vendor_specific_4;
728 UINT8 vendor_specific_5;
729 UINT8 vendor_specific_6;
730 UINT8 addnl_sense_length; // n - 7
731 UINT8 vendor_specific_8;
732 UINT8 vendor_specific_9;
733 UINT8 vendor_specific_10;
734 UINT8 vendor_specific_11;
735 UINT8 addnl_sense_code; // mandatory
736 UINT8 addnl_sense_code_qualifier; // mandatory
737 UINT8 field_replaceable_unit_code; // optional
738 UINT8 reserved_15;
739 UINT8 reserved_16;
740 UINT8 reserved_17;
741 //
742 // Followed by additional sense bytes : FIXME
743 //
744 } REQUEST_SENSE_DATA;
745
746 typedef struct {
747 UINT8 LastLba3;
748 UINT8 LastLba2;
749 UINT8 LastLba1;
750 UINT8 LastLba0;
751 UINT8 BlockSize3;
752 UINT8 BlockSize2;
753 UINT8 BlockSize1;
754 UINT8 BlockSize0;
755 } READ_CAPACITY_DATA;
756
757 typedef struct {
758 UINT8 reserved_0;
759 UINT8 reserved_1;
760 UINT8 reserved_2;
761 UINT8 Capacity_Length;
762 UINT8 LastLba3;
763 UINT8 LastLba2;
764 UINT8 LastLba1;
765 UINT8 LastLba0;
766 UINT8 DesCode : 2;
767 UINT8 reserved_9 : 6;
768 UINT8 BlockSize2;
769 UINT8 BlockSize1;
770 UINT8 BlockSize0;
771 } READ_FORMAT_CAPACITY_DATA;
772
773 #pragma pack()
774
775 //
776 // PIO mode definition
777 //
778 typedef enum {
779 ATA_PIO_MODE_BELOW_2,
780 ATA_PIO_MODE_2,
781 ATA_PIO_MODE_3,
782 ATA_PIO_MODE_4
783 } ATA_PIO_MODE;
784
785 //
786 // Multi word DMA definition
787 //
788 typedef enum {
789 ATA_MDMA_MODE_0,
790 ATA_MDMA_MODE_1,
791 ATA_MDMA_MODE_2
792 } ATA_MDMA_MODE;
793
794 //
795 // UDMA mode definition
796 //
797 typedef enum {
798 ATA_UDMA_MODE_0,
799 ATA_UDMA_MODE_1,
800 ATA_UDMA_MODE_2,
801 ATA_UDMA_MODE_3,
802 ATA_UDMA_MODE_4,
803 ATA_UDMA_MODE_5
804 } ATA_UDMA_MODE;
805
806 #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
807 #define ATA_MODE_CATEGORY_FLOW_PIO 0x01
808 #define ATA_MODE_CATEGORY_MDMA 0x04
809 #define ATA_MODE_CATEGORY_UDMA 0x08
810
811 #pragma pack(1)
812
813 typedef struct {
814 UINT8 ModeNumber : 3;
815 UINT8 ModeCategory : 5;
816 } ATA_TRANSFER_MODE;
817
818 typedef struct {
819 UINT8 Sector;
820 UINT8 Heads;
821 UINT8 MultipleSector;
822 } ATA_DRIVE_PARMS;
823
824 #pragma pack()
825 //
826 // IORDY Sample Point field value
827 //
828 #define ISP_5_CLK 0
829 #define ISP_4_CLK 1
830 #define ISP_3_CLK 2
831 #define ISP_2_CLK 3
832
833 //
834 // Recovery Time field value
835 //
836 #define RECVY_4_CLK 0
837 #define RECVY_3_CLK 1
838 #define RECVY_2_CLK 2
839 #define RECVY_1_CLK 3
840
841 //
842 // Slave IDE Timing Register Enable
843 //
844 #define SITRE bit14
845
846 //
847 // DMA Timing Enable Only Select 1
848 //
849 #define DTE1 bit7
850
851 //
852 // Pre-fetch and Posting Enable Select 1
853 //
854 #define PPE1 bit6
855
856 //
857 // IORDY Sample Point Enable Select 1
858 //
859 #define IE1 bit5
860
861 //
862 // Fast Timing Bank Drive Select 1
863 //
864 #define TIME1 bit4
865
866 //
867 // DMA Timing Enable Only Select 0
868 //
869 #define DTE0 bit3
870
871 //
872 // Pre-fetch and Posting Enable Select 0
873 //
874 #define PPE0 bit2
875
876 //
877 // IOREY Sample Point Enable Select 0
878 //
879 #define IE0 bit1
880
881 //
882 // Fast Timing Bank Drive Select 0
883 //
884 #define TIME0 bit0
885
886 #endif