EdkModulePkg/Bus/Pci/PciBus/Dxe/pcibus.h

   1 /*++
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14   pcibus.h
  15
  16 Abstract:
  17
  18   PCI Bus Driver
  19
  20 Revision History
  21
  22 --*/
  23
  24 #ifndef _EFI_PCI_BUS_H
  25 #define _EFI_PCI_BUS_H
  26
  27
  28 #include <IndustryStandard/pci22.h>
  29 #include <IndustryStandard/Acpi.h>
  30 #include "ComponentName.h"
  31
  32 //
  33 // Driver Produced Protocol Prototypes
  34 //
  35
  36 #define VGABASE1  0x3B0
  37 #define VGALIMIT1 0x3BB
  38
  39 #define VGABASE2  0x3C0
  40 #define VGALIMIT2 0x3DF
  41
  42 #define ISABASE   0x100
  43 #define ISALIMIT  0x3FF
  44
  45 typedef enum {
  46   PciBarTypeUnknown = 0,
  47   PciBarTypeIo16,
  48   PciBarTypeIo32,
  49   PciBarTypeMem32,
  50   PciBarTypePMem32,
  51   PciBarTypeMem64,
  52   PciBarTypePMem64,
  53   PciBarTypeIo,
  54   PciBarTypeMem,
  55   PciBarTypeMaxType
  56 } PCI_BAR_TYPE;
  57
  58 typedef struct {
  59   UINT64        BaseAddress;
  60   UINT64        Length;
  61   UINT64        Alignment;
  62   PCI_BAR_TYPE  BarType;
  63   BOOLEAN       Prefetchable;
  64   UINT8         MemType;
  65   UINT8         Offset;
  66 } PCI_BAR;
  67
  68 #define PPB_BAR_0                             0
  69 #define PPB_BAR_1                             1
  70 #define PPB_IO_RANGE                          2
  71 #define PPB_MEM32_RANGE                       3
  72 #define PPB_PMEM32_RANGE                      4
  73 #define PPB_PMEM64_RANGE                      5
  74 #define PPB_MEM64_RANGE                       0xFF
  75
  76 #define P2C_BAR_0                             0
  77 #define P2C_MEM_1                             1
  78 #define P2C_MEM_2                             2
  79 #define P2C_IO_1                              3
  80 #define P2C_IO_2                              4
  81
  82 #define PCI_IO_DEVICE_SIGNATURE               EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')
  83
  84 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
  85 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
  86 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
  87 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
  88 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
  89 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
  90 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
  91
  92 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
  93 //
  94 // Define resource status constant
  95 //
  96 #define EFI_RESOURCE_NONEXISTENT  0xFFFFFFFFFFFFFFFFULL
  97 #define EFI_RESOURCE_LESS         0xFFFFFFFFFFFFFFFEULL
  98 #define EFI_RESOURCE_SATISFIED    0x0000000000000000ULL
  99
 100 //
 101 // Define option for attribute
 102 //
 103 #define EFI_SET_SUPPORTS    0
 104 #define EFI_SET_ATTRIBUTES  1
 105
 106 typedef struct _PCI_IO_DEVICE {
 107   UINT32                                    Signature;
 108   EFI_HANDLE                                Handle;
 109   EFI_PCI_IO_PROTOCOL                       PciIo;
 110   LIST_ENTRY                                Link;
 111
 112   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 113   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 114   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 115
 116   //
 117   // PCI configuration space header type
 118   //
 119   PCI_TYPE00                                Pci;
 120
 121   //
 122   // Bus number, Device number, Function number
 123   //
 124   UINT8                                     BusNumber;
 125   UINT8                                     DeviceNumber;
 126   UINT8                                     FunctionNumber;
 127
 128   //
 129   // BAR for this PCI Device
 130   //
 131   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 132
 133   //
 134   // The bridge device this pci device is subject to
 135   //
 136   struct _PCI_IO_DEVICE                     *Parent;
 137
 138   //
 139   // A linked list for children Pci Device if it is bridge device
 140   //
 141   LIST_ENTRY                                ChildList;
 142
 143   //
 144   // TURE if the PCI bus driver creates the handle for this PCI device
 145   //
 146   BOOLEAN                                   Registered;
 147
 148   //
 149   // TRUE if the PCI bus driver successfully allocates the resource required by
 150   // this PCI device
 151   //
 152   BOOLEAN                                   Allocated;
 153
 154   //
 155   // The attribute this PCI device currently set
 156   //
 157   UINT64                                    Attributes;
 158
 159   //
 160   // The attributes this PCI device actually supports
 161   //
 162   UINT64                                    Supports;
 163
 164   //
 165   // The resource decode the bridge supports
 166   //
 167   UINT32                                    Decodes;
 168
 169   //
 170   // The OptionRom Size
 171   //
 172   UINT64                                    RomSize;
 173
 174   //
 175   // The OptionRom Size
 176   //
 177   UINT64                                    RomBase;
 178
 179   //
 180   // TRUE if all OpROM (in device or in platform specific position) have been processed
 181   //
 182   BOOLEAN                                   AllOpRomProcessed;
 183
 184   //
 185   // TRUE if there is any EFI driver in the OptionRom
 186   //
 187   BOOLEAN                                   BusOverride;
 188
 189   //
 190   //  A list tracking reserved resource on a bridge device
 191   //
 192   LIST_ENTRY                                ReservedResourceList;
 193
 194   //
 195   // A list tracking image handle of platform specific overriding driver
 196   //
 197   LIST_ENTRY                                OptionRomDriverList;
 198
 199   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 200   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 201
 202   BOOLEAN                                   IsPciExp;
 203
 204 } PCI_IO_DEVICE;
 205
 206
 207 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 208   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 209
 210 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 211   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 212
 213 #define PCI_IO_DEVICE_FROM_LINK(a) \
 214   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 215
 216 //
 217 // Global Variables
 218 //
 219 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
 220 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 221 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 222 extern LIST_ENTRY                                   gPciDevicePool;
 223 extern BOOLEAN                                      gFullEnumeration;
 224 extern UINTN                                        gPciHostBridgeNumber;
 225 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 226 extern UINT64                                       gAllOne;
 227 extern UINT64                                       gAllZero;
 228
 229 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 230
 231 #include "PciIo.h"
 232 #include "PciCommand.h"
 233 #include "PciDeviceSupport.h"
 234 #include "PciEnumerator.h"
 235 #include "PciEnumeratorSupport.h"
 236 #include "PciDriverOverride.h"
 237 #include "PciRomTable.h"
 238 #include "PciOptionRomSupport.h"
 239 #include "PciPowerManagement.h"
 240 #include "PciHotPlugSupport.h"
 241 #include "PciLib.h"
 242
 243 #endif