EdkModulePkg/Bus/Pci/Undi/RuntimeDxe/E100b.h

   1 /*++
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14   E100B.H
  15
  16 Abstract:
  17
  18
  19 Revision History
  20
  21 --*/
  22 // pci config offsets:
  23
  24 #define RX_BUFFER_COUNT 32
  25 #define TX_BUFFER_COUNT 32
  26
  27 #define PCI_VENDOR_ID_INTEL 0x8086
  28 #define PCI_DEVICE_ID_INTEL_82557 0x1229
  29 #define D100_VENDOR_ID   0x8086
  30 #define D100_DEVICE_ID   0x1229
  31 #define D102_DEVICE_ID   0x2449
  32
  33 #define ICH3_DEVICE_ID_1   0x1031
  34 #define ICH3_DEVICE_ID_2   0x1032
  35 #define ICH3_DEVICE_ID_3   0x1033
  36 #define ICH3_DEVICE_ID_4   0x1034
  37 #define ICH3_DEVICE_ID_5   0x1035
  38 #define ICH3_DEVICE_ID_6   0x1036
  39 #define ICH3_DEVICE_ID_7   0x1037
  40 #define ICH3_DEVICE_ID_8   0x1038
  41
  42 #define SPEEDO_DEVICE_ID   0x1227
  43 #define SPLASH1_DEVICE_ID   0x1226
  44
  45
  46 // bit fields for the command
  47 #define PCI_COMMAND_MASTER  0x04  // bit 2
  48 #define PCI_COMMAND_IO    0x01  // bit 0
  49 #define PCI_COMMAND  0x04
  50 #define PCI_LATENCY_TIMER  0x0D
  51
  52 #define ETHER_MAC_ADDR_LEN 6
  53 #ifdef AVL_XXX
  54 #define ETHER_HEADER_LEN 14
  55 // media interface type
  56 // #define INTERFACE_TYPE "
  57
  58 // Hardware type values
  59 #define HW_ETHER_TYPE    1
  60 #define HW_EXPERIMENTAL_ETHER_TYPE 2
  61 #define HW_IEEE_TYPE    6
  62 #define HW_ARCNET_TYPE     7
  63
  64 #endif  // AVL_XXX
  65
  66 #define MAX_ETHERNET_PKT_SIZE 1514  // including eth header
  67 #define RX_BUFFER_SIZE 1536  // including crc and padding
  68 #define TX_BUFFER_SIZE 64
  69 #define ETH_MTU 1500  // does not include ethernet header length
  70
  71 #define SPEEDO3_TOTAL_SIZE 0x20
  72
  73 #pragma pack(1)
  74
  75 typedef struct eth {
  76   UINT8 dest_addr[PXE_HWADDR_LEN_ETHER];
  77   UINT8 src_addr[PXE_HWADDR_LEN_ETHER];
  78   UINT16 type;
  79 } EtherHeader;
  80
  81 #pragma pack(1)
  82 typedef struct CONFIG_HEADER {
  83   UINT16 VendorID;
  84   UINT16 DeviceID;
  85   UINT16 Command;
  86   UINT16 Status;
  87   UINT16 RevID;
  88   UINT16 ClassID;
  89   UINT8  CacheLineSize;
  90   UINT8  LatencyTimer;
  91   UINT8  HeaderType;    // must be zero to impose this structure...
  92   UINT8  BIST;  // built-in self test
  93   UINT32 BaseAddressReg_0;  // memory mapped address
  94   UINT32 BaseAddressReg_1;  //io mapped address, Base IO address
  95   UINT32 BaseAddressReg_2;  // option rom address
  96   UINT32 BaseAddressReg_3;
  97   UINT32 BaseAddressReg_4;
  98   UINT32 BaseAddressReg_5;
  99   UINT32 CardBusCISPtr;
 100   UINT16 SubVendorID;
 101   UINT16 SubSystemID;
 102   UINT32 ExpansionROMBaseAddr;
 103   UINT8 CapabilitiesPtr;
 104   UINT8 reserved1;
 105   UINT16 Reserved2;
 106   UINT32 Reserved3;
 107   UINT8 int_line;
 108   UINT8 int_pin;
 109   UINT8 Min_gnt;
 110   UINT8 Max_lat;
 111 } PCI_CONFIG_HEADER;
 112 #pragma pack()
 113
 114 //-------------------------------------------------------------------------
 115 // Offsets to the various registers.
 116 //   All accesses need not be longword aligned.
 117 //-------------------------------------------------------------------------
 118 enum speedo_offsets {
 119   SCBStatus = 0, SCBCmd = 2,     // Rx/Command Unit command and status.
 120   SCBPointer = 4,                // General purpose pointer.
 121   SCBPort = 8,                   // Misc. commands and operands.
 122   SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.
 123   SCBCtrlMDI = 16,               // MDI interface control.
 124   SCBEarlyRx = 20,               // Early receive byte count.
 125   SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,
 126   // offsets for general control registers (GCRs)
 127   SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31,
 128 };
 129
 130 #define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2
 131
 132 //-------------------------------------------------------------------------
 133 // Action commands - Commands that can be put in a command list entry.
 134 //-------------------------------------------------------------------------
 135 enum commands {
 136   CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,
 137   CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7,
 138   CmdSuspend = 0x4000,    /* Suspend after completion. */
 139   CmdIntr = 0x2000,      /* Interrupt after completion. */
 140   CmdTxFlex = 0x0008,      /* Use "Flexible mode" for CmdTx command. */
 141 };
 142
 143 //-------------------------------------------------------------------------
 144 // port commands
 145 //-------------------------------------------------------------------------
 146 #define PORT_RESET 0
 147 #define PORT_SELF_TEST 1
 148 #define POR_SELECTIVE_RESET 2
 149 #define PORT_DUMP_POINTER 2
 150
 151 //-------------------------------------------------------------------------
 152 // SCB Command Word bit definitions
 153 //-------------------------------------------------------------------------
 154 //- CUC fields
 155 #define   CU_START    0x0010
 156 #define   CU_RESUME    0x0020
 157 #define   CU_STATSADDR  0x0040
 158 #define   CU_SHOWSTATS  0x0050  /* Dump statistics counters. */
 159 #define   CU_CMD_BASE  0x0060  /* Base address to add to add CU commands. */
 160 #define   CU_DUMPSTATS  0x0070  /* Dump then reset stats counters. */
 161
 162 //- RUC fields
 163 #define   RX_START  0x0001
 164 #define   RX_RESUME  0x0002
 165 #define   RX_ABORT  0x0004
 166 #define   RX_ADDR_LOAD  0x0006  /* load ru_base_reg */
 167 #define   RX_RESUMENR  0x0007
 168
 169 // Interrupt fields (assuming byte addressing)
 170 #define INT_MASK  0x0100
 171 #define DRVR_INT  0x0200    /* Driver generated interrupt. */
 172
 173 //- CB Status Word
 174 #define CMD_STATUS_COMPLETE 0x8000
 175 #define RX_STATUS_COMPLETE 0x8000
 176 #define CMD_STATUS_MASK 0xF000
 177
 178 //-------------------------------------------------------------------------
 179 //- SCB Status bits:
 180 // Interrupts are ACKed by writing to the upper 6 interrupt bits
 181 //-------------------------------------------------------------------------
 182 #define SCB_STATUS_MASK        0xFC00 // bits 2-7 - STATUS/ACK Mask
 183 #define SCB_STATUS_CX_TNO      0x8000 // BIT_15  - CX or TNO Interrupt
 184 #define SCB_STATUS_FR          0x4000 // BIT_14 - FR Interrupt
 185 #define SCB_STATUS_CNA         0x2000 // BIT_13 - CNA Interrupt
 186 #define SCB_STATUS_RNR         0x1000 // BIT_12  - RNR Interrupt
 187 #define SCB_STATUS_MDI         0x0800 // BIT_11  - MDI R/W Done Interrupt
 188 #define SCB_STATUS_SWI         0x0400 // BIT_10  - SWI Interrupt
 189
 190 // CU STATUS: bits 6 & 7
 191 #define SCB_STATUS_CU_MASK     0x00C0 // bits 6 & 7
 192 #define SCB_STATUS_CU_IDLE     0x0000 // 00
 193 #define SCB_STATUS_CU_SUSPEND  0x0040 // 01
 194 #define SCB_STATUS_CU_ACTIVE   0x0080 // 10
 195
 196 // RU STATUS: bits 2-5
 197 #define SCB_RUS_IDLE         0x0000
 198 #define SCB_RUS_SUSPENDED    0x0004  // bit 2
 199 #define SCB_RUS_NO_RESOURCES   0x0008 // bit 3
 200 #define SCB_RUS_READY       0x0010 // bit 4
 201
 202 //-------------------------------------------------------------------------
 203 // Bit Mask definitions
 204 //-------------------------------------------------------------------------
 205 #define BIT_0       0x0001
 206 #define BIT_1       0x0002
 207 #define BIT_2       0x0004
 208 #define BIT_3       0x0008
 209 #define BIT_4       0x0010
 210 #define BIT_5       0x0020
 211 #define BIT_6       0x0040
 212 #define BIT_7       0x0080
 213 #define BIT_8       0x0100
 214 #define BIT_9       0x0200
 215 #define BIT_10      0x0400
 216 #define BIT_11      0x0800
 217 #define BIT_12      0x1000
 218 #define BIT_13      0x2000
 219 #define BIT_14      0x4000
 220 #define BIT_15      0x8000
 221 #define BIT_24      0x01000000
 222 #define BIT_28      0x10000000
 223
 224
 225 //-------------------------------------------------------------------------
 226 // MDI Control register bit definitions
 227 //-------------------------------------------------------------------------
 228 #define MDI_DATA_MASK           BIT_0_15        // MDI Data port
 229 #define MDI_REG_ADDR            BIT_16_20       // which MDI register to read/write
 230 #define MDI_PHY_ADDR            BIT_21_25       // which PHY to read/write
 231 #define MDI_PHY_OPCODE          BIT_26_27       // which PHY to read/write
 232 #define MDI_PHY_READY           BIT_28          // PHY is ready for another MDI cycle
 233 #define MDI_PHY_INT_ENABLE      BIT_29          // Assert INT at MDI cycle completion
 234
 235 #define BIT_0_2     0x0007
 236 #define BIT_0_3     0x000F
 237 #define BIT_0_4     0x001F
 238 #define BIT_0_5     0x003F
 239 #define BIT_0_6     0x007F
 240 #define BIT_0_7     0x00FF
 241 #define BIT_0_8     0x01FF
 242 #define BIT_0_13    0x3FFF
 243 #define BIT_0_15    0xFFFF
 244 #define BIT_1_2     0x0006
 245 #define BIT_1_3     0x000E
 246 #define BIT_2_5     0x003C
 247 #define BIT_3_4     0x0018
 248 #define BIT_4_5     0x0030
 249 #define BIT_4_6     0x0070
 250 #define BIT_4_7     0x00F0
 251 #define BIT_5_7     0x00E0
 252 #define BIT_5_9     0x03E0
 253 #define BIT_5_12    0x1FE0
 254 #define BIT_5_15    0xFFE0
 255 #define BIT_6_7     0x00c0
 256 #define BIT_7_11    0x0F80
 257 #define BIT_8_10    0x0700
 258 #define BIT_9_13    0x3E00
 259 #define BIT_12_15   0xF000
 260
 261 #define BIT_16_20   0x001F0000
 262 #define BIT_21_25   0x03E00000
 263 #define BIT_26_27   0x0C000000
 264
 265 //-------------------------------------------------------------------------
 266 // MDI Control register opcode definitions
 267 //-------------------------------------------------------------------------
 268 #define MDI_WRITE               1               // Phy Write
 269 #define MDI_READ                2               // Phy read
 270
 271 //-------------------------------------------------------------------------
 272 // PHY 100 MDI Register/Bit Definitions
 273 //-------------------------------------------------------------------------
 274 // MDI register set
 275 #define MDI_CONTROL_REG             0x00        // MDI control register
 276 #define MDI_STATUS_REG              0x01        // MDI Status regiser
 277 #define PHY_ID_REG_1                0x02        // Phy indentification reg (word 1)
 278 #define PHY_ID_REG_2                0x03        // Phy indentification reg (word 2)
 279 #define AUTO_NEG_ADVERTISE_REG      0x04        // Auto-negotiation advertisement
 280 #define AUTO_NEG_LINK_PARTNER_REG   0x05        // Auto-negotiation link partner ability
 281 #define AUTO_NEG_EXPANSION_REG      0x06        // Auto-negotiation expansion
 282 #define AUTO_NEG_NEXT_PAGE_REG      0x07        // Auto-negotiation next page transmit
 283 #define EXTENDED_REG_0              0x10        // Extended reg 0 (Phy 100 modes)
 284 #define EXTENDED_REG_1              0x14        // Extended reg 1 (Phy 100 error indications)
 285 #define NSC_CONG_CONTROL_REG        0x17        // National (TX) congestion control
 286 #define NSC_SPEED_IND_REG           0x19        // National (TX) speed indication
 287
 288 // MDI Control register bit definitions
 289 #define MDI_CR_COLL_TEST_ENABLE     BIT_7       // Collision test enable
 290 #define MDI_CR_FULL_HALF            BIT_8       // FDX =1, half duplex =0
 291 #define MDI_CR_RESTART_AUTO_NEG     BIT_9       // Restart auto negotiation
 292 #define MDI_CR_ISOLATE              BIT_10      // Isolate PHY from MII
 293 #define MDI_CR_POWER_DOWN           BIT_11      // Power down
 294 #define MDI_CR_AUTO_SELECT          BIT_12      // Auto speed select enable
 295 #define MDI_CR_10_100               BIT_13      // 0 = 10Mbs, 1 = 100Mbs
 296 #define MDI_CR_LOOPBACK             BIT_14      // 0 = normal, 1 = loopback
 297 #define MDI_CR_RESET                BIT_15      // 0 = normal, 1 = PHY reset
 298
 299 // MDI Status register bit definitions
 300 #define MDI_SR_EXT_REG_CAPABLE      BIT_0       // Extended register capabilities
 301 #define MDI_SR_JABBER_DETECT        BIT_1       // Jabber detected
 302 #define MDI_SR_LINK_STATUS          BIT_2       // Link Status -- 1 = link
 303 #define MDI_SR_AUTO_SELECT_CAPABLE  BIT_3       // Auto speed select capable
 304 #define MDI_SR_REMOTE_FAULT_DETECT  BIT_4       // Remote fault detect
 305 #define MDI_SR_AUTO_NEG_COMPLETE    BIT_5       // Auto negotiation complete
 306 #define MDI_SR_10T_HALF_DPX         BIT_11      // 10BaseT Half Duplex capable
 307 #define MDI_SR_10T_FULL_DPX         BIT_12      // 10BaseT full duplex capable
 308 #define MDI_SR_TX_HALF_DPX          BIT_13      // TX Half Duplex capable
 309 #define MDI_SR_TX_FULL_DPX          BIT_14      // TX full duplex capable
 310 #define MDI_SR_T4_CAPABLE           BIT_15      // T4 capable
 311
 312 // Auto-Negotiation advertisement register bit definitions
 313 #define NWAY_AD_SELCTOR_FIELD       BIT_0_4     // identifies supported protocol
 314 #define NWAY_AD_ABILITY             BIT_5_12    // technologies that are supported
 315 #define NWAY_AD_10T_HALF_DPX        BIT_5       // 10BaseT Half Duplex capable
 316 #define NWAY_AD_10T_FULL_DPX        BIT_6       // 10BaseT full duplex capable
 317 #define NWAY_AD_TX_HALF_DPX         BIT_7       // TX Half Duplex capable
 318 #define NWAY_AD_TX_FULL_DPX         BIT_8       // TX full duplex capable
 319 #define NWAY_AD_T4_CAPABLE          BIT_9       // T4 capable
 320 #define NWAY_AD_REMOTE_FAULT        BIT_13      // indicates local remote fault
 321 #define NWAY_AD_RESERVED            BIT_14      // reserved
 322 #define NWAY_AD_NEXT_PAGE           BIT_15      // Next page (not supported)
 323
 324 // Auto-Negotiation link partner ability register bit definitions
 325 #define NWAY_LP_SELCTOR_FIELD       BIT_0_4     // identifies supported protocol
 326 #define NWAY_LP_ABILITY             BIT_5_9     // technologies that are supported
 327 #define NWAY_LP_REMOTE_FAULT        BIT_13      // indicates partner remote fault
 328 #define NWAY_LP_ACKNOWLEDGE         BIT_14      // acknowledge
 329 #define NWAY_LP_NEXT_PAGE           BIT_15      // Next page (not supported)
 330
 331 // Auto-Negotiation expansion register bit definitions
 332 #define NWAY_EX_LP_NWAY             BIT_0       // link partner is NWAY
 333 #define NWAY_EX_PAGE_RECEIVED       BIT_1       // link code word received
 334 #define NWAY_EX_NEXT_PAGE_ABLE      BIT_2       // local is next page able
 335 #define NWAY_EX_LP_NEXT_PAGE_ABLE   BIT_3       // partner is next page able
 336 #define NWAY_EX_PARALLEL_DET_FLT    BIT_4       // parallel detection fault
 337 #define NWAY_EX_RESERVED            BIT_5_15    // reserved
 338
 339
 340 // PHY 100 Extended Register 0 bit definitions
 341 #define PHY_100_ER0_FDX_INDIC       BIT_0       // 1 = FDX, 0 = half duplex
 342 #define PHY_100_ER0_SPEED_INDIC     BIT_1       // 1 = 100mbs, 0= 10mbs
 343 #define PHY_100_ER0_WAKE_UP         BIT_2       // Wake up DAC
 344 #define PHY_100_ER0_RESERVED        BIT_3_4     // Reserved
 345 #define PHY_100_ER0_REV_CNTRL       BIT_5_7     // Revsion control (A step = 000)
 346 #define PHY_100_ER0_FORCE_FAIL      BIT_8       // Force Fail is enabled
 347 #define PHY_100_ER0_TEST            BIT_9_13    // Revsion control (A step = 000)
 348 #define PHY_100_ER0_LINKDIS         BIT_14      // Link integrity test is disabled
 349 #define PHY_100_ER0_JABDIS          BIT_15      // Jabber function is disabled
 350
 351
 352 // PHY 100 Extended Register 1 bit definitions
 353 #define PHY_100_ER1_RESERVED        BIT_0_8     // Reserved
 354 #define PHY_100_ER1_CH2_DET_ERR     BIT_9       // Channel 2 EOF detection error
 355 #define PHY_100_ER1_MANCH_CODE_ERR  BIT_10      // Manchester code error
 356 #define PHY_100_ER1_EOP_ERR         BIT_11      // EOP error
 357 #define PHY_100_ER1_BAD_CODE_ERR    BIT_12      // bad code error
 358 #define PHY_100_ER1_INV_CODE_ERR    BIT_13      // invalid code error
 359 #define PHY_100_ER1_DC_BAL_ERR      BIT_14      // DC balance error
 360 #define PHY_100_ER1_PAIR_SKEW_ERR   BIT_15      // Pair skew error
 361
 362 // National Semiconductor TX phy congestion control register bit definitions
 363 #define NSC_TX_CONG_TXREADY         BIT_10      // Makes TxReady an input
 364 #define NSC_TX_CONG_ENABLE          BIT_8       // Enables congestion control
 365 #define NSC_TX_CONG_F_CONNECT       BIT_5       // Enables congestion control
 366
 367 // National Semiconductor TX phy speed indication register bit definitions
 368 #define NSC_TX_SPD_INDC_SPEED       BIT_6       // 0 = 100mb, 1=10mb
 369
 370 //-------------------------------------------------------------------------
 371 // Phy related constants
 372 //-------------------------------------------------------------------------
 373 #define PHY_503                 0
 374 #define PHY_100_A               0x000003E0
 375 #define PHY_100_C               0x035002A8
 376 #define PHY_TX_ID               0x015002A8
 377 #define PHY_NSC_TX              0x5c002000
 378 #define PHY_OTHER               0xFFFF
 379
 380 #define PHY_MODEL_REV_ID_MASK   0xFFF0FFFF
 381 #define PARALLEL_DETECT         0
 382 #define N_WAY                   1
 383
 384 #define RENEGOTIATE_TIME        35 // (3.5 Seconds)
 385
 386 #define CONNECTOR_AUTO          0
 387 #define CONNECTOR_TPE           1
 388 #define CONNECTOR_MII           2
 389
 390 //-------------------------------------------------------------------------
 391
 392 /* The Speedo3 Rx and Tx frame/buffer descriptors. */
 393 #pragma pack(1)
 394 struct CB_Header {      /* A generic descriptor. */
 395   UINT16 status;    /* Offset 0. */
 396   UINT16 command;    /* Offset 2. */
 397   UINT32 link;          /* struct descriptor *  */
 398 };
 399
 400 /* transmit command block structure */
 401 #pragma pack(1)
 402 typedef struct s_TxCB {
 403   struct CB_Header cb_header;
 404   UINT32 PhysTBDArrayAddres;  /* address of an array that contains
 405                 physical TBD pointers */
 406   UINT16 ByteCount;  /* immediate data count = 0 always */
 407   UINT8 Threshold;
 408   UINT8 TBDCount;
 409   UINT8 ImmediateData[TX_BUFFER_SIZE];
 410   /* following fields are not seen by the 82557 */
 411   struct TBD {
 412     UINT32 phys_buf_addr;
 413     UINT32 buf_len;
 414     } TBDArray[MAX_XMIT_FRAGMENTS];
 415   UINT32 PhysArrayAddr;  /* in case the one in the header is lost */
 416   UINT32 PhysTCBAddress;    /* for this TCB */
 417   struct s_TxCB *NextTCBVirtualLinkPtr;
 418   struct s_TxCB *PrevTCBVirtualLinkPtr;
 419   UINT64 free_data_ptr;  // to be given to the upper layer when this xmit completes1
 420 }TxCB;
 421
 422 /* The Speedo3 Rx and Tx buffer descriptors. */
 423 #pragma pack(1)
 424 typedef struct s_RxFD {          /* Receive frame descriptor. */
 425   struct CB_Header cb_header;
 426   UINT32 rx_buf_addr;      /* VOID * */
 427   UINT16 ActualCount;
 428   UINT16 RFDSize;
 429   UINT8 RFDBuffer[RX_BUFFER_SIZE];
 430   UINT8 forwarded;
 431   UINT8 junk[3];
 432 }RxFD;
 433
 434 /* Elements of the RxFD.status word. */
 435 #define RX_COMPLETE 0x8000
 436 #define RX_FRAME_OK 0x2000
 437
 438 /* Elements of the dump_statistics block. This block must be lword aligned. */
 439 #pragma pack(1)
 440 struct speedo_stats {
 441   UINT32 tx_good_frames;
 442   UINT32 tx_coll16_errs;
 443   UINT32 tx_late_colls;
 444   UINT32 tx_underruns;
 445   UINT32 tx_lost_carrier;
 446   UINT32 tx_deferred;
 447   UINT32 tx_one_colls;
 448   UINT32 tx_multi_colls;
 449   UINT32 tx_total_colls;
 450   UINT32 rx_good_frames;
 451   UINT32 rx_crc_errs;
 452   UINT32 rx_align_errs;
 453   UINT32 rx_resource_errs;
 454   UINT32 rx_overrun_errs;
 455   UINT32 rx_colls_errs;
 456   UINT32 rx_runt_errs;
 457   UINT32 done_marker;
 458 };
 459 #pragma pack()
 460
 461
 462 struct Krn_Mem{
 463   RxFD rx_ring[RX_BUFFER_COUNT];
 464   TxCB tx_ring[TX_BUFFER_COUNT];
 465   struct speedo_stats statistics;
 466 };
 467 #define MEMORY_NEEDED  sizeof(struct Krn_Mem)
 468
 469 /* The parameters for a CmdConfigure operation.
 470    There are so many options that it would be difficult to document each bit.
 471    We mostly use the default or recommended settings.
 472 */
 473
 474 /*
 475  *--------------------------------------------------------------------------
 476  * Configuration CB Parameter Bit Definitions
 477  *--------------------------------------------------------------------------
 478  */
 479 // - Byte 0  (Default Value = 16h)
 480 #define CFIG_BYTE_COUNT    0x16       // 22 Configuration Bytes
 481
 482 //- Byte 1  (Default Value = 88h)
 483 #define CFIG_TXRX_FIFO_LIMIT  0x88
 484
 485 //- Byte 2  (Default Value = 0)
 486 #define CFIG_ADAPTIVE_IFS    0
 487
 488 //- Byte 3  (Default Value = 0, ALWAYS. This byte is RESERVED)
 489 #define CFIG_RESERVED        0
 490
 491 //- Byte 4  (Default Value = 0. Default implies that Rx DMA cannot be
 492 //-          preempted).
 493 #define CFIG_RXDMA_BYTE_COUNT      0
 494
 495 //- Byte 5  (Default Value = 80h. Default implies that Tx DMA cannot be
 496 //-          preempted. However, setting these counters is enabled.)
 497 #define CFIG_DMBC_ENABLE            0x80
 498
 499 //- Byte 6  (Default Value = 33h. Late SCB enabled, No TNO interrupts,
 500 //-          CNA interrupts and do not save bad frames.)
 501 #define CFIG_LATE_SCB               1  // BIT 0
 502 #define CFIG_TNO_INTERRUPT          0x4  // BIT 2
 503 #define CFIG_CI_INTERRUPT           0x8  // BIT 3
 504 #define CFIG_SAVE_BAD_FRAMES        0x80  // BIT_7
 505
 506 //- Byte 7  (Default Value = 7h. Discard short frames automatically and
 507 //-          attempt upto 3 retries on transmit.)
 508 #define CFIG_DISCARD_SHORTRX         0x00001
 509 #define CFIG_URUN_RETRY              BIT_1 OR BIT_2
 510
 511 //- Byte 8  (Default Value = 1. Enable MII mode.)
 512 #define CFIG_503_MII              BIT_0
 513
 514 //- Byte 9  (Default Value = 0, ALWAYS)
 515
 516 //- Byte 10 (Default Value = 2Eh)
 517 #define CFIG_NSAI                   BIT_3
 518 #define CFIG_PREAMBLE_LENGTH         BIT_5      ;- Bit 5-4  = 1-0
 519 #define CFIG_NO_LOOPBACK             0
 520 #define CFIG_INTERNAL_LOOPBACK       BIT_6
 521 #define CFIG_EXT_LOOPBACK            BIT_7
 522 #define CFIG_EXT_PIN_LOOPBACK        BIT_6 OR BIT_7
 523
 524 //- Byte 11 (Default Value = 0)
 525 #define CFIG_LINEAR_PRIORITY         0
 526
 527 //- Byte 12 (Default Value = 60h)
 528 #define CFIG_LPRIORITY_MODE          0
 529 #define CFIG_IFS                     6          ;- 6 * 16 = 96
 530
 531 //- Byte 13 (Default Value = 0, ALWAYS)
 532
 533 //- Byte 14 (Default Value = 0F2h, ALWAYS)
 534
 535 //- Byte 15 (Default Value = E8h)
 536 #define CFIG_PROMISCUOUS_MODE        BIT_0
 537 #define CFIG_BROADCAST_DISABLE       BIT_1
 538 #define CFIG_CRS_CDT                 BIT_7
 539
 540 //- Byte 16 (Default Value = 0, ALWAYS)
 541
 542 //- Byte 17 (Default Value = 40h, ALWAYS)
 543
 544 //- Byte 18 (Default Value = F2h)
 545 #define CFIG_STRIPPING               BIT_0
 546 #define CFIG_PADDING                 BIT_1
 547 #define CFIG_RX_CRC_TRANSFER         BIT_2
 548
 549 //- Byte 19 (Default Value = 80h)
 550 #define CFIG_FORCE_FDX               BIT_6
 551 #define CFIG_FDX_PIN_ENABLE          BIT_7
 552
 553 //- Byte 20 (Default Value = 3Fh)
 554 #define CFIG_MULTI_IA                BIT_6
 555
 556 //- Byte 21 (Default Value = 05)
 557 #define CFIG_MC_ALL                  BIT_3
 558
 559 /*-----------------------------------------------------------------------*/
 560 #define D102_REVID 0x0b
 561
 562 #define HALF_DUPLEX 1
 563 #define FULL_DUPLEX 2
 564
 565 typedef struct s_data_instance {
 566
 567   UINT16 State;  // stopped, started or initialized
 568   UINT16 Bus;
 569   UINT8 Device;
 570   UINT8 Function;
 571   UINT16 VendorID;
 572   UINT16 DeviceID;
 573   UINT16 RevID;
 574   UINT16 SubVendorID;
 575   UINT16 SubSystemID;
 576
 577   UINT8 PermNodeAddress[PXE_MAC_LENGTH];
 578   UINT8 CurrentNodeAddress[PXE_MAC_LENGTH];
 579   UINT8 BroadcastNodeAddress[PXE_MAC_LENGTH];
 580   UINT32 Config[MAX_PCI_CONFIG_LEN];
 581   UINT32 NVData[MAX_EEPROM_LEN];
 582
 583   UINT32 ioaddr;
 584   UINT32 flash_addr;
 585
 586   UINT16 LinkSpeed;     // actual link speed setting
 587   UINT16 LinkSpeedReq;  // requested (forced) link speed
 588   UINT8  DuplexReq;     // requested duplex
 589   UINT8  Duplex;        // Duplex set
 590   UINT8  CableDetect;   // 1 to detect and 0 not to detect the cable
 591   UINT8  LoopBack;
 592
 593   UINT16 TxBufCnt;
 594   UINT16 TxBufSize;
 595   UINT16 RxBufCnt;
 596   UINT16 RxBufSize;
 597   UINT32 RxTotals;
 598   UINT32 TxTotals;
 599
 600   UINT16 int_mask;
 601   UINT16 Int_Status;
 602   UINT16 PhyRecord[2];  // primary and secondary PHY record registers from eeprom
 603   UINT8  PhyAddress;
 604   UINT8  int_num;
 605   UINT16 NVData_Len;
 606   UINT32 MemoryLength;
 607
 608   RxFD *rx_ring;  // array of rx buffers
 609   TxCB *tx_ring;  // array of tx buffers
 610   struct speedo_stats *statistics;
 611   TxCB *FreeTxHeadPtr;
 612   TxCB *FreeTxTailPtr;
 613   RxFD *RFDTailPtr;
 614
 615   UINT64 rx_phy_addr;  // physical addresses
 616   UINT64 tx_phy_addr;
 617   UINT64 stat_phy_addr;
 618   UINT64 MemoryPtr;
 619   UINT64 Mapped_MemoryPtr;
 620
 621   UINT64 xmit_done[TX_BUFFER_COUNT << 1]; // circular buffer
 622   UINT16 xmit_done_head;  // index into the xmit_done array
 623   UINT16 xmit_done_tail;  // where are we filling now (index into xmit_done)
 624   UINT16 cur_rx_ind;  // current RX Q head index
 625   UINT16 FreeCBCount;
 626
 627   BOOLEAN in_interrupt;
 628   BOOLEAN in_transmit;
 629   BOOLEAN Receive_Started;
 630   UINT8 Rx_Filter;
 631   UINT8 VersionFlag;  // UNDI30 or UNDI31??
 632   UINT8 rsvd[3];
 633
 634   struct mc{
 635     UINT16 reserved [3]; // padding for this structure to make it 8 byte aligned
 636     UINT16 list_len;
 637     UINT8 mc_list[MAX_MCAST_ADDRESS_CNT][PXE_MAC_LENGTH]; // 8*32 is the size
 638   } mcast_list;
 639
 640   UINT64 Unique_ID;
 641
 642   EFI_PCI_IO_PROTOCOL   *Io_Function;
 643
 644   VOID (*Delay_30)(UINTN);  // call back routine
 645   VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr);  // call back routine
 646   VOID (*Block_30)(UINT32 enable);  // call back routine
 647   VOID (*Mem_Io_30)(UINT8 read_write, UINT8 len, UINT64 port, UINT64 buf_addr);
 648   VOID (*Delay)(UINT64, UINTN);  // call back routine
 649   VOID (*Virt2Phys)(UINT64 unq_id, UINT64 virtual_addr, UINT64 physical_ptr);  // call back routine
 650   VOID (*Block)(UINT64 unq_id, UINT32 enable);  // call back routine
 651   VOID (*Mem_Io)(UINT64 unq_id, UINT8 read_write, UINT8 len, UINT64 port,
 652           UINT64 buf_addr);
 653   VOID (*Map_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
 654                    UINT32 Direction, UINT64 mapped_addr);
 655   VOID (*UnMap_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
 656             UINT32 Direction, UINT64 mapped_addr);
 657   VOID (*Sync_Mem)(UINT64 unq_id, UINT64 virtual_addr,
 658             UINT32 size, UINT32 Direction, UINT64 mapped_addr);
 659 } NIC_DATA_INSTANCE;
 660
 661 #pragma pack(1)
 662 struct MC_CB_STRUCT{
 663   UINT16 count;
 664   UINT8 m_list[MAX_MCAST_ADDRESS_CNT][ETHER_MAC_ADDR_LEN];
 665 };
 666 #pragma pack()
 667
 668 #define FOUR_GIGABYTE (UINT64)0x100000000ULL