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Make DxeIpl "assembly-free" to avoid the undesired LongMode.obj code in image even...
[mirror_edk2.git] / EdkModulePkg / Core / DxeIplPeim / Ia32 / VirtualMemory.h
1 /*++
2
3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module Name:
13 VirtualMemory.h
14
15 Abstract:
16
17 x64 Long Mode Virtual Memory Management Definitions
18
19 References:
20 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
21 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
22 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
23 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
24 --*/
25 #ifndef _VIRTUAL_MEMORY_H_
26 #define _VIRTUAL_MEMORY_H_
27
28
29 #define SYS_CODE64_SEL 0x38
30
31 #pragma pack(1)
32
33 typedef union {
34 struct {
35 UINT32 LimitLow : 16;
36 UINT32 BaseLow : 16;
37 UINT32 BaseMid : 8;
38 UINT32 Type : 4;
39 UINT32 System : 1;
40 UINT32 Dpl : 2;
41 UINT32 Present : 1;
42 UINT32 LimitHigh : 4;
43 UINT32 Software : 1;
44 UINT32 Reserved : 1;
45 UINT32 DefaultSize : 1;
46 UINT32 Granularity : 1;
47 UINT32 BaseHigh : 8;
48 } Bits;
49 UINT64 Uint64;
50 } IA32_GDT;
51
52 //
53 // Page-Map Level-4 Offset (PML4) and
54 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
55 //
56
57 typedef union {
58 struct {
59 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
60 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
61 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
62 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
63 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
64 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
65 UINT64 Reserved:1; // Reserved
66 UINT64 MustBeZero:2; // Must Be Zero
67 UINT64 Available:3; // Available for use by system software
68 UINT64 PageTableBaseAddress:40; // Page Table Base Address
69 UINT64 AvabilableHigh:11; // Available for use by system software
70 UINT64 Nx:1; // No Execute bit
71 } Bits;
72 UINT64 Uint64;
73 } PAGE_MAP_AND_DIRECTORY_POINTER;
74
75 //
76 // Page Table Entry 2MB
77 //
78 typedef union {
79 struct {
80 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
81 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
82 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
83 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
84 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
85 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
86 UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
87 UINT64 MustBe1:1; // Must be 1
88 UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
89 UINT64 Available:3; // Available for use by system software
90 UINT64 PAT:1; //
91 UINT64 MustBeZero:8; // Must be zero;
92 UINT64 PageTableBaseAddress:31; // Page Table Base Address
93 UINT64 AvabilableHigh:11; // Available for use by system software
94 UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
95 } Bits;
96 UINT64 Uint64;
97 } PAGE_TABLE_ENTRY;
98
99 #pragma pack()
100
101 UINTN
102 CreateIdentityMappingPageTables (
103 VOID
104 )
105 ;
106
107 #endif