EdkModulePkg/Core/DxeIplPeim/x64/VirtualMemory.h

   1 /*++
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13   VirtualMemory.h
  14
  15 Abstract:
  16
  17   x64 Long Mode Virtual Memory Management Definitions
  18
  19   References:
  20     1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
  21     2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
  22     3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
  23     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
  24 --*/
  25 #ifndef _VIRTUAL_MEMORY_H_
  26 #define _VIRTUAL_MEMORY_H_
  27
  28
  29 #pragma pack(1)
  30
  31 //
  32 // Page-Map Level-4 Offset (PML4) and
  33 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  34 //
  35
  36 typedef union {
  37   struct {
  38     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  39     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  40     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  41     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  42     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  43     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  44     UINT64  Reserved:1;               // Reserved
  45     UINT64  MustBeZero:2;             // Must Be Zero
  46     UINT64  Available:3;              // Available for use by system software
  47     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  48     UINT64  AvabilableHigh:11;        // Available for use by system software
  49     UINT64  Nx:1;                     // No Execute bit
  50   } Bits;
  51   UINT64    Uint64;
  52 } x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;
  53
  54 //
  55 // Page-Directory Offset 4K
  56 //
  57 typedef union {
  58   struct {
  59     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  60     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  61     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  62     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  63     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  64     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  65     UINT64  Reserved:1;               // Reserved
  66     UINT64  MustBeZero:1;             // Must Be Zero
  67     UINT64  Reserved2:1;              // Reserved
  68     UINT64  Available:3;              // Available for use by system software
  69     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  70     UINT64  AvabilableHigh:11;        // Available for use by system software
  71     UINT64  Nx:1;                     // No Execute bit
  72   } Bits;
  73   UINT64    Uint64;
  74 } x64_PAGE_DIRECTORY_ENTRY_4K;
  75
  76 //
  77 // Page Table Entry 4K
  78 //
  79 typedef union {
  80   struct {
  81     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  82     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  83     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  84     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  85     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  86     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  87     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  88     UINT64  PAT:1;                    // 0 = Ignore Page Attribute Table
  89     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  90     UINT64  Available:3;              // Available for use by system software
  91     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  92     UINT64  AvabilableHigh:11;        // Available for use by system software
  93     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  94   } Bits;
  95   UINT64    Uint64;
  96 } x64_PAGE_TABLE_ENTRY_4K;
  97
  98
  99 //
 100 // Page Table Entry 2MB
 101 //
 102 typedef union {
 103   struct {
 104     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 105     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 106     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 107     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 108     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 109     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 110     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 111     UINT64  MustBe1:1;                // Must be 1
 112     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 113     UINT64  Available:3;              // Available for use by system software
 114     UINT64  PAT:1;                    //
 115     UINT64  MustBeZero:8;             // Must be zero;
 116     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
 117     UINT64  AvabilableHigh:11;        // Available for use by system software
 118     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 119   } Bits;
 120   UINT64    Uint64;
 121 } x64_PAGE_TABLE_ENTRY_2M;
 122
 123 typedef union {
 124   UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 125   UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 126   UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 127   UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 128   UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 129   UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 130   UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 131   UINT64  Reserved:57;
 132 } x64_PAGE_TABLE_ENTRY_COMMON;
 133
 134 typedef union {
 135   x64_PAGE_TABLE_ENTRY_4K     Page4k;
 136   x64_PAGE_TABLE_ENTRY_2M     Page2Mb;
 137   x64_PAGE_TABLE_ENTRY_COMMON Common;
 138 } x64_PAGE_TABLE_ENTRY;
 139
 140 //
 141 // MTRR Definitions
 142 //
 143 typedef enum {
 144   Uncached       = 0,
 145   WriteCombining = 1,
 146   WriteThrough   = 4,
 147   WriteProtected = 5,
 148   WriteBack      = 6
 149 } x64_MTRR_MEMORY_TYPE;
 150
 151 typedef union {
 152   struct {
 153     UINT32  VCNT:8;         // The number of Variable Range MTRRs
 154     UINT32  FIX:1;          // 1=Fixed Range MTRRs supported.  0=Fixed Range MTRRs not supported
 155     UINT32  Reserved_0;     // Reserved
 156     UINT32  WC:1;           // Write combining memory type supported
 157     UINT32  Reserved_1:21;  // Reserved
 158     UINT32  Reserved_2:32;  // Reserved
 159   } Bits;
 160   UINT64  Uint64;
 161 } x64_MTRRCAP_MSR;
 162
 163 typedef union {
 164   struct {
 165     UINT32  Type:8;         // Default Memory Type
 166     UINT32  Reserved_0:2;   // Reserved
 167     UINT32  FE:1;           // 1=Fixed Range MTRRs enabled.  0=Fixed Range MTRRs disabled
 168     UINT32  E:1;            // 1=MTRRs enabled, 0=MTRRs disabled
 169     UINT32  Reserved_1:20;  // Reserved
 170     UINT32  Reserved_2:32;  // Reserved
 171   } Bits;
 172   UINT64  Uint64;
 173 } x64_MTRR_DEF_TYPE_MSR;
 174
 175 typedef union {
 176   UINT8   Type[8];          // The 8 Memory Type values in the 64-bit MTRR
 177   UINT64  Uint64;           // The full 64-bit MSR
 178 } x64_MTRR_FIXED_RANGE_MSR;
 179
 180 typedef struct {
 181   x64_MTRRCAP_MSR           Capabilities;   // MTRR Capabilities MSR value
 182   x64_MTRR_DEF_TYPE_MSR     DefaultType;    // Default Memory Type MSR Value
 183   x64_MTRR_FIXED_RANGE_MSR  Fixed[11];      // The 11 Fixed MTRR MSR Values
 184 } x64_MTRR_FIXED_RANGE;
 185
 186
 187 typedef union {
 188   struct {
 189     UINT64  Type:8;         // Memory Type
 190     UINT64  Reserved0:4;    // Reserved
 191     UINT64  PhysBase:40;    // The physical base address(bits 35..12) of the MTRR
 192     UINT64  Reserved1:12 ;  // Reserved
 193   } Bits;
 194   UINT64  Uint64;
 195 } x64_MTRR_PHYSBASE_MSR;
 196
 197 typedef union {
 198   struct {
 199     UINT64  Reserved0:11;  // Reserved
 200     UINT64  Valid:1;        // 1=MTRR is valid, 0=MTRR is not valid
 201     UINT64  PhysMask:40;    // The physical address mask (bits 35..12) of the MTRR
 202     UINT64  Reserved1:12;  // Reserved
 203   } Bits;
 204   UINT64  Uint64;
 205 } x64_MTRR_PHYSMASK_MSR;
 206
 207 typedef struct {
 208   x64_MTRR_PHYSBASE_MSR  PhysBase;  // Variable MTRR Physical Base MSR
 209   x64_MTRR_PHYSMASK_MSR  PhysMask;  // Variable MTRR Physical Mask MSR
 210 } x64_MTRR_VARIABLE_RANGE;
 211
 212 #pragma pack()
 213
 214 x64_MTRR_MEMORY_TYPE
 215 EfiGetMTRRMemoryType (
 216   IN  EFI_PHYSICAL_ADDRESS      Address
 217   )
 218 ;
 219
 220 BOOLEAN
 221 CanNotUse2MBPage (
 222   IN  EFI_PHYSICAL_ADDRESS  BaseAddress
 223   )
 224 ;
 225
 226 VOID
 227 Convert2MBPageTo4KPages (
 228   IN  x64_PAGE_TABLE_ENTRY_2M   *PageDirectoryEntry2MB,
 229   IN  EFI_PHYSICAL_ADDRESS        PageAddress
 230   )
 231 ;
 232
 233 EFI_PHYSICAL_ADDRESS
 234 CreateIdentityMappingPageTables (
 235   IN UINT32                NumberOfProcessorPhysicalAddressBits
 236   )
 237 ;
 238
 239 #endif