EmbeddedPkg/Drivers/DwEmmcDxe/DwEmmc.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15
  16 #ifndef __DWEMMC_H__
  17 #define __DWEMMC_H__
  18
  19 #include <Protocol/EmbeddedGpio.h>
  20
  21 // DW MMC Registers
  22 #define DWEMMC_CTRL             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)
  23 #define DWEMMC_PWREN            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004)
  24 #define DWEMMC_CLKDIV           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008)
  25 #define DWEMMC_CLKSRC           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c)
  26 #define DWEMMC_CLKENA           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)
  27 #define DWEMMC_TMOUT            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014)
  28 #define DWEMMC_CTYPE            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018)
  29 #define DWEMMC_BLKSIZ           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c)
  30 #define DWEMMC_BYTCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020)
  31 #define DWEMMC_INTMASK          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024)
  32 #define DWEMMC_CMDARG           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028)
  33 #define DWEMMC_CMD              ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c)
  34 #define DWEMMC_RESP0            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030)
  35 #define DWEMMC_RESP1            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034)
  36 #define DWEMMC_RESP2            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038)
  37 #define DWEMMC_RESP3            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c)
  38 #define DWEMMC_RINTSTS          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044)
  39 #define DWEMMC_STATUS           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048)
  40 #define DWEMMC_FIFOTH           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c)
  41 #define DWEMMC_TCBCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x05c)
  42 #define DWEMMC_TBBCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x060)
  43 #define DWEMMC_DEBNCE           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064)
  44 #define DWEMMC_HCON             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x070)
  45 #define DWEMMC_UHSREG           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074)
  46 #define DWEMMC_BMOD             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080)
  47 #define DWEMMC_DBADDR           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088)
  48 #define DWEMMC_IDSTS            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c)
  49 #define DWEMMC_IDINTEN          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090)
  50 #define DWEMMC_DSCADDR          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094)
  51 #define DWEMMC_BUFADDR          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098)
  52 #define DWEMMC_CARDTHRCTL       ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)
  53 #define DWEMMC_DATA             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X200)
  54
  55 #define CMD_UPDATE_CLK                          0x80202000
  56 #define CMD_START_BIT                           (1 << 31)
  57
  58 #define MMC_8BIT_MODE                           (1 << 16)
  59
  60 #define BIT_CMD_RESPONSE_EXPECT                 (1 << 6)
  61 #define BIT_CMD_LONG_RESPONSE                   (1 << 7)
  62 #define BIT_CMD_CHECK_RESPONSE_CRC              (1 << 8)
  63 #define BIT_CMD_DATA_EXPECTED                   (1 << 9)
  64 #define BIT_CMD_READ                            (0 << 10)
  65 #define BIT_CMD_WRITE                           (1 << 10)
  66 #define BIT_CMD_BLOCK_TRANSFER                  (0 << 11)
  67 #define BIT_CMD_STREAM_TRANSFER                 (1 << 11)
  68 #define BIT_CMD_SEND_AUTO_STOP                  (1 << 12)
  69 #define BIT_CMD_WAIT_PRVDATA_COMPLETE           (1 << 13)
  70 #define BIT_CMD_STOP_ABORT_CMD                  (1 << 14)
  71 #define BIT_CMD_SEND_INIT                       (1 << 15)
  72 #define BIT_CMD_UPDATE_CLOCK_ONLY               (1 << 21)
  73 #define BIT_CMD_READ_CEATA_DEVICE               (1 << 22)
  74 #define BIT_CMD_CCS_EXPECTED                    (1 << 23)
  75 #define BIT_CMD_ENABLE_BOOT                     (1 << 24)
  76 #define BIT_CMD_EXPECT_BOOT_ACK                 (1 << 25)
  77 #define BIT_CMD_DISABLE_BOOT                    (1 << 26)
  78 #define BIT_CMD_MANDATORY_BOOT                  (0 << 27)
  79 #define BIT_CMD_ALTERNATE_BOOT                  (1 << 27)
  80 #define BIT_CMD_VOLT_SWITCH                     (1 << 28)
  81 #define BIT_CMD_USE_HOLD_REG                    (1 << 29)
  82 #define BIT_CMD_START                           (1 << 31)
  83
  84 #define DWEMMC_INT_EBE                          (1 << 15)       /* End-bit Err */
  85 #define DWEMMC_INT_SBE                          (1 << 13)       /* Start-bit  Err */
  86 #define DWEMMC_INT_HLE                          (1 << 12)       /* Hardware-lock Err */
  87 #define DWEMMC_INT_FRUN                         (1 << 11)       /* FIFO UN/OV RUN */
  88 #define DWEMMC_INT_DRT                          (1 << 9)        /* Data timeout */
  89 #define DWEMMC_INT_RTO                          (1 << 8)        /* Response timeout */
  90 #define DWEMMC_INT_DCRC                         (1 << 7)        /* Data CRC err */
  91 #define DWEMMC_INT_RCRC                         (1 << 6)        /* Response CRC err */
  92 #define DWEMMC_INT_RXDR                         (1 << 5)
  93 #define DWEMMC_INT_TXDR                         (1 << 4)
  94 #define DWEMMC_INT_DTO                          (1 << 3)        /* Data trans over */
  95 #define DWEMMC_INT_CMD_DONE                     (1 << 2)
  96 #define DWEMMC_INT_RE                           (1 << 1)
  97
  98 #define DWEMMC_IDMAC_DES0_DIC                   (1 << 1)
  99 #define DWEMMC_IDMAC_DES0_LD                    (1 << 2)
 100 #define DWEMMC_IDMAC_DES0_FS                    (1 << 3)
 101 #define DWEMMC_IDMAC_DES0_CH                    (1 << 4)
 102 #define DWEMMC_IDMAC_DES0_ER                    (1 << 5)
 103 #define DWEMMC_IDMAC_DES0_CES                   (1 << 30)
 104 #define DWEMMC_IDMAC_DES0_OWN                   (1 << 31)
 105 #define DWEMMC_IDMAC_DES1_BS1(x)                ((x) & 0x1fff)
 106 #define DWEMMC_IDMAC_DES2_BS2(x)                (((x) & 0x1fff) << 13)
 107 #define DWEMMC_IDMAC_SWRESET                    (1 << 0)
 108 #define DWEMMC_IDMAC_FB                         (1 << 1)
 109 #define DWEMMC_IDMAC_ENABLE                     (1 << 7)
 110
 111 #define EMMC_FIX_RCA                            6
 112
 113 /* bits in MMC0_CTRL */
 114 #define DWEMMC_CTRL_RESET                       (1 << 0)
 115 #define DWEMMC_CTRL_FIFO_RESET                  (1 << 1)
 116 #define DWEMMC_CTRL_DMA_RESET                   (1 << 2)
 117 #define DWEMMC_CTRL_INT_EN                      (1 << 4)
 118 #define DWEMMC_CTRL_DMA_EN                      (1 << 5)
 119 #define DWEMMC_CTRL_IDMAC_EN                    (1 << 25)
 120 #define DWEMMC_CTRL_RESET_ALL                   (DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)
 121
 122 #define DWEMMC_STS_DATA_BUSY                    (1 << 9)
 123
 124 #define DWEMMC_FIFO_TWMARK(x)                   (x & 0xfff)
 125 #define DWEMMC_FIFO_RWMARK(x)                   ((x & 0x1ff) << 16)
 126 #define DWEMMC_DMA_BURST_SIZE(x)                ((x & 0x7) << 28)
 127
 128 #define DWEMMC_CARD_RD_THR(x)                   ((x & 0xfff) << 16)
 129 #define DWEMMC_CARD_RD_THR_EN                   (1 << 0)
 130
 131 #define DWEMMC_GET_HDATA_WIDTH(x)               (((x) >> 7) & 0x7)
 132
 133 #endif  // __DWEMMC_H__