EmbeddedPkg/Isp1761UsbDxe: Driver for the NXP ISP1761's USB peripheral controller
[mirror_edk2.git] / EmbeddedPkg / Drivers / Isp1761UsbDxe / Isp1761UsbDxe.h
1 /** @file
2
3 Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
4
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef __ISP1761_USB_DXE_H__
16 #define __ISP1761_USB_DXE_H__
17
18 #define ISP1761_USB_BASE FixedPcdGet32 (PcdIsp1761BaseAddress)
19
20 #define READ_REG32(Offset) MmioRead32 (ISP1761_USB_BASE + Offset)
21 #define READ_REG16(Offset) (UINT16) READ_REG32 (Offset)
22 #define WRITE_REG32(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, Val)
23 #define WRITE_REG16(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)
24 #define WRITE_REG8(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)
25
26 // Max packet size in bytes (For Full Speed USB 64 is the only valid value)
27 #define MAX_PACKET_SIZE_CONTROL 64
28
29 #define MAX_PACKET_SIZE_BULK 512
30
31 // 8 Endpoints, in and out. Don't count the Endpoint 0 setup buffer
32 #define ISP1761_NUM_ENDPOINTS 16
33
34 // Endpoint Indexes
35 #define ISP1761_EP0SETUP 0x20
36 #define ISP1761_EP0RX 0x00
37 #define ISP1761_EP0TX 0x01
38 #define ISP1761_EP1RX 0x02
39 #define ISP1761_EP1TX 0x03
40
41 // DcInterrupt bits
42 #define ISP1761_DC_INTERRUPT_BRESET BIT0
43 #define ISP1761_DC_INTERRUPT_SOF BIT1
44 #define ISP1761_DC_INTERRUPT_PSOF BIT2
45 #define ISP1761_DC_INTERRUPT_SUSP BIT3
46 #define ISP1761_DC_INTERRUPT_RESUME BIT4
47 #define ISP1761_DC_INTERRUPT_HS_STAT BIT5
48 #define ISP1761_DC_INTERRUPT_DMA BIT6
49 #define ISP1761_DC_INTERRUPT_VBUS BIT7
50 #define ISP1761_DC_INTERRUPT_EP0SETUP BIT8
51 #define ISP1761_DC_INTERRUPT_EP0RX BIT10
52 #define ISP1761_DC_INTERRUPT_EP0TX BIT11
53 #define ISP1761_DC_INTERRUPT_EP1RX BIT12
54 #define ISP1761_DC_INTERRUPT_EP1TX BIT13
55 // All valid peripheral controller interrupts
56 #define ISP1761_DC_INTERRUPT_MASK 0x003FFFDFF
57
58 #define ISP1761_ADDRESS 0x200
59 #define ISP1761_ADDRESS_DEVEN BIT7
60
61 #define ISP1761_MODE 0x20C
62 #define ISP1761_MODE_DATA_BUS_WIDTH BIT8
63 #define ISP1761_MODE_CLKAON BIT7
64 #define ISP1761_MODE_SFRESET BIT4
65 #define ISP1761_MODE_WKUPCS BIT2
66
67 #define ISP1761_ENDPOINT_MAX_PACKET_SIZE 0x204
68
69 #define ISP1761_ENDPOINT_TYPE 0x208
70 #define ISP1761_ENDPOINT_TYPE_NOEMPKT BIT4
71 #define ISP1761_ENDPOINT_TYPE_ENABLE BIT3
72
73 #define ISP1761_INTERRUPT_CONFIG 0x210
74 // Interrupt config value to only interrupt on ACK of IN and OUT tokens
75 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6
76
77 #define ISP1761_DC_INTERRUPT 0x218
78 #define ISP1761_DC_INTERRUPT_ENABLE 0x214
79
80 #define ISP1761_CTRL_FUNCTION 0x228
81 #define ISP1761_CTRL_FUNCTION_VENDP BIT3
82 #define ISP1761_CTRL_FUNCTION_DSEN BIT2
83 #define ISP1761_CTRL_FUNCTION_STATUS BIT1
84
85 #define ISP1761_DEVICE_UNLOCK 0x27C
86 #define ISP1761_DEVICE_UNLOCK_MAGIC 0xAA37
87
88 #define ISP1761_SW_RESET_REG 0x30C
89 #define ISP1761_SW_RESET_ALL BIT0
90
91 #define ISP1761_DEVICE_ID 0x370
92
93 #define ISP1761_OTG_CTRL_SET 0x374
94 #define ISP1761_OTG_CTRL_CLR OTG_CTRL_SET + 2
95 #define ISP1761_OTG_CTRL_OTG_DISABLE BIT10
96 #define ISP1761_OTG_CTRL_VBUS_CHRG BIT6
97 #define ISP1761_OTG_CTRL_VBUS_DISCHRG BIT5
98 #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
99 #define ISP1761_OTG_CTRL_DP_PULLDOWN BIT1
100 #define ISP1761_OTG_CTRL_DP_PULLUP BIT0
101
102 #define ISP1761_OTG_STATUS 0x378
103 #define ISP1761_OTG_STATUS_B_SESS_END BIT7
104 #define ISP1761_OTG_STATUS_A_B_SESS_VLD BIT1
105
106 #define ISP1761_OTG_INTERRUPT_LATCH_SET 0x37C
107 #define ISP1761_OTG_INTERRUPT_LATCH_CLR 0x37E
108 #define ISP1761_OTG_INTERRUPT_ENABLE_RISE 0x384
109
110 #define ISP1761_DMA_ENDPOINT_INDEX 0x258
111
112 #define ISP1761_ENDPOINT_INDEX 0x22c
113 #define ISP1761_DATA_PORT 0x220
114 #define ISP1761_BUFFER_LENGTH 0x21c
115
116 // Device ID Values
117 #define PHILLIPS_VENDOR_ID_VAL 0x04cc
118 #define ISP1761_PRODUCT_ID_VAL 0x1761
119 #define ISP1761_DEVICE_ID_VAL ((ISP1761_PRODUCT_ID_VAL << 16) |\
120 PHILLIPS_VENDOR_ID_VAL)
121
122 #endif //ifndef __ISP1761_USB_DXE_H__