EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2012-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include "Lan9118Dxe.h"
  16
  17 STATIC EFI_MAC_ADDRESS mZeroMac = { 0 };
  18
  19 /**
  20   This internal function reverses bits for 32bit data.
  21
  22   @param  Value                 The data to be reversed.
  23
  24   @return                       Data reversed.
  25
  26 **/
  27 UINT32
  28 ReverseBits (
  29   UINT32  Value
  30   )
  31 {
  32   UINTN   Index;
  33   UINT32  NewValue;
  34
  35   NewValue = 0;
  36   for (Index = 0; Index < 32; Index++) {
  37     if ((Value & (1 << Index)) != 0) {
  38       NewValue = NewValue | (1 << (31 - Index));
  39     }
  40   }
  41
  42   return NewValue;
  43 }
  44
  45 /*
  46 **  Create Ethernet CRC
  47 **
  48 **  INFO USED:
  49 **    1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check
  50 **
  51 **    2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html
  52 **
  53 **    3: http://en.wikipedia.org/wiki/Computation_of_CRC
  54 */
  55 UINT32
  56 GenEtherCrc32 (
  57   IN    EFI_MAC_ADDRESS *Mac,
  58   IN    UINT32 AddrLen
  59   )
  60 {
  61   INT32 Iter;
  62   UINT32 Remainder;
  63   UINT8 *Ptr;
  64
  65   Iter = 0;
  66   Remainder = 0xFFFFFFFF;    // 0xFFFFFFFF is standard seed for Ethernet
  67
  68   // Convert Mac Address to array of bytes
  69   Ptr = (UINT8*)Mac;
  70
  71   // Generate the Crc bit-by-bit (LSB first)
  72   while (AddrLen--) {
  73     Remainder ^= *Ptr++;
  74     for (Iter = 0;Iter < 8;Iter++) {
  75       // Check if exponent is set
  76       if (Remainder & 1) {
  77         Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;
  78       } else {
  79         Remainder = (Remainder >> 1) ^ 0;
  80       }
  81     }
  82   }
  83
  84   // Reverse the bits before returning (to Big Endian)
  85   //TODO: Need to be reviewed. Do we want to do a bit reverse or a byte reverse (in this case use SwapBytes32())
  86   return ReverseBits (Remainder);
  87 }
  88
  89 // Function to read from MAC indirect registers
  90 UINT32
  91 IndirectMACRead32 (
  92   UINT32 Index
  93   )
  94 {
  95   UINT32 MacCSR;
  96
  97   // Check index is in the range
  98   ASSERT(Index <= 12);
  99
 100   // Wait until CSR busy bit is cleared
 101   while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 102
 103   // Set CSR busy bit to ensure read will occur
 104   // Set the R/W bit to indicate we are reading
 105   // Set the index of CSR Address to access desired register
 106   MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index);
 107
 108   // Write to the register
 109   MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);
 110
 111   // Wait until CSR busy bit is cleared
 112   while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 113
 114   // Now read from data register to get read value
 115   return MmioRead32 (LAN9118_MAC_CSR_DATA);
 116 }
 117
 118 // Function to write to MAC indirect registers
 119 UINT32
 120 IndirectMACWrite32 (
 121   UINT32 Index,
 122   UINT32 Value
 123   )
 124 {
 125   UINT32 ValueWritten;
 126   UINT32 MacCSR;
 127
 128   // Check index is in the range
 129   ASSERT(Index <= 12);
 130
 131   // Wait until CSR busy bit is cleared
 132   while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 133
 134   // Set CSR busy bit to ensure read will occur
 135   // Set the R/W bit to indicate we are writing
 136   // Set the index of CSR Address to access desired register
 137   MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index);
 138
 139   // Now write the value to the register before issuing the write command
 140   ValueWritten = MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);
 141
 142   // Write the config to the register
 143   MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);
 144
 145   // Wait until CSR busy bit is cleared
 146   while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 147
 148   return ValueWritten;
 149 }
 150
 151 // Function to read from MII register (PHY Access)
 152 UINT32
 153 IndirectPHYRead32 (
 154   UINT32 Index
 155   )
 156 {
 157   UINT32 ValueRead;
 158   UINT32 MiiAcc;
 159
 160   // Check it is a valid index
 161   ASSERT(Index < 31);
 162
 163   // Wait for busy bit to clear
 164   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 165
 166   // Clear the R/W bit to indicate we are reading
 167   // Set the index of the MII register
 168   // Set the PHY Address
 169   // Set the MII busy bit to allow read
 170   MiiAcc = MII_ACC_MII_READ | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;
 171
 172   // Now write this config to register
 173   IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);
 174
 175   // Wait for busy bit to clear
 176   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 177
 178   // Now read the value of the register
 179   ValueRead = (IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_DATA) & 0xFFFF); // only lower 16 bits are valid for any PHY register
 180
 181   return ValueRead;
 182 }
 183
 184
 185 // Function to write to the MII register (PHY Access)
 186 UINT32
 187 IndirectPHYWrite32 (
 188   UINT32 Index,
 189   UINT32 Value
 190   )
 191 {
 192   UINT32 MiiAcc;
 193   UINT32 ValueWritten;
 194
 195   // Check it is a valid index
 196   ASSERT(Index < 31);
 197
 198   // Wait for busy bit to clear
 199   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 200
 201   // Clear the R/W bit to indicate we are reading
 202   // Set the index of the MII register
 203   // Set the PHY Address
 204   // Set the MII busy bit to allow read
 205   MiiAcc = MII_ACC_MII_WRITE | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;
 206
 207   // Write the desired value to the register first
 208   ValueWritten = IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_DATA, (Value & 0xFFFF));
 209
 210   // Now write the config to register
 211   IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);
 212
 213   // Wait for operation to terminate
 214   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 215
 216   return ValueWritten;
 217 }
 218
 219
 220 /* ---------------- EEPROM Operations ------------------ */
 221
 222
 223 // Function to read from EEPROM memory
 224 UINT32
 225 IndirectEEPROMRead32 (
 226   UINT32 Index
 227   )
 228 {
 229   UINT32 EepromCmd;
 230
 231   // Set the busy bit to ensure read will occur
 232   EepromCmd = E2P_EPC_BUSY | E2P_EPC_CMD_READ;
 233
 234   // Set the index to access desired EEPROM memory location
 235   EepromCmd |= E2P_EPC_ADDRESS(Index);
 236
 237   // Write to Eeprom command register
 238   MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);
 239   gBS->Stall (LAN9118_STALL);
 240
 241   // Wait until operation has completed
 242   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 243
 244   // Check that operation didn't time out
 245   if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {
 246     DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index));
 247     return 0;
 248   }
 249
 250   // Wait until operation has completed
 251   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 252
 253   // Finally read the value
 254   return MmioRead32 (LAN9118_E2P_DATA);
 255 }
 256
 257 // Function to write to EEPROM memory
 258 UINT32
 259 IndirectEEPROMWrite32 (
 260   UINT32 Index,
 261   UINT32 Value
 262   )
 263 {
 264   UINT32 ValueWritten;
 265   UINT32 EepromCmd;
 266
 267   ValueWritten = 0;
 268
 269   // Read the EEPROM Command register
 270   EepromCmd = MmioRead32 (LAN9118_E2P_CMD);
 271
 272   // Set the busy bit to ensure read will occur
 273   EepromCmd |= ((UINT32)1 << 31);
 274
 275   // Set the EEPROM command to write(0b011)
 276   EepromCmd &= ~(7 << 28);    // Clear the command first
 277   EepromCmd |= (3 << 28);     // Write 011
 278
 279   // Set the index to access desired EEPROM memory location
 280   EepromCmd |= (Index & 0xF);
 281
 282   // Write the value to the data register first
 283   ValueWritten = MmioWrite32 (LAN9118_E2P_DATA, Value);
 284
 285   // Write to Eeprom command register
 286   MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);
 287   gBS->Stall (LAN9118_STALL);
 288
 289   // Wait until operation has completed
 290   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 291
 292   // Check that operation didn't time out
 293   if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {
 294     DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value));
 295     return 0;
 296   }
 297
 298   // Wait until operation has completed
 299   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 300
 301   return ValueWritten;
 302 }
 303
 304 /* ---------------- General Operations ----------------- */
 305
 306 VOID
 307 Lan9118SetMacAddress (
 308   EFI_MAC_ADDRESS             *Mac,
 309   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 310   )
 311 {
 312   IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRL,
 313                       (Mac->Addr[0] & 0xFF) |
 314                       ((Mac->Addr[1] & 0xFF) << 8) |
 315                       ((Mac->Addr[2] & 0xFF) << 16) |
 316                       ((Mac->Addr[3] & 0xFF) << 24)
 317                     );
 318
 319   IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRH,
 320                       (UINT32)(Mac->Addr[4] & 0xFF) |
 321                       ((Mac->Addr[5] & 0xFF) << 8)
 322                     );
 323
 324   CopyMem (&Snp->Mode->CurrentAddress, &Mac, NET_ETHER_ADDR_LEN);
 325 }
 326
 327 VOID
 328 Lan9118ReadMacAddress (
 329   OUT EFI_MAC_ADDRESS *MacAddress
 330   )
 331 {
 332   UINT32          MacAddrHighValue;
 333   UINT32          MacAddrLowValue;
 334
 335   // Read the Mac Addr high register
 336   MacAddrHighValue = (IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRH) & 0xFFFF);
 337   // Read the Mac Addr low register
 338   MacAddrLowValue = IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRL);
 339
 340   SetMem (MacAddress, sizeof(*MacAddress), 0);
 341   MacAddress->Addr[0] = (MacAddrLowValue & 0xFF);
 342   MacAddress->Addr[1] = (MacAddrLowValue & 0xFF00) >> 8;
 343   MacAddress->Addr[2] = (MacAddrLowValue & 0xFF0000) >> 16;
 344   MacAddress->Addr[3] = (MacAddrLowValue & 0xFF000000) >> 24;
 345   MacAddress->Addr[4] = (MacAddrHighValue & 0xFF);
 346   MacAddress->Addr[5] = (MacAddrHighValue & 0xFF00) >> 8;
 347 }
 348
 349 /*
 350  *  Power up the 9118 and find its MAC address.
 351  *
 352  *  This operation can be carried out when the LAN9118 is in any power state
 353  *
 354  */
 355 EFI_STATUS
 356 Lan9118Initialize (
 357   IN  EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 358   )
 359 {
 360   UINTN  Timeout;
 361   UINT64 DefaultMacAddress;
 362
 363   // Attempt to wake-up the device if it is in a lower power state
 364   if (((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {
 365     DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));
 366     MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);
 367     gBS->Stall (LAN9118_STALL);
 368   }
 369
 370   // Check that device is active
 371   Timeout = 20;
 372   while ((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Timeout) {
 373     gBS->Stall (LAN9118_STALL);
 374   }
 375   if (!Timeout) {
 376     return EFI_TIMEOUT;
 377   }
 378
 379   // Check that EEPROM isn't active
 380   Timeout = 20;
 381   while ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Timeout){
 382     gBS->Stall (LAN9118_STALL);
 383   }
 384   if (!Timeout) {
 385     return EFI_TIMEOUT;
 386   }
 387
 388   // Check if a MAC address was loaded from EEPROM, and if it was, set it as the
 389   // current address.
 390   if ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {
 391     DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n"));
 392
 393     // If we had an address before (set by StationAddess), continue to use it
 394     if (CompareMem (&Snp->Mode->CurrentAddress, &mZeroMac, NET_ETHER_ADDR_LEN)) {
 395       Lan9118SetMacAddress (&Snp->Mode->CurrentAddress, Snp);
 396     } else {
 397       // If there are no cached addresses, then fall back to a default
 398       DEBUG ((EFI_D_WARN, "Warning: using driver-default MAC address\n"));
 399       DefaultMacAddress = FixedPcdGet64 (PcdLan9118DefaultMacAddress);
 400       Lan9118SetMacAddress((EFI_MAC_ADDRESS *) &DefaultMacAddress, Snp);
 401     }
 402   } else {
 403     // Store the MAC address that was loaded from EEPROM
 404     Lan9118ReadMacAddress (&Snp->Mode->CurrentAddress);
 405     CopyMem (&Snp->Mode->PermanentAddress, &Snp->Mode->CurrentAddress, NET_ETHER_ADDR_LEN);
 406   }
 407
 408   // Clear and acknowledge interrupts
 409   MmioWrite32 (LAN9118_INT_EN, 0);
 410   MmioWrite32 (LAN9118_IRQ_CFG, 0);
 411   MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);
 412
 413   // Do self tests here?
 414
 415   return EFI_SUCCESS;
 416 }
 417
 418
 419 // Perform software reset on the LAN9118
 420 // Return 0 on success, -1 on error
 421 EFI_STATUS
 422 SoftReset (
 423   UINT32 Flags,
 424   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 425   )
 426 {
 427   UINT32 HwConf;
 428   UINT32 ResetTime;
 429
 430   // Initialize variable
 431   ResetTime = 0;
 432
 433   // Stop Rx and Tx
 434   StopTx (STOP_TX_MAC | STOP_TX_CFG | STOP_TX_CLEAR, Snp);
 435   StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO
 436
 437   // Issue the reset
 438   HwConf = MmioRead32 (LAN9118_HW_CFG);
 439   HwConf |= 1;
 440
 441   // Set the Must Be One (MBO) bit
 442   if (((HwConf & HWCFG_MBO) >> 20) == 0) {
 443     HwConf |= HWCFG_MBO;
 444   }
 445
 446   // Check that EEPROM isn't active
 447   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 448
 449   // Write the configuration
 450   MmioWrite32 (LAN9118_HW_CFG, HwConf);
 451   gBS->Stall (LAN9118_STALL);
 452
 453   // Wait for reset to complete
 454   while (MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {
 455
 456     gBS->Stall (LAN9118_STALL);
 457     ResetTime += 1;
 458
 459     // If time taken exceeds 100us, then there was an error condition
 460     if (ResetTime > 1000) {
 461       Snp->Mode->State = EfiSimpleNetworkStopped;
 462       return EFI_TIMEOUT;
 463     }
 464   }
 465
 466   // Check that EEPROM isn't active
 467   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 468
 469   // TODO we probably need to re-set the mac address here.
 470
 471   // Clear and acknowledge all interrupts
 472   if (Flags & SOFT_RESET_CLEAR_INT) {
 473     MmioWrite32 (LAN9118_INT_EN, 0);
 474     MmioWrite32 (LAN9118_IRQ_CFG, 0);
 475     MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);
 476   }
 477
 478   // Do self tests here?
 479   if (Flags & SOFT_RESET_SELF_TEST) {
 480
 481   }
 482
 483   return EFI_SUCCESS;
 484 }
 485
 486
 487 // Perform PHY software reset
 488 INT32
 489 PhySoftReset (
 490   UINT32 Flags,
 491   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 492   )
 493 {
 494   UINT32 PmtCtrl = 0;
 495   UINT32 LinkTo = 0;
 496
 497   // PMT PHY reset takes precedence over BCR
 498   if (Flags & PHY_RESET_PMT) {
 499     PmtCtrl = MmioRead32 (LAN9118_PMT_CTRL);
 500     PmtCtrl |= MPTCTRL_PHY_RST;
 501     MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);
 502
 503     // Wait for completion
 504     while (MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {
 505       gBS->Stall (LAN9118_STALL);
 506     }
 507   // PHY Basic Control Register reset
 508   } else if (Flags & PHY_RESET_PMT) {
 509     IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PHYCR_RESET);
 510
 511     // Wait for completion
 512     while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {
 513       gBS->Stall (LAN9118_STALL);
 514     }
 515   }
 516
 517   // Check the link status
 518   if (Flags & PHY_RESET_CHECK_LINK) {
 519     LinkTo = 100000; // 2 second (could be 50% more)
 520     while (EFI_ERROR (CheckLinkStatus (0, Snp)) && (LinkTo > 0)) {
 521       gBS->Stall (LAN9118_STALL);
 522       LinkTo--;
 523     }
 524
 525     // Timed out
 526     if (LinkTo <= 0) {
 527       return -1;
 528     }
 529   }
 530
 531   // Clear and acknowledge all interrupts
 532   if (Flags & PHY_SOFT_RESET_CLEAR_INT) {
 533     MmioWrite32 (LAN9118_INT_EN, 0);
 534     MmioWrite32 (LAN9118_IRQ_CFG, 0);
 535     MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);
 536   }
 537
 538   return 0;
 539 }
 540
 541
 542 // Configure hardware for LAN9118
 543 EFI_STATUS
 544 ConfigureHardware (
 545   UINT32 Flags,
 546   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 547   )
 548 {
 549   UINT32 GpioConf;
 550
 551   // Check if we want to use LEDs on GPIO
 552   if (Flags & HW_CONF_USE_LEDS) {
 553     GpioConf = MmioRead32 (LAN9118_GPIO_CFG);
 554
 555     // Enable GPIO as LEDs and Config as Push-Pull driver
 556     GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL |
 557                 GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE;
 558
 559     // Write the configuration
 560     MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);
 561     gBS->Stall (LAN9118_STALL);
 562   }
 563
 564   return EFI_SUCCESS;
 565 }
 566
 567 // Configure flow control
 568 EFI_STATUS
 569 ConfigureFlow (
 570   UINT32 Flags,
 571   UINT32 HighTrig,
 572   UINT32 LowTrig,
 573   UINT32 BPDuration,
 574   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 575   )
 576 {
 577   return EFI_SUCCESS;
 578 }
 579
 580 // Do auto-negotiation
 581 EFI_STATUS
 582 AutoNegotiate (
 583   UINT32 Flags,
 584   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 585   )
 586 {
 587   UINT32 PhyControl;
 588   UINT32 PhyStatus;
 589   UINT32 Features;
 590   UINT32 TimeOut;
 591
 592   // First check that auto-negotiation is supported
 593   PhyStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);
 594   if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) {
 595     DEBUG ((EFI_D_ERROR, "Auto-negotiation not supported.\n"));
 596     return EFI_DEVICE_ERROR;
 597   }
 598
 599   // Check that link is up first
 600   if ((PhyStatus & PHYSTS_LINK_STS) == 0) {
 601     // Wait until it is up or until Time Out
 602     TimeOut = 2000;
 603     while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {
 604       gBS->Stall (LAN9118_STALL);
 605       TimeOut--;
 606       if (!TimeOut) {
 607         DEBUG ((EFI_D_ERROR, "Link timeout in auto-negotiation.\n"));
 608         return EFI_TIMEOUT;
 609       }
 610     }
 611   }
 612
 613   // Configure features to advertise
 614   Features = IndirectPHYRead32 (PHY_INDEX_AUTO_NEG_ADVERT);
 615
 616   if ((Flags & AUTO_NEGOTIATE_ADVERTISE_ALL) > 0) {
 617     // Link speed capabilities
 618     Features |= (PHYANA_10BASET | PHYANA_10BASETFD | PHYANA_100BASETX | PHYANA_100BASETXFD);
 619
 620     // Pause frame capabilities
 621     Features &= ~(PHYANA_PAUSE_OP_MASK);
 622     Features |= 3 << 10;
 623   }
 624
 625   // Write the features
 626   IndirectPHYWrite32 (PHY_INDEX_AUTO_NEG_ADVERT, Features);
 627
 628   // Read control register
 629   PhyControl = IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL);
 630
 631   // Enable Auto-Negotiation
 632   if ((PhyControl & PHYCR_AUTO_EN) == 0) {
 633     PhyControl |= PHYCR_AUTO_EN;
 634   }
 635
 636   // Restart auto-negotiation
 637   PhyControl |= PHYCR_RST_AUTO;
 638
 639   // Enable collision test if required to do so
 640   if (Flags & AUTO_NEGOTIATE_COLLISION_TEST) {
 641     PhyControl |= PHYCR_COLL_TEST;
 642   } else {
 643     PhyControl &= ~ PHYCR_COLL_TEST;
 644   }
 645
 646   // Write this configuration
 647   IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PhyControl);
 648
 649   // Wait until process has completed
 650   while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0);
 651
 652   return EFI_SUCCESS;
 653 }
 654
 655 // Check the Link Status and take appropriate action
 656 EFI_STATUS
 657 CheckLinkStatus (
 658   UINT32 Flags,
 659   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 660   )
 661 {
 662   // Get the PHY Status
 663   UINT32 PhyBStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);
 664
 665   if (PhyBStatus & PHYSTS_LINK_STS) {
 666     return EFI_SUCCESS;
 667   } else {
 668     return EFI_DEVICE_ERROR;
 669   }
 670 }
 671
 672 // Stop the transmitter
 673 EFI_STATUS
 674 StopTx (
 675   UINT32 Flags,
 676   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 677   )
 678 {
 679   UINT32 MacCsr;
 680   UINT32 TxCfg;
 681
 682   MacCsr = 0;
 683   TxCfg = 0;
 684
 685   // Check if we want to clear tx
 686   if (Flags & STOP_TX_CLEAR) {
 687     TxCfg = MmioRead32 (LAN9118_TX_CFG);
 688     TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;
 689     MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 690     gBS->Stall (LAN9118_STALL);
 691   }
 692
 693   // Check if already stopped
 694   if (Flags & STOP_TX_MAC) {
 695     MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 696
 697     if (MacCsr & MACCR_TX_EN) {
 698       MacCsr &= ~MACCR_TX_EN;
 699       IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 700     }
 701   }
 702
 703   if (Flags & STOP_TX_CFG) {
 704     TxCfg = MmioRead32 (LAN9118_TX_CFG);
 705
 706     if (TxCfg & TXCFG_TX_ON) {
 707       TxCfg |= TXCFG_STOP_TX;
 708       MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 709       gBS->Stall (LAN9118_STALL);
 710
 711       // Wait for Tx to finish transmitting
 712       while (MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);
 713     }
 714   }
 715
 716   return EFI_SUCCESS;
 717 }
 718
 719 // Stop the receiver
 720 EFI_STATUS
 721 StopRx (
 722   UINT32 Flags,
 723   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 724   )
 725 {
 726   UINT32 MacCsr;
 727   UINT32 RxCfg;
 728
 729   RxCfg = 0;
 730
 731   // Check if already stopped
 732   MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 733
 734   if (MacCsr & MACCR_RX_EN) {
 735     MacCsr &= ~ MACCR_RX_EN;
 736     IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 737   }
 738
 739   // Check if we want to clear receiver FIFOs
 740   if (Flags & STOP_RX_CLEAR) {
 741     RxCfg = MmioRead32 (LAN9118_RX_CFG);
 742     RxCfg |= RXCFG_RX_DUMP;
 743     MmioWrite32 (LAN9118_RX_CFG, RxCfg);
 744     gBS->Stall (LAN9118_STALL);
 745
 746     while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);
 747   }
 748
 749   return EFI_SUCCESS;
 750 }
 751
 752 // Start the transmitter
 753 EFI_STATUS
 754 StartTx (
 755   UINT32 Flags,
 756   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 757   )
 758 {
 759   UINT32 MacCsr;
 760   UINT32 TxCfg;
 761
 762   MacCsr = 0;
 763   TxCfg = 0;
 764
 765   // Check if we want to clear tx
 766   if (Flags & START_TX_CLEAR) {
 767     TxCfg = MmioRead32 (LAN9118_TX_CFG);
 768     TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;
 769     MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 770     gBS->Stall (LAN9118_STALL);
 771   }
 772
 773   // Check if tx was started from MAC and enable if not
 774   if (Flags & START_TX_MAC) {
 775     MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 776     gBS->Stall (LAN9118_STALL);
 777     if ((MacCsr & MACCR_TX_EN) == 0) {
 778       MacCsr |= MACCR_TX_EN;
 779       IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 780       gBS->Stall (LAN9118_STALL);
 781     }
 782   }
 783
 784   // Check if tx was started from TX_CFG and enable if not
 785   if (Flags & START_TX_CFG) {
 786     TxCfg = MmioRead32 (LAN9118_TX_CFG);
 787     gBS->Stall (LAN9118_STALL);
 788     if ((TxCfg & TXCFG_TX_ON) == 0) {
 789       TxCfg |= TXCFG_TX_ON;
 790       MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 791       gBS->Stall (LAN9118_STALL);
 792     }
 793   }
 794
 795   // Set the tx data trigger level
 796
 797   return EFI_SUCCESS;
 798 }
 799
 800 // Start the receiver
 801 EFI_STATUS
 802 StartRx (
 803   UINT32 Flags,
 804   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 805   )
 806 {
 807   UINT32 MacCsr;
 808   UINT32 RxCfg;
 809
 810   RxCfg = 0;
 811
 812   // Check if already started
 813   MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 814
 815   if ((MacCsr & MACCR_RX_EN) == 0) {
 816     // Check if we want to clear receiver FIFOs before starting
 817     if (Flags & START_RX_CLEAR) {
 818       RxCfg = MmioRead32 (LAN9118_RX_CFG);
 819       RxCfg |= RXCFG_RX_DUMP;
 820       MmioWrite32 (LAN9118_RX_CFG, RxCfg);
 821       gBS->Stall (LAN9118_STALL);
 822
 823       while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);
 824     }
 825
 826     MacCsr |= MACCR_RX_EN;
 827     IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 828     gBS->Stall (LAN9118_STALL);
 829   }
 830
 831   return EFI_SUCCESS;
 832 }
 833
 834 // Check Tx Data available space
 835 UINT32
 836 TxDataFreeSpace (
 837   UINT32 Flags,
 838   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 839   )
 840 {
 841   UINT32 TxInf;
 842   UINT32 FreeSpace;
 843
 844   // Get the amount of free space from information register
 845   TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);
 846   FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK);
 847
 848   return FreeSpace; // Value in bytes
 849 }
 850
 851 // Check Tx Status used space
 852 UINT32
 853 TxStatusUsedSpace (
 854   UINT32 Flags,
 855   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 856   )
 857 {
 858   UINT32 TxInf;
 859   UINT32 UsedSpace;
 860
 861   // Get the amount of used space from information register
 862   TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);
 863   UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16;
 864
 865   return UsedSpace << 2; // Value in bytes
 866 }
 867
 868 // Check Rx Data used space
 869 UINT32
 870 RxDataUsedSpace (
 871   UINT32 Flags,
 872   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 873   )
 874 {
 875   UINT32 RxInf;
 876   UINT32 UsedSpace;
 877
 878   // Get the amount of used space from information register
 879   RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);
 880   UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK);
 881
 882   return UsedSpace; // Value in bytes (rounded up to nearest DWORD)
 883 }
 884
 885 // Check Rx Status used space
 886 UINT32
 887 RxStatusUsedSpace (
 888   UINT32 Flags,
 889   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 890   )
 891 {
 892   UINT32 RxInf;
 893   UINT32 UsedSpace;
 894
 895   // Get the amount of used space from information register
 896   RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);
 897   UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16;
 898
 899   return UsedSpace << 2; // Value in bytes
 900 }
 901
 902
 903 // Change the allocation of FIFOs
 904 EFI_STATUS
 905 ChangeFifoAllocation (
 906   IN      UINT32 Flags,
 907   IN  OUT UINTN  *TxDataSize    OPTIONAL,
 908   IN  OUT UINTN  *RxDataSize    OPTIONAL,
 909   IN  OUT UINT32 *TxStatusSize  OPTIONAL,
 910   IN  OUT UINT32 *RxStatusSize  OPTIONAL,
 911   IN  OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 912   )
 913 {
 914   UINT32 HwConf;
 915   UINT32 TxFifoOption;
 916
 917   // Check that desired sizes don't exceed limits
 918   if (*TxDataSize > TX_FIFO_MAX_SIZE)
 919     return EFI_INVALID_PARAMETER;
 920
 921 #if defined(RX_FIFO_MIN_SIZE) && defined(RX_FIFO_MAX_SIZE)
 922   if (*RxDataSize > RX_FIFO_MAX_SIZE) {
 923     return EFI_INVALID_PARAMETER;
 924   }
 925 #endif
 926
 927   if (Flags & ALLOC_USE_DEFAULT) {
 928     return EFI_SUCCESS;
 929   }
 930
 931   // If we use the FIFOs (always use this first)
 932   if (Flags & ALLOC_USE_FIFOS) {
 933     // Read the current value of allocation
 934     HwConf = MmioRead32 (LAN9118_HW_CFG);
 935     TxFifoOption = (HwConf >> 16) & 0xF;
 936
 937     // Choose the correct size (always use larger than requested if possible)
 938     if (*TxDataSize < TX_FIFO_MIN_SIZE) {
 939       *TxDataSize = TX_FIFO_MIN_SIZE;
 940       *RxDataSize = 13440;
 941       *RxStatusSize = 896;
 942       TxFifoOption = 2;
 943     } else if ((*TxDataSize > TX_FIFO_MIN_SIZE) && (*TxDataSize <= 2560)) {
 944       *TxDataSize = 2560;
 945       *RxDataSize = 12480;
 946       *RxStatusSize = 832;
 947       TxFifoOption = 3;
 948     } else if ((*TxDataSize > 2560) && (*TxDataSize <= 3584)) {
 949       *TxDataSize = 3584;
 950       *RxDataSize = 11520;
 951       *RxStatusSize = 768;
 952       TxFifoOption = 4;
 953     } else if ((*TxDataSize > 3584) && (*TxDataSize <= 4608)) { // default option
 954       *TxDataSize = 4608;
 955       *RxDataSize = 10560;
 956       *RxStatusSize = 704;
 957       TxFifoOption = 5;
 958     } else if ((*TxDataSize > 4608) && (*TxDataSize <= 5632)) {
 959       *TxDataSize = 5632;
 960       *RxDataSize = 9600;
 961       *RxStatusSize = 640;
 962       TxFifoOption = 6;
 963     } else if ((*TxDataSize > 5632) && (*TxDataSize <= 6656)) {
 964       *TxDataSize = 6656;
 965       *RxDataSize = 8640;
 966       *RxStatusSize = 576;
 967       TxFifoOption = 7;
 968     } else if ((*TxDataSize > 6656) && (*TxDataSize <= 7680)) {
 969       *TxDataSize = 7680;
 970       *RxDataSize = 7680;
 971       *RxStatusSize = 512;
 972       TxFifoOption = 8;
 973     } else if ((*TxDataSize > 7680) && (*TxDataSize <= 8704)) {
 974       *TxDataSize = 8704;
 975       *RxDataSize = 6720;
 976       *RxStatusSize = 448;
 977       TxFifoOption = 9;
 978     } else if ((*TxDataSize > 8704) && (*TxDataSize <= 9728)) {
 979       *TxDataSize = 9728;
 980       *RxDataSize = 5760;
 981       *RxStatusSize = 384;
 982       TxFifoOption = 10;
 983     } else if ((*TxDataSize > 9728) && (*TxDataSize <= 10752)) {
 984       *TxDataSize = 10752;
 985       *RxDataSize = 4800;
 986       *RxStatusSize = 320;
 987       TxFifoOption = 11;
 988     } else if ((*TxDataSize > 10752) && (*TxDataSize <= 11776)) {
 989       *TxDataSize = 11776;
 990       *RxDataSize = 3840;
 991       *RxStatusSize = 256;
 992       TxFifoOption = 12;
 993     } else if ((*TxDataSize > 11776) && (*TxDataSize <= 12800)) {
 994       *TxDataSize = 12800;
 995       *RxDataSize = 2880;
 996       *RxStatusSize = 192;
 997       TxFifoOption = 13;
 998     } else if ((*TxDataSize > 12800) && (*TxDataSize <= 13824)) {
 999       *TxDataSize = 13824;
1000       *RxDataSize = 1920;
1001       *RxStatusSize = 128;
1002       TxFifoOption = 14;
1003     }
1004   } else {
1005     ASSERT(0); // Untested code path
1006     HwConf = 0;
1007     TxFifoOption = 0;
1008   }
1009
1010   // Do we need DMA?
1011   if (Flags & ALLOC_USE_DMA) {
1012     return EFI_UNSUPPORTED; // Unsupported as of now
1013   }
1014   // Clear and assign the new size option
1015   HwConf &= ~(0xF0000);
1016   HwConf |= ((TxFifoOption & 0xF) << 16);
1017   MmioWrite32 (LAN9118_HW_CFG, HwConf);
1018   gBS->Stall (LAN9118_STALL);
1019
1020   return EFI_SUCCESS;
1021 }