EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2012-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include "Lan9118Dxe.h"
  16
  17 STATIC EFI_MAC_ADDRESS mZeroMac = { { 0 } };
  18
  19 /**
  20   This internal function reverses bits for 32bit data.
  21
  22   @param  Value                 The data to be reversed.
  23
  24   @return                       Data reversed.
  25
  26 **/
  27 UINT32
  28 ReverseBits (
  29   UINT32  Value
  30   )
  31 {
  32   UINTN   Index;
  33   UINT32  NewValue;
  34
  35   NewValue = 0;
  36   for (Index = 0; Index < 32; Index++) {
  37     if ((Value & (1 << Index)) != 0) {
  38       NewValue = NewValue | (1 << (31 - Index));
  39     }
  40   }
  41
  42   return NewValue;
  43 }
  44
  45 /*
  46 **  Create Ethernet CRC
  47 **
  48 **  INFO USED:
  49 **    1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check
  50 **
  51 **    2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html
  52 **
  53 **    3: http://en.wikipedia.org/wiki/Computation_of_CRC
  54 */
  55 UINT32
  56 GenEtherCrc32 (
  57   IN    EFI_MAC_ADDRESS *Mac,
  58   IN    UINT32 AddrLen
  59   )
  60 {
  61   INT32 Iter;
  62   UINT32 Remainder;
  63   UINT8 *Ptr;
  64
  65   Iter = 0;
  66   Remainder = 0xFFFFFFFF;    // 0xFFFFFFFF is standard seed for Ethernet
  67
  68   // Convert Mac Address to array of bytes
  69   Ptr = (UINT8*)Mac;
  70
  71   // Generate the Crc bit-by-bit (LSB first)
  72   while (AddrLen--) {
  73     Remainder ^= *Ptr++;
  74     for (Iter = 0;Iter < 8;Iter++) {
  75       // Check if exponent is set
  76       if (Remainder & 1) {
  77         Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;
  78       } else {
  79         Remainder = (Remainder >> 1) ^ 0;
  80       }
  81     }
  82   }
  83
  84   // Reverse the bits before returning (to Big Endian)
  85   //TODO: Need to be reviewed. Do we want to do a bit reverse or a byte reverse (in this case use SwapBytes32())
  86   return ReverseBits (Remainder);
  87 }
  88
  89 // Function to read from MAC indirect registers
  90 UINT32
  91 IndirectMACRead32 (
  92   UINT32 Index
  93   )
  94 {
  95   UINT32 MacCSR;
  96
  97   // Check index is in the range
  98   ASSERT(Index <= 12);
  99
 100   // Wait until CSR busy bit is cleared
 101   while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 102
 103   // Set CSR busy bit to ensure read will occur
 104   // Set the R/W bit to indicate we are reading
 105   // Set the index of CSR Address to access desired register
 106   MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index);
 107
 108   // Write to the register
 109   MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);
 110
 111   // Wait until CSR busy bit is cleared
 112   while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 113
 114   // Now read from data register to get read value
 115   return MmioRead32 (LAN9118_MAC_CSR_DATA);
 116 }
 117
 118 // Function to write to MAC indirect registers
 119 UINT32
 120 IndirectMACWrite32 (
 121   UINT32 Index,
 122   UINT32 Value
 123   )
 124 {
 125   UINT32 ValueWritten;
 126   UINT32 MacCSR;
 127
 128   // Check index is in the range
 129   ASSERT(Index <= 12);
 130
 131   // Wait until CSR busy bit is cleared
 132   while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 133
 134   // Set CSR busy bit to ensure read will occur
 135   // Set the R/W bit to indicate we are writing
 136   // Set the index of CSR Address to access desired register
 137   MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index);
 138
 139   // Now write the value to the register before issuing the write command
 140   ValueWritten = MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);
 141
 142   // Write the config to the register
 143   MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);
 144
 145   // Wait until CSR busy bit is cleared
 146   while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);
 147
 148   return ValueWritten;
 149 }
 150
 151 // Function to read from MII register (PHY Access)
 152 UINT32
 153 IndirectPHYRead32 (
 154   UINT32 Index
 155   )
 156 {
 157   UINT32 ValueRead;
 158   UINT32 MiiAcc;
 159
 160   // Check it is a valid index
 161   ASSERT(Index < 31);
 162
 163   // Wait for busy bit to clear
 164   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 165
 166   // Clear the R/W bit to indicate we are reading
 167   // Set the index of the MII register
 168   // Set the PHY Address
 169   // Set the MII busy bit to allow read
 170   MiiAcc = MII_ACC_MII_READ | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;
 171
 172   // Now write this config to register
 173   IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);
 174
 175   // Wait for busy bit to clear
 176   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 177
 178   // Now read the value of the register
 179   ValueRead = (IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_DATA) & 0xFFFF); // only lower 16 bits are valid for any PHY register
 180
 181   return ValueRead;
 182 }
 183
 184
 185 // Function to write to the MII register (PHY Access)
 186 UINT32
 187 IndirectPHYWrite32 (
 188   UINT32 Index,
 189   UINT32 Value
 190   )
 191 {
 192   UINT32 MiiAcc;
 193   UINT32 ValueWritten;
 194
 195   // Check it is a valid index
 196   ASSERT(Index < 31);
 197
 198   // Wait for busy bit to clear
 199   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 200
 201   // Clear the R/W bit to indicate we are reading
 202   // Set the index of the MII register
 203   // Set the PHY Address
 204   // Set the MII busy bit to allow read
 205   MiiAcc = MII_ACC_MII_WRITE | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;
 206
 207   // Write the desired value to the register first
 208   ValueWritten = IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_DATA, (Value & 0xFFFF));
 209
 210   // Now write the config to register
 211   IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);
 212
 213   // Wait for operation to terminate
 214   while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);
 215
 216   return ValueWritten;
 217 }
 218
 219
 220 /* ---------------- EEPROM Operations ------------------ */
 221
 222
 223 // Function to read from EEPROM memory
 224 UINT32
 225 IndirectEEPROMRead32 (
 226   UINT32 Index
 227   )
 228 {
 229   UINT32 EepromCmd;
 230
 231   // Set the busy bit to ensure read will occur
 232   EepromCmd = E2P_EPC_BUSY | E2P_EPC_CMD_READ;
 233
 234   // Set the index to access desired EEPROM memory location
 235   EepromCmd |= E2P_EPC_ADDRESS(Index);
 236
 237   // Write to Eeprom command register
 238   MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);
 239   gBS->Stall (LAN9118_STALL);
 240
 241   // Wait until operation has completed
 242   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 243
 244   // Check that operation didn't time out
 245   if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {
 246     DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index));
 247     return 0;
 248   }
 249
 250   // Wait until operation has completed
 251   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 252
 253   // Finally read the value
 254   return MmioRead32 (LAN9118_E2P_DATA);
 255 }
 256
 257 // Function to write to EEPROM memory
 258 UINT32
 259 IndirectEEPROMWrite32 (
 260   UINT32 Index,
 261   UINT32 Value
 262   )
 263 {
 264   UINT32 ValueWritten;
 265   UINT32 EepromCmd;
 266
 267   ValueWritten = 0;
 268
 269   // Read the EEPROM Command register
 270   EepromCmd = MmioRead32 (LAN9118_E2P_CMD);
 271
 272   // Set the busy bit to ensure read will occur
 273   EepromCmd |= ((UINT32)1 << 31);
 274
 275   // Set the EEPROM command to write(0b011)
 276   EepromCmd &= ~(7 << 28);    // Clear the command first
 277   EepromCmd |= (3 << 28);     // Write 011
 278
 279   // Set the index to access desired EEPROM memory location
 280   EepromCmd |= (Index & 0xF);
 281
 282   // Write the value to the data register first
 283   ValueWritten = MmioWrite32 (LAN9118_E2P_DATA, Value);
 284
 285   // Write to Eeprom command register
 286   MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);
 287   gBS->Stall (LAN9118_STALL);
 288
 289   // Wait until operation has completed
 290   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 291
 292   // Check that operation didn't time out
 293   if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {
 294     DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value));
 295     return 0;
 296   }
 297
 298   // Wait until operation has completed
 299   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 300
 301   return ValueWritten;
 302 }
 303
 304 /* ---------------- General Operations ----------------- */
 305
 306 VOID
 307 Lan9118SetMacAddress (
 308   EFI_MAC_ADDRESS             *Mac,
 309   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 310   )
 311 {
 312   IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRL,
 313                       (Mac->Addr[0] & 0xFF) |
 314                       ((Mac->Addr[1] & 0xFF) << 8) |
 315                       ((Mac->Addr[2] & 0xFF) << 16) |
 316                       ((Mac->Addr[3] & 0xFF) << 24)
 317                     );
 318
 319   IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRH,
 320                       (UINT32)(Mac->Addr[4] & 0xFF) |
 321                       ((Mac->Addr[5] & 0xFF) << 8)
 322                     );
 323 }
 324
 325 VOID
 326 Lan9118ReadMacAddress (
 327   OUT EFI_MAC_ADDRESS *MacAddress
 328   )
 329 {
 330   UINT32          MacAddrHighValue;
 331   UINT32          MacAddrLowValue;
 332
 333   // Read the Mac Addr high register
 334   MacAddrHighValue = (IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRH) & 0xFFFF);
 335   // Read the Mac Addr low register
 336   MacAddrLowValue = IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRL);
 337
 338   SetMem (MacAddress, sizeof(*MacAddress), 0);
 339   MacAddress->Addr[0] = (MacAddrLowValue & 0xFF);
 340   MacAddress->Addr[1] = (MacAddrLowValue & 0xFF00) >> 8;
 341   MacAddress->Addr[2] = (MacAddrLowValue & 0xFF0000) >> 16;
 342   MacAddress->Addr[3] = (MacAddrLowValue & 0xFF000000) >> 24;
 343   MacAddress->Addr[4] = (MacAddrHighValue & 0xFF);
 344   MacAddress->Addr[5] = (MacAddrHighValue & 0xFF00) >> 8;
 345 }
 346
 347 /*
 348  *  Power up the 9118 and find its MAC address.
 349  *
 350  *  This operation can be carried out when the LAN9118 is in any power state
 351  *
 352  */
 353 EFI_STATUS
 354 Lan9118Initialize (
 355   IN  EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 356   )
 357 {
 358   UINTN  Timeout;
 359   UINT64 DefaultMacAddress;
 360
 361   // Attempt to wake-up the device if it is in a lower power state
 362   if (((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {
 363     DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));
 364     MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);
 365     gBS->Stall (LAN9118_STALL);
 366   }
 367
 368   // Check that device is active
 369   Timeout = 20;
 370   while ((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Timeout) {
 371     gBS->Stall (LAN9118_STALL);
 372   }
 373   if (!Timeout) {
 374     return EFI_TIMEOUT;
 375   }
 376
 377   // Check that EEPROM isn't active
 378   Timeout = 20;
 379   while ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Timeout){
 380     gBS->Stall (LAN9118_STALL);
 381   }
 382   if (!Timeout) {
 383     return EFI_TIMEOUT;
 384   }
 385
 386   // Check if a MAC address was loaded from EEPROM, and if it was, set it as the
 387   // current address.
 388   if ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {
 389     DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n"));
 390
 391     // If we had an address before (set by StationAddess), continue to use it
 392     if (CompareMem (&Snp->Mode->CurrentAddress, &mZeroMac, NET_ETHER_ADDR_LEN)) {
 393       Lan9118SetMacAddress (&Snp->Mode->CurrentAddress, Snp);
 394     } else {
 395       // If there are no cached addresses, then fall back to a default
 396       DEBUG ((EFI_D_WARN, "Warning: using driver-default MAC address\n"));
 397       DefaultMacAddress = FixedPcdGet64 (PcdLan9118DefaultMacAddress);
 398       Lan9118SetMacAddress((EFI_MAC_ADDRESS *) &DefaultMacAddress, Snp);
 399       CopyMem (&Snp->Mode->CurrentAddress, &DefaultMacAddress, NET_ETHER_ADDR_LEN);
 400     }
 401   } else {
 402     // Store the MAC address that was loaded from EEPROM
 403     Lan9118ReadMacAddress (&Snp->Mode->CurrentAddress);
 404     CopyMem (&Snp->Mode->PermanentAddress, &Snp->Mode->CurrentAddress, NET_ETHER_ADDR_LEN);
 405   }
 406
 407   // Clear and acknowledge interrupts
 408   MmioWrite32 (LAN9118_INT_EN, 0);
 409   MmioWrite32 (LAN9118_IRQ_CFG, 0);
 410   MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);
 411
 412   // Do self tests here?
 413
 414   return EFI_SUCCESS;
 415 }
 416
 417
 418 // Perform software reset on the LAN9118
 419 // Return 0 on success, -1 on error
 420 EFI_STATUS
 421 SoftReset (
 422   UINT32 Flags,
 423   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 424   )
 425 {
 426   UINT32 HwConf;
 427   UINT32 ResetTime;
 428
 429   // Initialize variable
 430   ResetTime = 0;
 431
 432   // Stop Rx and Tx
 433   StopTx (STOP_TX_MAC | STOP_TX_CFG | STOP_TX_CLEAR, Snp);
 434   StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO
 435
 436   // Issue the reset
 437   HwConf = MmioRead32 (LAN9118_HW_CFG);
 438   HwConf |= 1;
 439
 440   // Set the Must Be One (MBO) bit
 441   if (((HwConf & HWCFG_MBO) >> 20) == 0) {
 442     HwConf |= HWCFG_MBO;
 443   }
 444
 445   // Check that EEPROM isn't active
 446   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 447
 448   // Write the configuration
 449   MmioWrite32 (LAN9118_HW_CFG, HwConf);
 450   gBS->Stall (LAN9118_STALL);
 451
 452   // Wait for reset to complete
 453   while (MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {
 454
 455     gBS->Stall (LAN9118_STALL);
 456     ResetTime += 1;
 457
 458     // If time taken exceeds 100us, then there was an error condition
 459     if (ResetTime > 1000) {
 460       Snp->Mode->State = EfiSimpleNetworkStopped;
 461       return EFI_TIMEOUT;
 462     }
 463   }
 464
 465   // Check that EEPROM isn't active
 466   while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
 467
 468   // TODO we probably need to re-set the mac address here.
 469
 470   // Clear and acknowledge all interrupts
 471   if (Flags & SOFT_RESET_CLEAR_INT) {
 472     MmioWrite32 (LAN9118_INT_EN, 0);
 473     MmioWrite32 (LAN9118_IRQ_CFG, 0);
 474     MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);
 475   }
 476
 477   // Do self tests here?
 478   if (Flags & SOFT_RESET_SELF_TEST) {
 479
 480   }
 481
 482   return EFI_SUCCESS;
 483 }
 484
 485
 486 // Perform PHY software reset
 487 EFI_STATUS
 488 PhySoftReset (
 489   UINT32 Flags,
 490   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 491   )
 492 {
 493   UINT32 PmtCtrl = 0;
 494   UINT32 LinkTo = 0;
 495
 496   // PMT PHY reset takes precedence over BCR
 497   if (Flags & PHY_RESET_PMT) {
 498     PmtCtrl = MmioRead32 (LAN9118_PMT_CTRL);
 499     PmtCtrl |= MPTCTRL_PHY_RST;
 500     MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);
 501
 502     // Wait for completion
 503     while (MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {
 504       gBS->Stall (LAN9118_STALL);
 505     }
 506   // PHY Basic Control Register reset
 507   } else if (Flags & PHY_RESET_BCR) {
 508     IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PHYCR_RESET);
 509
 510     // Wait for completion
 511     while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {
 512       gBS->Stall (LAN9118_STALL);
 513     }
 514   }
 515
 516   // Check the link status
 517   if (Flags & PHY_RESET_CHECK_LINK) {
 518     LinkTo = 100000; // 2 second (could be 50% more)
 519     while (EFI_ERROR (CheckLinkStatus (0, Snp)) && (LinkTo > 0)) {
 520       gBS->Stall (LAN9118_STALL);
 521       LinkTo--;
 522     }
 523
 524     // Timed out
 525     if (LinkTo <= 0) {
 526       return EFI_TIMEOUT;
 527     }
 528   }
 529
 530   // Clear and acknowledge all interrupts
 531   if (Flags & PHY_SOFT_RESET_CLEAR_INT) {
 532     MmioWrite32 (LAN9118_INT_EN, 0);
 533     MmioWrite32 (LAN9118_IRQ_CFG, 0);
 534     MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);
 535   }
 536
 537   return EFI_SUCCESS;
 538 }
 539
 540
 541 // Configure hardware for LAN9118
 542 EFI_STATUS
 543 ConfigureHardware (
 544   UINT32 Flags,
 545   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 546   )
 547 {
 548   UINT32 GpioConf;
 549
 550   // Check if we want to use LEDs on GPIO
 551   if (Flags & HW_CONF_USE_LEDS) {
 552     GpioConf = MmioRead32 (LAN9118_GPIO_CFG);
 553
 554     // Enable GPIO as LEDs and Config as Push-Pull driver
 555     GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL |
 556                 GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE;
 557
 558     // Write the configuration
 559     MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);
 560     gBS->Stall (LAN9118_STALL);
 561   }
 562
 563   return EFI_SUCCESS;
 564 }
 565
 566 // Configure flow control
 567 EFI_STATUS
 568 ConfigureFlow (
 569   UINT32 Flags,
 570   UINT32 HighTrig,
 571   UINT32 LowTrig,
 572   UINT32 BPDuration,
 573   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 574   )
 575 {
 576   return EFI_SUCCESS;
 577 }
 578
 579 // Do auto-negotiation
 580 EFI_STATUS
 581 AutoNegotiate (
 582   UINT32 Flags,
 583   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 584   )
 585 {
 586   UINT32 PhyControl;
 587   UINT32 PhyStatus;
 588   UINT32 Features;
 589   UINT32 TimeOut;
 590
 591   // First check that auto-negotiation is supported
 592   PhyStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);
 593   if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) {
 594     DEBUG ((EFI_D_ERROR, "Auto-negotiation not supported.\n"));
 595     return EFI_DEVICE_ERROR;
 596   }
 597
 598   // Check that link is up first
 599   if ((PhyStatus & PHYSTS_LINK_STS) == 0) {
 600     // Wait until it is up or until Time Out
 601     TimeOut = 2000;
 602     while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {
 603       gBS->Stall (LAN9118_STALL);
 604       TimeOut--;
 605       if (!TimeOut) {
 606         DEBUG ((EFI_D_ERROR, "Link timeout in auto-negotiation.\n"));
 607         return EFI_TIMEOUT;
 608       }
 609     }
 610   }
 611
 612   // Configure features to advertise
 613   Features = IndirectPHYRead32 (PHY_INDEX_AUTO_NEG_ADVERT);
 614
 615   if ((Flags & AUTO_NEGOTIATE_ADVERTISE_ALL) > 0) {
 616     // Link speed capabilities
 617     Features |= (PHYANA_10BASET | PHYANA_10BASETFD | PHYANA_100BASETX | PHYANA_100BASETXFD);
 618
 619     // Pause frame capabilities
 620     Features &= ~(PHYANA_PAUSE_OP_MASK);
 621     Features |= 3 << 10;
 622   }
 623
 624   // Write the features
 625   IndirectPHYWrite32 (PHY_INDEX_AUTO_NEG_ADVERT, Features);
 626
 627   // Read control register
 628   PhyControl = IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL);
 629
 630   // Enable Auto-Negotiation
 631   if ((PhyControl & PHYCR_AUTO_EN) == 0) {
 632     PhyControl |= PHYCR_AUTO_EN;
 633   }
 634
 635   // Restart auto-negotiation
 636   PhyControl |= PHYCR_RST_AUTO;
 637
 638   // Enable collision test if required to do so
 639   if (Flags & AUTO_NEGOTIATE_COLLISION_TEST) {
 640     PhyControl |= PHYCR_COLL_TEST;
 641   } else {
 642     PhyControl &= ~ PHYCR_COLL_TEST;
 643   }
 644
 645   // Write this configuration
 646   IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PhyControl);
 647
 648   // Wait until process has completed
 649   while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0);
 650
 651   return EFI_SUCCESS;
 652 }
 653
 654 // Check the Link Status and take appropriate action
 655 EFI_STATUS
 656 CheckLinkStatus (
 657   UINT32 Flags,
 658   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 659   )
 660 {
 661   // Get the PHY Status
 662   UINT32 PhyBStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);
 663
 664   if (PhyBStatus & PHYSTS_LINK_STS) {
 665     return EFI_SUCCESS;
 666   } else {
 667     return EFI_DEVICE_ERROR;
 668   }
 669 }
 670
 671 // Stop the transmitter
 672 EFI_STATUS
 673 StopTx (
 674   UINT32 Flags,
 675   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 676   )
 677 {
 678   UINT32 MacCsr;
 679   UINT32 TxCfg;
 680
 681   MacCsr = 0;
 682   TxCfg = 0;
 683
 684   // Check if we want to clear tx
 685   if (Flags & STOP_TX_CLEAR) {
 686     TxCfg = MmioRead32 (LAN9118_TX_CFG);
 687     TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;
 688     MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 689     gBS->Stall (LAN9118_STALL);
 690   }
 691
 692   // Check if already stopped
 693   if (Flags & STOP_TX_MAC) {
 694     MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 695
 696     if (MacCsr & MACCR_TX_EN) {
 697       MacCsr &= ~MACCR_TX_EN;
 698       IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 699     }
 700   }
 701
 702   if (Flags & STOP_TX_CFG) {
 703     TxCfg = MmioRead32 (LAN9118_TX_CFG);
 704
 705     if (TxCfg & TXCFG_TX_ON) {
 706       TxCfg |= TXCFG_STOP_TX;
 707       MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 708       gBS->Stall (LAN9118_STALL);
 709
 710       // Wait for Tx to finish transmitting
 711       while (MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);
 712     }
 713   }
 714
 715   return EFI_SUCCESS;
 716 }
 717
 718 // Stop the receiver
 719 EFI_STATUS
 720 StopRx (
 721   UINT32 Flags,
 722   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 723   )
 724 {
 725   UINT32 MacCsr;
 726   UINT32 RxCfg;
 727
 728   RxCfg = 0;
 729
 730   // Check if already stopped
 731   MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 732
 733   if (MacCsr & MACCR_RX_EN) {
 734     MacCsr &= ~ MACCR_RX_EN;
 735     IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 736   }
 737
 738   // Check if we want to clear receiver FIFOs
 739   if (Flags & STOP_RX_CLEAR) {
 740     RxCfg = MmioRead32 (LAN9118_RX_CFG);
 741     RxCfg |= RXCFG_RX_DUMP;
 742     MmioWrite32 (LAN9118_RX_CFG, RxCfg);
 743     gBS->Stall (LAN9118_STALL);
 744
 745     while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);
 746   }
 747
 748   return EFI_SUCCESS;
 749 }
 750
 751 // Start the transmitter
 752 EFI_STATUS
 753 StartTx (
 754   UINT32 Flags,
 755   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 756   )
 757 {
 758   UINT32 MacCsr;
 759   UINT32 TxCfg;
 760
 761   MacCsr = 0;
 762   TxCfg = 0;
 763
 764   // Check if we want to clear tx
 765   if (Flags & START_TX_CLEAR) {
 766     TxCfg = MmioRead32 (LAN9118_TX_CFG);
 767     TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;
 768     MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 769     gBS->Stall (LAN9118_STALL);
 770   }
 771
 772   // Check if tx was started from MAC and enable if not
 773   if (Flags & START_TX_MAC) {
 774     MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 775     gBS->Stall (LAN9118_STALL);
 776     if ((MacCsr & MACCR_TX_EN) == 0) {
 777       MacCsr |= MACCR_TX_EN;
 778       IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 779       gBS->Stall (LAN9118_STALL);
 780     }
 781   }
 782
 783   // Check if tx was started from TX_CFG and enable if not
 784   if (Flags & START_TX_CFG) {
 785     TxCfg = MmioRead32 (LAN9118_TX_CFG);
 786     gBS->Stall (LAN9118_STALL);
 787     if ((TxCfg & TXCFG_TX_ON) == 0) {
 788       TxCfg |= TXCFG_TX_ON;
 789       MmioWrite32 (LAN9118_TX_CFG, TxCfg);
 790       gBS->Stall (LAN9118_STALL);
 791     }
 792   }
 793
 794   // Set the tx data trigger level
 795
 796   return EFI_SUCCESS;
 797 }
 798
 799 // Start the receiver
 800 EFI_STATUS
 801 StartRx (
 802   UINT32 Flags,
 803   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 804   )
 805 {
 806   UINT32 MacCsr;
 807   UINT32 RxCfg;
 808
 809   RxCfg = 0;
 810
 811   // Check if already started
 812   MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
 813
 814   if ((MacCsr & MACCR_RX_EN) == 0) {
 815     // Check if we want to clear receiver FIFOs before starting
 816     if (Flags & START_RX_CLEAR) {
 817       RxCfg = MmioRead32 (LAN9118_RX_CFG);
 818       RxCfg |= RXCFG_RX_DUMP;
 819       MmioWrite32 (LAN9118_RX_CFG, RxCfg);
 820       gBS->Stall (LAN9118_STALL);
 821
 822       while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);
 823     }
 824
 825     MacCsr |= MACCR_RX_EN;
 826     IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
 827     gBS->Stall (LAN9118_STALL);
 828   }
 829
 830   return EFI_SUCCESS;
 831 }
 832
 833 // Check Tx Data available space
 834 UINT32
 835 TxDataFreeSpace (
 836   UINT32 Flags,
 837   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 838   )
 839 {
 840   UINT32 TxInf;
 841   UINT32 FreeSpace;
 842
 843   // Get the amount of free space from information register
 844   TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);
 845   FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK);
 846
 847   return FreeSpace; // Value in bytes
 848 }
 849
 850 // Check Tx Status used space
 851 UINT32
 852 TxStatusUsedSpace (
 853   UINT32 Flags,
 854   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 855   )
 856 {
 857   UINT32 TxInf;
 858   UINT32 UsedSpace;
 859
 860   // Get the amount of used space from information register
 861   TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);
 862   UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16;
 863
 864   return UsedSpace << 2; // Value in bytes
 865 }
 866
 867 // Check Rx Data used space
 868 UINT32
 869 RxDataUsedSpace (
 870   UINT32 Flags,
 871   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 872   )
 873 {
 874   UINT32 RxInf;
 875   UINT32 UsedSpace;
 876
 877   // Get the amount of used space from information register
 878   RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);
 879   UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK);
 880
 881   return UsedSpace; // Value in bytes (rounded up to nearest DWORD)
 882 }
 883
 884 // Check Rx Status used space
 885 UINT32
 886 RxStatusUsedSpace (
 887   UINT32 Flags,
 888   EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 889   )
 890 {
 891   UINT32 RxInf;
 892   UINT32 UsedSpace;
 893
 894   // Get the amount of used space from information register
 895   RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);
 896   UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16;
 897
 898   return UsedSpace << 2; // Value in bytes
 899 }
 900
 901
 902 // Change the allocation of FIFOs
 903 EFI_STATUS
 904 ChangeFifoAllocation (
 905   IN      UINT32 Flags,
 906   IN  OUT UINTN  *TxDataSize    OPTIONAL,
 907   IN  OUT UINTN  *RxDataSize    OPTIONAL,
 908   IN  OUT UINT32 *TxStatusSize  OPTIONAL,
 909   IN  OUT UINT32 *RxStatusSize  OPTIONAL,
 910   IN  OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp
 911   )
 912 {
 913   UINT32 HwConf;
 914   UINT32 TxFifoOption;
 915
 916   // Check that desired sizes don't exceed limits
 917   if (*TxDataSize > TX_FIFO_MAX_SIZE)
 918     return EFI_INVALID_PARAMETER;
 919
 920 #if defined(RX_FIFO_MIN_SIZE) && defined(RX_FIFO_MAX_SIZE)
 921   if (*RxDataSize > RX_FIFO_MAX_SIZE) {
 922     return EFI_INVALID_PARAMETER;
 923   }
 924 #endif
 925
 926   if (Flags & ALLOC_USE_DEFAULT) {
 927     return EFI_SUCCESS;
 928   }
 929
 930   // If we use the FIFOs (always use this first)
 931   if (Flags & ALLOC_USE_FIFOS) {
 932     // Read the current value of allocation
 933     HwConf = MmioRead32 (LAN9118_HW_CFG);
 934     TxFifoOption = (HwConf >> 16) & 0xF;
 935
 936     // Choose the correct size (always use larger than requested if possible)
 937     if (*TxDataSize < TX_FIFO_MIN_SIZE) {
 938       *TxDataSize = TX_FIFO_MIN_SIZE;
 939       *RxDataSize = 13440;
 940       *RxStatusSize = 896;
 941       TxFifoOption = 2;
 942     } else if ((*TxDataSize > TX_FIFO_MIN_SIZE) && (*TxDataSize <= 2560)) {
 943       *TxDataSize = 2560;
 944       *RxDataSize = 12480;
 945       *RxStatusSize = 832;
 946       TxFifoOption = 3;
 947     } else if ((*TxDataSize > 2560) && (*TxDataSize <= 3584)) {
 948       *TxDataSize = 3584;
 949       *RxDataSize = 11520;
 950       *RxStatusSize = 768;
 951       TxFifoOption = 4;
 952     } else if ((*TxDataSize > 3584) && (*TxDataSize <= 4608)) { // default option
 953       *TxDataSize = 4608;
 954       *RxDataSize = 10560;
 955       *RxStatusSize = 704;
 956       TxFifoOption = 5;
 957     } else if ((*TxDataSize > 4608) && (*TxDataSize <= 5632)) {
 958       *TxDataSize = 5632;
 959       *RxDataSize = 9600;
 960       *RxStatusSize = 640;
 961       TxFifoOption = 6;
 962     } else if ((*TxDataSize > 5632) && (*TxDataSize <= 6656)) {
 963       *TxDataSize = 6656;
 964       *RxDataSize = 8640;
 965       *RxStatusSize = 576;
 966       TxFifoOption = 7;
 967     } else if ((*TxDataSize > 6656) && (*TxDataSize <= 7680)) {
 968       *TxDataSize = 7680;
 969       *RxDataSize = 7680;
 970       *RxStatusSize = 512;
 971       TxFifoOption = 8;
 972     } else if ((*TxDataSize > 7680) && (*TxDataSize <= 8704)) {
 973       *TxDataSize = 8704;
 974       *RxDataSize = 6720;
 975       *RxStatusSize = 448;
 976       TxFifoOption = 9;
 977     } else if ((*TxDataSize > 8704) && (*TxDataSize <= 9728)) {
 978       *TxDataSize = 9728;
 979       *RxDataSize = 5760;
 980       *RxStatusSize = 384;
 981       TxFifoOption = 10;
 982     } else if ((*TxDataSize > 9728) && (*TxDataSize <= 10752)) {
 983       *TxDataSize = 10752;
 984       *RxDataSize = 4800;
 985       *RxStatusSize = 320;
 986       TxFifoOption = 11;
 987     } else if ((*TxDataSize > 10752) && (*TxDataSize <= 11776)) {
 988       *TxDataSize = 11776;
 989       *RxDataSize = 3840;
 990       *RxStatusSize = 256;
 991       TxFifoOption = 12;
 992     } else if ((*TxDataSize > 11776) && (*TxDataSize <= 12800)) {
 993       *TxDataSize = 12800;
 994       *RxDataSize = 2880;
 995       *RxStatusSize = 192;
 996       TxFifoOption = 13;
 997     } else if ((*TxDataSize > 12800) && (*TxDataSize <= 13824)) {
 998       *TxDataSize = 13824;
 999       *RxDataSize = 1920;
1000       *RxStatusSize = 128;
1001       TxFifoOption = 14;
1002     }
1003   } else {
1004     ASSERT(0); // Untested code path
1005     HwConf = 0;
1006     TxFifoOption = 0;
1007   }
1008
1009   // Do we need DMA?
1010   if (Flags & ALLOC_USE_DMA) {
1011     return EFI_UNSUPPORTED; // Unsupported as of now
1012   }
1013   // Clear and assign the new size option
1014   HwConf &= ~(0xF0000);
1015   HwConf |= ((TxFifoOption & 0xF) << 16);
1016   MmioWrite32 (LAN9118_HW_CFG, HwConf);
1017   gBS->Stall (LAN9118_STALL);
1018
1019   return EFI_SUCCESS;
1020 }