EmbeddedPkg/TemplateCpuDxe/Arm/Exception.c

   1 /** @file
   2
   3   Copyright (c) 2008-2009, Apple Inc. All rights reserved.
   4
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <CpuDxe.h>
  16 #include <Library/CacheMaintenanceLib.h>
  17
  18 VOID
  19 ExceptionHandlersStart (
  20         VOID
  21         );
  22
  23 VOID
  24 ExceptionHandlersEnd (
  25         VOID
  26         );
  27
  28 VOID
  29 CommonExceptionEntry (
  30         VOID
  31         );
  32
  33 VOID
  34 AsmCommonExceptionEntry (
  35         VOID
  36         );
  37
  38
  39 EFI_EXCEPTION_CALLBACK  gExceptionHandlers[MAX_ARM_EXCEPTION + 1];
  40
  41
  42 /**
  43   This function registers and enables the handler specified by InterruptHandler for a processor
  44   interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
  45   handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
  46   The installed handler is called once for each processor interrupt or exception.
  47
  48   @param  InterruptType    A pointer to the processor's current interrupt state. Set to TRUE if interrupts
  49                            are enabled and FALSE if interrupts are disabled.
  50   @param  InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
  51                            when a processor interrupt occurs. If this parameter is NULL, then the handler
  52                            will be uninstalled.
  53
  54   @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.
  55   @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was
  56                                 previously installed.
  57   @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
  58                                 previously installed.
  59   @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported.
  60
  61 **/
  62 EFI_STATUS
  63 RegisterInterruptHandler (
  64   IN EFI_EXCEPTION_TYPE             InterruptType,
  65   IN EFI_CPU_INTERRUPT_HANDLER      InterruptHandler
  66   )
  67 {
  68         if (InterruptType > MAX_ARM_EXCEPTION) {
  69                 return EFI_UNSUPPORTED;
  70         }
  71
  72         if ((InterruptHandler == NULL) && (gExceptionHandlers[InterruptType] == NULL)) {
  73                 return EFI_INVALID_PARAMETER;
  74         }
  75
  76         if ((InterruptHandler != NULL) && (gExceptionHandlers[InterruptType] != NULL)) {
  77                 return EFI_ALREADY_STARTED;
  78         }
  79
  80         gExceptionHandlers[InterruptType] = InterruptHandler;
  81
  82         return EFI_SUCCESS;
  83 }
  84
  85
  86
  87
  88 VOID
  89 EFIAPI
  90 DefaultSWIExceptionHandler(
  91         IN     EFI_EXCEPTION_TYPE                                               ExceptionType,
  92         IN OUT EFI_SYSTEM_CONTEXT                                               SystemContext
  93         )
  94 {
  95         return;
  96 }
  97
  98
  99 VOID
 100 EFIAPI
 101 DefaultExceptionHandler(
 102         IN     EFI_EXCEPTION_TYPE                                               ExceptionType,
 103         IN OUT EFI_SYSTEM_CONTEXT                                               SystemContext
 104         )
 105 {
 106         DEBUG ((EFI_D_ERROR, "Exception %d from %x\n", ExceptionType, SystemContext.SystemContextArm->PC));
 107   ASSERT (FALSE);
 108
 109         return;
 110 }
 111
 112
 113
 114 EFI_STATUS
 115 InitializeExceptions (
 116         IN EFI_CPU_ARCH_PROTOCOL    *Cpu
 117         )
 118 {
 119         EFI_STATUS    Status = EFI_SUCCESS;
 120         UINTN                                   Offset;
 121         UINTN                                   Length;
 122         UINTN                                   Index;
 123         BOOLEAN                         Enabled;
 124
 125   //
 126   // Disable interrupts
 127   //
 128         Cpu->GetInterruptState (Cpu, &Enabled);
 129   Cpu->DisableInterrupt (Cpu);
 130
 131   //
 132   // Initialize the C entry points for interrupts
 133   //
 134         for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {
 135     if (Index == EXCEPT_ARM_SOFTWARE_INTERRUPT) {
 136       Status = Cpu->RegisterInterruptHandler (Cpu, Index, DefaultSWIExceptionHandler);
 137     } else {
 138       Status = Cpu->RegisterInterruptHandler (Cpu, Index, DefaultExceptionHandler);
 139                 }
 140                 ASSERT_EFI_ERROR (Status);
 141         }
 142
 143         //
 144         // Copy an implementation of the ARM exception vectors to 0x0.
 145         //
 146         Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;
 147
 148         CopyMem ((VOID *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress), (VOID *)ExceptionHandlersStart, Length);
 149
 150   //
 151   // Patch in the common Assembly exception handler
 152   //
 153         Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;
 154         *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress)  + Offset) = (UINTN)AsmCommonExceptionEntry;
 155
 156   //
 157   // Flush Caches since we updated executable stuff
 158   //
 159         InvalidateInstructionCache ();
 160
 161         if (Enabled) {
 162           //
 163           // Restore interrupt state
 164           //
 165                 Status = Cpu->EnableInterrupt (Cpu);
 166         }
 167
 168         return Status;
 169 }
 170
 171
 172
 173 /**
 174   This function reads the processor timer specified by TimerIndex and returns it in TimerValue.
 175
 176   @param  TimerIndex       Specifies which processor timer is to be returned in TimerValue. This parameter
 177                            must be between 0 and NumberOfTimers-1.
 178   @param  TimerValue       Pointer to the returned timer value.
 179   @param  TimerPeriod      A pointer to the amount of time that passes in femtoseconds for each increment
 180                            of TimerValue.
 181
 182   @retval EFI_SUCCESS           The processor timer value specified by TimerIndex was returned in TimerValue.
 183   @retval EFI_DEVICE_ERROR      An error occurred attempting to read one of the processor's timers.
 184   @retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.
 185   @retval EFI_UNSUPPORTED       The processor does not have any readable timers.
 186
 187 **/
 188 EFI_STATUS
 189 EFIAPI
 190 GetTimerValue (
 191   IN  UINT32                         TimerIndex,
 192   OUT UINT64                         *TimerValue,
 193   OUT UINT64                         *TimerPeriod   OPTIONAL
 194   )
 195 {
 196   return EFI_UNSUPPORTED;
 197 }
 198
 199
 200 /**
 201   This function flushes the range of addresses from Start to Start+Length
 202   from the processor's data cache. If Start is not aligned to a cache line
 203   boundary, then the bytes before Start to the preceding cache line boundary
 204   are also flushed. If Start+Length is not aligned to a cache line boundary,
 205   then the bytes past Start+Length to the end of the next cache line boundary
 206   are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
 207   supported. If the data cache is fully coherent with all DMA operations, then
 208   this function can just return EFI_SUCCESS. If the processor does not support
 209   flushing a range of the data cache, then the entire data cache can be flushed.
 210
 211   @param  Start            The beginning physical address to flush from the processor's data
 212                            cache.
 213   @param  Length           The number of bytes to flush from the processor's data cache. This
 214                            function may flush more bytes than Length specifies depending upon
 215                            the granularity of the flush operation that the processor supports.
 216   @param  FlushType        Specifies the type of flush operation to perform.
 217
 218   @retval EFI_SUCCESS           The address range from Start to Start+Length was flushed from
 219                                 the processor's data cache.
 220   @retval EFI_UNSUPPORTED       The processor does not support the cache flush type specified
 221                                 by FlushType.
 222   @retval EFI_DEVICE_ERROR      The address range from Start to Start+Length could not be flushed
 223                                 from the processor's data cache.
 224
 225 **/
 226 EFI_STATUS
 227 EFIAPI
 228 FlushCpuDataCache (
 229   IN EFI_PHYSICAL_ADDRESS            Start,
 230   IN UINT64                          Length,
 231   IN EFI_CPU_FLUSH_TYPE              FlushType
 232   )
 233 {
 234   if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
 235     WriteBackInvalidateDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);
 236     return EFI_SUCCESS;
 237   } else if (FlushType == EfiCpuFlushTypeInvalidate) {
 238     InvalidateDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);
 239     return EFI_SUCCESS;
 240   } else if (FlushType == EfiCpuFlushTypeWriteBack) {
 241     WriteBackDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);
 242     return EFI_SUCCESS;
 243   } else {
 244     return EFI_UNSUPPORTED;
 245   }
 246 }
 247
 248
 249
 250