3 Copyright (c) 2006, Intel Corporation. All rights reserved.
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
23 #ifndef _PEI_RECOVERY_FDC_H
24 #define _PEI_RECOVERY_FDC_H
29 #define FDC_REGISTER_DOR 2 // 0x3F2 //Digital Output Register
30 #define FDC_REGISTER_MSR 4 // 0x3F4 //Main Status Register
31 #define FDC_REGISTER_DTR 5 // 0x3F5 //Data Register
32 #define FDC_REGISTER_CCR 7 // 0x3F7 //Configuration Control Register(data rate select)
33 #define FDC_REGISTER_DIR 7 // 0x3F7 //Digital Input Register(diskchange)
35 // FDC Register Bit Definitions
38 // Digital Out Register(WO)
40 #define SELECT_DRV BIT0 // Select Drive: 0=A 1=B
41 #define RESET_FDC BIT2 // Reset FDC
42 #define INT_DMA_ENABLE BIT3 // Enable Int & DMA
43 #define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor
44 #define DRVB_MOTOR_ON BIT5 // Turn On Drive B Motor
46 // Main Status Register(RO)
48 #define MSR_DAB BIT0 // Drive A Busy
49 #define MSR_DBB BIT1 // Drive B Busy
50 #define MSR_CB BIT4 // FDC Busy
51 #define MSR_NDM BIT5 // Non-DMA Mode
52 #define MSR_DIO BIT6 // Data Input/Output
53 #define MSR_RQM BIT7 // Request For Master
55 // Configuration Control Register(WO)
57 #define CCR_DRC (BIT0 | BIT1) // Data Rate select
59 // Digital Input Register(RO)
61 #define DIR_DCL BIT7 // Disk change line
62 #define DRC_500KBS 0x0 // 500K
63 #define DRC_300KBS 0x01 // 300K
64 #define DRC_250KBS 0x02 // 250K
68 #define READ_DATA_CMD 0x06
70 #define RECALIBRATE_CMD 0x07
71 #define SENSE_INT_STATUS_CMD 0x08
72 #define SPECIFY_CMD 0x03
73 #define SENSE_DRV_STATUS_CMD 0x04
76 // CMD_MT: Multi_Track Selector
77 // when set , this flag selects the multi-track operating mode.
78 // In this mode, the FDC treats a complete cylinder under head0 and 1 as a single track
83 // CMD_MFM: MFM/FM Mode Selector
84 // A one selects the double density(MFM) mode
85 // A zero selects single density (FM) mode
91 // When set to 1, sectors containing a deleted data address mark will automatically be skipped
92 // during the execution of Read Data.
93 // When set to 0, the sector is read or written the same as the read and write commands.
98 // FDC Status Register Bit Definitions
103 #define STS0_IC (BIT7 | BIT6) // Interrupt Code
104 #define STS0_SE BIT5 // Seek End: the FDC completed a seek or recalibrate command
105 #define STS0_EC BIT4 // Equipment Check
106 #define STS0_NR BIT3 // Not Ready(unused), this bit is always 0
107 #define STS0_HA BIT2 // Head Address: the current head address
108 // STS0_US1 & STS0_US0: Drive Select(the current selected drive)
110 #define STS0_US1 BIT1 // Unit Select1
111 #define STS0_US0 BIT0 // Unit Select0
115 #define STS1_EN BIT7 // End of Cylinder
118 #define STS1_DE BIT5 // Data Error: The FDC detected a CRC error in either the ID field or data field of a sector
119 #define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval
122 #define STS1_ND BIT2 // No data
123 #define STS1_NW BIT1 // Not Writable
124 #define STS1_MA BIT0 // Missing Address Mark
130 #define STS2_CM BIT6 // Control Mark
131 #define STS2_DD BIT5 // Data Error in Data Field: The FDC detected a CRC error in the data field
132 #define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC
133 // #define STS2_SH BIT3 // Scan Equal Hit
134 // #define STS2_SN BIT2 // Scan Not Satisfied
138 #define STS2_BC BIT1 // Bad Cylinder
139 #define STS2_MD BIT0 // Missing Address Mark in DataField
141 // #define STS3_FT BIT7 // Fault
144 #define STS3_WP BIT6 // Write Protected
145 // #define STS3_RDY BIT5 // Ready
148 #define STS3_T0 BIT4 // Track 0
149 // #define STS3_TS BIT3 // Two Side
152 #define STS3_HD BIT2 // Head Address
153 // STS3_US1 & STS3_US0 : Drive Select
155 #define STS3_US1 BIT1 // Unit Select1
156 #define STS3_US0 BIT0 // Unit Select0
158 // Status Register 0 Interrupt Code Description
160 #define IC_NT 0x0 // Normal Termination of Command
161 #define IC_AT 0x40 // Abnormal Termination of Command
162 #define IC_IC 0x80 // Invalid Command
163 #define IC_ATRC 0xC0 // Abnormal Termination caused by Polling
165 UINT8 EOT
; // End of track
166 UINT8 GPL
; // Gap length
167 UINT8 DTL
; // Data length
168 UINT8 Number
; // Number of bytes per sector
170 UINT8 MotorStartTime
;
172 UINT8 HeadSettlingTime
;
173 UINT8 DataTransferRate
;
186 } FDC_COMMAND_PACKET1
;
191 } FDC_COMMAND_PACKET2
;