IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/Fdc.h

   1 /** @file
   2 Definition of FDC registers and structures.
   3
   4 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
   5
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions
   8 of the BSD License which accompanies this distribution.  The
   9 full text of the license may be found at
  10 http://opensource.org/licenses/bsd-license.php
  11
  12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #ifndef _PEI_RECOVERY_FDC_H_
  18 #define _PEI_RECOVERY_FDC_H_
  19
  20 //
  21 // FDC Registers
  22 //
  23 #define FDC_REGISTER_DOR  2 //Digital Output Register
  24 #define FDC_REGISTER_MSR  4 //Main Status Register
  25 #define FDC_REGISTER_DTR  5 //Data Register
  26 #define FDC_REGISTER_CCR  7 //Configuration Control Register(data rate select)
  27 #define FDC_REGISTER_DIR  7 //Digital Input Register(diskchange)
  28 //
  29 // FDC Register Bit Definitions
  30 //
  31 //
  32 // Digital Out Register(WO)
  33 //
  34 #define SELECT_DRV      BIT0  // Select Drive: 0=A 1=B
  35 #define RESET_FDC       BIT2  // Reset FDC
  36 #define INT_DMA_ENABLE  BIT3  // Enable Int & DMA
  37 #define DRVA_MOTOR_ON   BIT4  // Turn On Drive A Motor
  38 #define DRVB_MOTOR_ON   BIT5  // Turn On Drive B Motor
  39 //
  40 // Main Status Register(RO)
  41 //
  42 #define MSR_DAB BIT0  // Drive A Busy
  43 #define MSR_DBB BIT1  // Drive B Busy
  44 #define MSR_CB  BIT4  // FDC Busy
  45 #define MSR_NDM BIT5  // Non-DMA Mode
  46 #define MSR_DIO BIT6  // Data Input/Output
  47 #define MSR_RQM BIT7  // Request For Master
  48 //
  49 // Configuration Control Register(WO)
  50 //
  51 #define CCR_DRC (BIT0 | BIT1) // Data Rate select
  52 //
  53 // Digital Input Register(RO)
  54 //
  55 #define DIR_DCL     BIT7  // Disk change line
  56 #define DRC_500KBS  0x0   // 500K
  57 #define DRC_300KBS  0x01  // 300K
  58 #define DRC_250KBS  0x02  // 250K
  59 //
  60 // FDC Command Code
  61 //
  62 #define READ_DATA_CMD         0x06
  63 #define SEEK_CMD              0x0F
  64 #define RECALIBRATE_CMD       0x07
  65 #define SENSE_INT_STATUS_CMD  0x08
  66 #define SPECIFY_CMD           0x03
  67 #define SENSE_DRV_STATUS_CMD  0x04
  68
  69 ///
  70 /// CMD_MT: Multi_Track Selector
  71 /// when set , this flag selects the multi-track operating mode.
  72 /// In this mode, the FDC treats a complete cylinder under head0 and 1 as a single track
  73 ///
  74 #define CMD_MT  BIT7
  75
  76 ///
  77 /// CMD_MFM: MFM/FM Mode Selector
  78 /// A one selects the double density(MFM) mode
  79 /// A zero selects single density (FM) mode
  80 ///
  81 #define CMD_MFM BIT6
  82
  83 ///
  84 /// CMD_SK: Skip Flag
  85 /// When set to 1, sectors containing a deleted data address mark will automatically be skipped
  86 /// during the execution of Read Data.
  87 /// When set to 0, the sector is read or written the same as the read and write commands.
  88 ///
  89 #define CMD_SK  BIT5
  90
  91 //
  92 // FDC Status Register Bit Definitions
  93 //
  94 //
  95 // Status Register 0
  96 //
  97 #define STS0_IC (BIT7 | BIT6) // Interrupt Code
  98 #define STS0_SE BIT5          // Seek End: the FDC completed a seek or recalibrate command
  99 #define STS0_EC BIT4          // Equipment Check
 100 #define STS0_NR BIT3          // Not Ready(unused), this bit is always 0
 101 #define STS0_HA BIT2          // Head Address: the current head address
 102 //
 103 // STS0_US1 & STS0_US0: Drive Select(the current selected drive)
 104 //
 105 #define STS0_US1  BIT1  // Unit Select1
 106 #define STS0_US0  BIT0  // Unit Select0
 107 //
 108 // Status Register 1
 109 //
 110 #define STS1_EN BIT7  // End of Cylinder
 111 //
 112 // BIT6 is unused
 113 //
 114 #define STS1_DE BIT5  // Data Error: The FDC detected a CRC error in either the ID field or data field of a sector
 115 #define STS1_OR BIT4  // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval
 116 //
 117 // BIT3 is unused
 118 //
 119 #define STS1_ND BIT2  // No data
 120 #define STS1_NW BIT1  // Not Writable
 121 #define STS1_MA BIT0  // Missing Address Mark
 122
 123 //
 124 // Status Register 2
 125 //
 126 // BIT7 is unused
 127 //
 128 #define STS2_CM BIT6  // Control Mark
 129 #define STS2_DD BIT5  // Data Error in Data Field: The FDC detected a CRC error in the data field
 130 #define STS2_WC BIT4  // Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC
 131 //
 132 // BIT3 is unused
 133 // BIT2 is unused
 134 //
 135 #define STS2_BC BIT1  // Bad Cylinder
 136 #define STS2_MD BIT0  // Missing Address Mark in DataField
 137
 138 //
 139 // Status Register 3
 140 //
 141 // BIT7 is unused
 142 //
 143 #define STS3_WP BIT6  // Write Protected
 144 //
 145 // BIT5 is unused
 146 //
 147 #define STS3_T0 BIT4  // Track 0
 148 //
 149 // BIT3 is unused
 150 //
 151 #define STS3_HD BIT2  // Head Address
 152 //
 153 // STS3_US1 & STS3_US0 : Drive Select
 154 //
 155 #define STS3_US1  BIT1  // Unit Select1
 156 #define STS3_US0  BIT0  // Unit Select0
 157
 158 //
 159 // Status Register 0 Interrupt Code Description
 160 //
 161 #define IC_NT   0x0   // Normal Termination of Command
 162 #define IC_AT   0x40  // Abnormal Termination of Command
 163 #define IC_IC   0x80  // Invalid Command
 164 #define IC_ATRC 0xC0  // Abnormal Termination caused by Polling
 165
 166 ///
 167 /// Table of parameters for diskette
 168 ///
 169 typedef struct {
 170   UINT8 EndOfTrack;          ///< End of track
 171   UINT8 GapLength;           ///< Gap length
 172   UINT8 DataLength;          ///< Data length
 173   UINT8 Number;              ///< Number of bytes per sector
 174   UINT8 MaxTrackNum;
 175   UINT8 MotorStartTime;
 176   UINT8 MotorOffTime;
 177   UINT8 HeadSettlingTime;
 178   UINT8 DataTransferRate;
 179 } DISKET_PARA_TABLE;
 180
 181 ///
 182 /// Structure for FDC Command Packet 1
 183 ///
 184 typedef struct {
 185   UINT8 CommandCode;
 186   UINT8 DiskHeadSel;
 187   UINT8 Cylinder;
 188   UINT8 Head;
 189   UINT8 Sector;
 190   UINT8 Number;
 191   UINT8 EndOfTrack;
 192   UINT8 GapLength;
 193   UINT8 DataLength;
 194 } FDC_COMMAND_PACKET1;
 195
 196 ///
 197 /// Structure for FDC Command Packet 2
 198 ///
 199 typedef struct {
 200   UINT8 CommandCode;
 201   UINT8 DiskHeadSel;
 202 } FDC_COMMAND_PACKET2;
 203
 204 ///
 205 /// Structure for FDC Specify Command
 206 ///
 207 typedef struct {
 208   UINT8 CommandCode;
 209   UINT8 SrtHut;
 210   UINT8 HltNd;
 211 } FDC_SPECIFY_CMD;
 212
 213 ///
 214 /// Structure for FDC Seek Command
 215 ///
 216 typedef struct {
 217   UINT8 CommandCode;
 218   UINT8 DiskHeadSel;
 219   UINT8 NewCylinder;
 220 } FDC_SEEK_CMD;
 221
 222 ///
 223 /// Structure for FDC Result Packet
 224 ///
 225 typedef struct {
 226   UINT8 Status0;
 227   UINT8 Status1;
 228   UINT8 Status2;
 229   UINT8 CylinderNumber;
 230   UINT8 HeaderAddress;
 231   UINT8 Record;
 232   UINT8 Number;
 233 } FDC_RESULT_PACKET;
 234
 235 #endif