3 Copyright (c) 2006 - 2007, Intel Corporation<BR>
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Include for Serial Driver
29 // The package level header files this module uses
32 #include <FrameworkPei.h>
34 // The protocols, PPI and GUID defintions for this module
36 #include <Protocol/IsaIo.h>
37 #include <Protocol/SerialIo.h>
38 #include <Protocol/DevicePath.h>
40 // The Library classes this module consumes
42 #include <Library/DebugLib.h>
43 #include <Library/UefiDriverEntryPoint.h>
44 #include <Library/BaseLib.h>
45 #include <Library/UefiLib.h>
46 #include <Library/DevicePathLib.h>
47 #include <Library/BaseMemoryLib.h>
48 #include <Library/MemoryAllocationLib.h>
49 #include <Library/UefiBootServicesTableLib.h>
50 #include <Library/ReportStatusCodeLib.h>
51 #include <Library/PcdLib.h>
53 // Driver Binding Externs
55 extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver
;
56 extern EFI_COMPONENT_NAME_PROTOCOL gIsaSerialComponentName
;
59 // Internal Data Structures
61 #define SERIAL_DEV_SIGNATURE EFI_SIGNATURE_32 ('s', 'e', 'r', 'd')
62 #define SERIAL_MAX_BUFFER_SIZE 16
63 #define TIMEOUT_STALL_INTERVAL 10
66 // Name: SERIAL_DEV_FIFO
67 // Purpose: To define Receive FIFO and Transmit FIFO
68 // Context: Used by serial data transmit and receive
70 // First UINT32: The index of the first data in array Data[]
71 // Last UINT32: The index, which you can put a new data into array Data[]
72 // Surplus UINT32: Identify how many data you can put into array Data[]
73 // Data[] UINT8 : An array, which used to store data
79 UINT8 Data
[SERIAL_MAX_BUFFER_SIZE
];
91 // Purpose: To provide device specific information
94 // Signature UINTN: The identity of the serial device
95 // SerialIo SERIAL_IO_PROTOCOL: Serial I/O protocol interface
96 // SerialMode SERIAL_IO_MODE:
97 // DevicePath EFI_DEVICE_PATH_PROTOCOL *: Device path of the serial device
98 // Handle EFI_HANDLE: The handle instance attached to serial device
99 // BaseAddress UINT16: The base address of specific serial device
100 // Receive SERIAL_DEV_FIFO: The FIFO used to store data,
101 // which is received by UART
102 // Transmit SERIAL_DEV_FIFO: The FIFO used to store data,
103 // which you want to transmit by UART
104 // SoftwareLoopbackEnable BOOLEAN:
105 // Type EFI_UART_TYPE: Specify the UART type of certain serial device
111 EFI_SERIAL_IO_PROTOCOL SerialIo
;
112 EFI_SERIAL_IO_MODE SerialMode
;
113 EFI_DEVICE_PATH_PROTOCOL
*DevicePath
;
115 EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
;
116 UART_DEVICE_PATH UartDevicePath
;
117 EFI_ISA_IO_PROTOCOL
*IsaIo
;
120 SERIAL_DEV_FIFO Receive
;
121 SERIAL_DEV_FIFO Transmit
;
122 BOOLEAN SoftwareLoopbackEnable
;
123 BOOLEAN HardwareFlowControl
;
125 EFI_UNICODE_STRING_TABLE
*ControllerNameTable
;
128 #include "ComponentName.h"
130 #define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)
135 extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver
;
138 // Serial Driver Defaults
140 #define SERIAL_PORT_DEFAULT_BAUD_RATE 115200
141 #define SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH 1
142 #define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
143 #define SERIAL_PORT_DEFAULT_PARITY NoParity
144 #define SERIAL_PORT_DEFAULT_DATA_BITS 8
145 #define SERIAL_PORT_DEFAULT_STOP_BITS 1
146 #define SERIAL_PORT_DEFAULT_CONTROL_MASK 0
149 // (24000000/13)MHz input clock
151 #define SERIAL_PORT_INPUT_CLOCK 1843200
154 // 115200 baud with rounding errors
156 #define SERIAL_PORT_MAX_BAUD_RATE 115400
157 #define SERIAL_PORT_MIN_BAUD_RATE 50
159 #define SERIAL_PORT_MAX_RECEIVE_FIFO_DEPTH 16
160 #define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS
161 #define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
165 #define SERIAL_REGISTER_THR 0 // WO Transmit Holding Register
166 #define SERIAL_REGISTER_RBR 0 // RO Receive Buffer Register
167 #define SERIAL_REGISTER_DLL 0 // R/W Divisor Latch LSB
168 #define SERIAL_REGISTER_DLM 1 // R/W Divisor Latch MSB
169 #define SERIAL_REGISTER_IER 1 // R/W Interrupt Enable Register
170 #define SERIAL_REGISTER_IIR 2 // RO Interrupt Identification Register
171 #define SERIAL_REGISTER_FCR 2 // WO FIFO Cotrol Register
172 #define SERIAL_REGISTER_LCR 3 // R/W Line Control Register
173 #define SERIAL_REGISTER_MCR 4 // R/W Modem Control Register
174 #define SERIAL_REGISTER_LSR 5 // R/W Line Status Register
175 #define SERIAL_REGISTER_MSR 6 // R/W Modem Status Register
176 #define SERIAL_REGISTER_SCR 7 // R/W Scratch Pad Register
179 // Name: SERIAL_PORT_IER_BITS
180 // Purpose: Define each bit in Interrupt Enable Register
183 // RAVIE Bit0: Receiver Data Available Interrupt Enable
184 // THEIE Bit1: Transmistter Holding Register Empty Interrupt Enable
185 // RIE Bit2: Receiver Interrupt Enable
186 // MIE Bit3: Modem Interrupt Enable
187 // Reserved Bit4-Bit7: Reserved
195 } SERIAL_PORT_IER_BITS
;
198 // Name: SERIAL_PORT_IER
202 // Bits SERIAL_PORT_IER_BITS: Bits of the IER
203 // Data UINT8: the value of the IER
206 SERIAL_PORT_IER_BITS Bits
;
211 // Name: SERIAL_PORT_IIR_BITS
212 // Purpose: Define each bit in Interrupt Identification Register
215 // IPS Bit0: Interrupt Pending Status
216 // IIB Bit1-Bit3: Interrupt ID Bits
217 // Reserved Bit4-Bit5: Reserved
218 // FIFOES Bit6-Bit7: FIFO Mode Enable Status
225 } SERIAL_PORT_IIR_BITS
;
228 // Name: SERIAL_PORT_IIR
232 // Bits SERIAL_PORT_IIR_BITS: Bits of the IIR
233 // Data UINT8: the value of the IIR
236 SERIAL_PORT_IIR_BITS Bits
;
241 // Name: SERIAL_PORT_FCR_BITS
242 // Purpose: Define each bit in FIFO Control Register
245 // TRFIFOE Bit0: Transmit and Receive FIFO Enable
246 // RESETRF Bit1: Reset Reciever FIFO
247 // RESETTF Bit2: Reset Transmistter FIFO
248 // DMS Bit3: DMA Mode Select
249 // Reserved Bit4-Bit5: Reserved
250 // RTB Bit6-Bit7: Receive Trigger Bits
259 } SERIAL_PORT_FCR_BITS
;
262 // Name: SERIAL_PORT_FCR
266 // Bits SERIAL_PORT_FCR_BITS: Bits of the FCR
267 // Data UINT8: the value of the FCR
270 SERIAL_PORT_FCR_BITS Bits
;
275 // Name: SERIAL_PORT_LCR_BITS
276 // Purpose: Define each bit in Line Control Register
279 // SERIALDB Bit0-Bit1: Number of Serial Data Bits
280 // STOPB Bit2: Number of Stop Bits
281 // PAREN Bit3: Parity Enable
282 // EVENPAR Bit4: Even Parity Select
283 // STICPAR Bit5: Sticky Parity
284 // BRCON Bit6: Break Control
285 // DLAB Bit7: Divisor Latch Access Bit
295 } SERIAL_PORT_LCR_BITS
;
298 // Name: SERIAL_PORT_LCR
302 // Bits SERIAL_PORT_LCR_BITS: Bits of the LCR
303 // Data UINT8: the value of the LCR
306 SERIAL_PORT_LCR_BITS Bits
;
311 // Name: SERIAL_PORT_MCR_BITS
312 // Purpose: Define each bit in Modem Control Register
315 // DTRC Bit0: Data Terminal Ready Control
316 // RTS Bit1: Request To Send Control
317 // OUT1 Bit2: Output1
318 // OUT2 Bit3: Output2, used to disable interrupt
319 // LME; Bit4: Loopback Mode Enable
320 // Reserved Bit5-Bit7: Reserved
329 } SERIAL_PORT_MCR_BITS
;
332 // Name: SERIAL_PORT_MCR
336 // Bits SERIAL_PORT_MCR_BITS: Bits of the MCR
337 // Data UINT8: the value of the MCR
340 SERIAL_PORT_MCR_BITS Bits
;
345 // Name: SERIAL_PORT_LSR_BITS
346 // Purpose: Define each bit in Line Status Register
349 // DR Bit0: Receiver Data Ready Status
350 // OE Bit1: Overrun Error Status
351 // PE Bit2: Parity Error Status
352 // FE Bit3: Framing Error Status
353 // BI Bit4: Break Interrupt Status
354 // THRE Bit5: Transmistter Holding Register Status
355 // TEMT Bit6: Transmitter Empty Status
356 // FIFOE Bit7: FIFO Error Status
367 } SERIAL_PORT_LSR_BITS
;
370 // Name: SERIAL_PORT_LSR
374 // Bits SERIAL_PORT_LSR_BITS: Bits of the LSR
375 // Data UINT8: the value of the LSR
378 SERIAL_PORT_LSR_BITS Bits
;
383 // Name: SERIAL_PORT_MSR_BITS
384 // Purpose: Define each bit in Modem Status Register
387 // DeltaCTS Bit0: Delta Clear To Send Status
388 // DeltaDSR Bit1: Delta Data Set Ready Status
389 // TrailingEdgeRI Bit2: Trailing Edge of Ring Indicator Status
390 // DeltaDCD Bit3: Delta Data Carrier Detect Status
391 // CTS Bit4: Clear To Send Status
392 // DSR Bit5: Data Set Ready Status
393 // RI Bit6: Ring Indicator Status
394 // DCD Bit7: Data Carrier Detect Status
399 UINT8 TrailingEdgeRI
: 1;
405 } SERIAL_PORT_MSR_BITS
;
408 // Name: SERIAL_PORT_MSR
412 // Bits SERIAL_PORT_MSR_BITS: Bits of the MSR
413 // Data UINT8: the value of the MSR
416 SERIAL_PORT_MSR_BITS Bits
;
422 // Define serial register I/O macros
424 #define READ_RBR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_RBR)
425 #define READ_DLL(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLL)
426 #define READ_DLM(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLM)
427 #define READ_IER(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IER)
428 #define READ_IIR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IIR)
429 #define READ_LCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LCR)
430 #define READ_MCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MCR)
431 #define READ_LSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LSR)
432 #define READ_MSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MSR)
433 #define READ_SCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_SCR)
435 #define WRITE_THR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_THR, D)
436 #define WRITE_DLL(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLL, D)
437 #define WRITE_DLM(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLM, D)
438 #define WRITE_IER(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_IER, D)
439 #define WRITE_FCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_FCR, D)
440 #define WRITE_LCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LCR, D)
441 #define WRITE_MCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MCR, D)
442 #define WRITE_LSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LSR, D)
443 #define WRITE_MSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MSR, D)
444 #define WRITE_SCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_SCR, D)
448 // Driver model protocol interface
453 SerialControllerDriverSupported (
454 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
455 IN EFI_HANDLE Controller
,
456 IN EFI_DEVICE_PATH_PROTOCOL
*RemainingDevicePath
461 SerialControllerDriverStart (
462 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
463 IN EFI_HANDLE Controller
,
464 IN EFI_DEVICE_PATH_PROTOCOL
*RemainingDevicePath
469 SerialControllerDriverStop (
470 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
471 IN EFI_HANDLE Controller
,
472 IN UINTN NumberOfChildren
,
473 IN EFI_HANDLE
*ChildHandleBuffer
477 // Serial I/O Protocol Interface
482 IN EFI_SERIAL_IO_PROTOCOL
*This
487 IsaSerialSetAttributes (
488 IN EFI_SERIAL_IO_PROTOCOL
*This
,
490 IN UINT32 ReceiveFifoDepth
,
492 IN EFI_PARITY_TYPE Parity
,
494 IN EFI_STOP_BITS_TYPE StopBits
499 IsaSerialSetControl (
500 IN EFI_SERIAL_IO_PROTOCOL
*This
,
506 IsaSerialGetControl (
507 IN EFI_SERIAL_IO_PROTOCOL
*This
,
514 IN EFI_SERIAL_IO_PROTOCOL
*This
,
515 IN OUT UINTN
*BufferSize
,
522 IN EFI_SERIAL_IO_PROTOCOL
*This
,
523 IN OUT UINTN
*BufferSize
,
528 // Internal Functions
531 IsaSerialPortPresent (
532 IN SERIAL_DEV
*SerialDevice
537 IN SERIAL_DEV_FIFO
*Fifo
542 IN SERIAL_DEV_FIFO
*Fifo
547 IN SERIAL_DEV_FIFO
*Fifo
,
552 IsaSerialFifoRemove (
553 IN SERIAL_DEV_FIFO
*Fifo
,
558 IsaSerialReceiveTransmit (
559 IN SERIAL_DEV
*SerialDevice
564 IN EFI_ISA_IO_PROTOCOL
*IsaIo
,
565 IN UINT16 BaseAddress
,
571 IN EFI_ISA_IO_PROTOCOL
*IsaIo
,
572 IN UINT16 BaseAddress
,