IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeData.h

   1 /** @file
   2   Header file for IDE Bus Driver's Data Structures
   3
   4   Copyright (c) 2006 - 2007 Intel Corporation. <BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _IDE_DATA_H_
  16 #define _IDE_DATA_H_
  17
  18 #include <IndustryStandard/Atapi.h>
  19
  20 //
  21 // common constants
  22 //
  23 #define STALL_1_MILLI_SECOND  1000    // stall 1 ms
  24 #define STALL_1_SECOND        1000000 // stall 1 second
  25 typedef enum {
  26   IdePrimary    = 0,
  27   IdeSecondary  = 1,
  28   IdeMaxChannel = 2
  29 } EFI_IDE_CHANNEL;
  30
  31 typedef enum {
  32   IdeMaster     = 0,
  33   IdeSlave      = 1,
  34   IdeMaxDevice  = 2
  35 } EFI_IDE_DEVICE;
  36
  37 typedef enum {
  38   IdeMagnetic,                        /* ZIP Drive or LS120 Floppy Drive */
  39   IdeCdRom,                           /* ATAPI CDROM */
  40   IdeHardDisk,                        /* Hard Disk */
  41   Ide48bitAddressingHardDisk,         /* Hard Disk larger than 120GB */
  42   IdeUnknown
  43 } IDE_DEVICE_TYPE;
  44
  45 typedef enum {
  46   SenseNoSenseKey,
  47   SenseDeviceNotReadyNoRetry,
  48   SenseDeviceNotReadyNeedRetry,
  49   SenseNoMedia,
  50   SenseMediaChange,
  51   SenseMediaError,
  52   SenseOtherSense
  53 } SENSE_RESULT;
  54
  55 typedef enum {
  56   AtaUdmaReadOp,
  57   AtaUdmaReadExtOp,
  58   AtaUdmaWriteOp,
  59   AtaUdmaWriteExtOp
  60 } ATA_UDMA_OPERATION;
  61
  62 //
  63 // IDE Registers
  64 //
  65 typedef union {
  66   UINT16  Command;        /* when write */
  67   UINT16  Status;         /* when read */
  68 } IDE_CMD_OR_STATUS;
  69
  70 typedef union {
  71   UINT16  Error;          /* when read */
  72   UINT16  Feature;        /* when write */
  73 } IDE_ERROR_OR_FEATURE;
  74
  75 typedef union {
  76   UINT16  AltStatus;      /* when read */
  77   UINT16  DeviceControl;  /* when write */
  78 } IDE_ALTSTATUS_OR_DEVICECONTROL;
  79
  80 //
  81 // IDE registers set
  82 //
  83 typedef struct {
  84   UINT16                          Data;
  85   IDE_ERROR_OR_FEATURE            Reg1;
  86   UINT16                          SectorCount;
  87   UINT16                          SectorNumber;
  88   UINT16                          CylinderLsb;
  89   UINT16                          CylinderMsb;
  90   UINT16                          Head;
  91   IDE_CMD_OR_STATUS               Reg;
  92
  93   IDE_ALTSTATUS_OR_DEVICECONTROL  Alt;
  94   UINT16                          DriveAddress;
  95
  96   UINT16                          MasterSlave;
  97   UINT16                          BusMasterBaseAddr;
  98 } IDE_BASE_REGISTERS;
  99
 100 //
 101 // IDE registers' base addresses
 102 //
 103 typedef struct {
 104   UINT16  CommandBlockBaseAddr;
 105   UINT16  ControlBlockBaseAddr;
 106   UINT16  BusMasterBaseAddr;
 107 } IDE_REGISTERS_BASE_ADDR;
 108
 109 //
 110 // Bit definitions in Programming Interface byte of the Class Code field
 111 // in PCI IDE controller's Configuration Space
 112 //
 113 #define IDE_PRIMARY_OPERATING_MODE            BIT0
 114 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR    BIT1
 115 #define IDE_SECONDARY_OPERATING_MODE          BIT2
 116 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR  BIT3
 117
 118
 119 //
 120 // Bus Master Reg
 121 //
 122 #define BMIC_NREAD      BIT3
 123 #define BMIC_START      BIT0
 124 #define BMIS_INTERRUPT  BIT2
 125 #define BMIS_ERROR      BIT1
 126
 127 #define BMICP_OFFSET    0x00
 128 #define BMISP_OFFSET    0x02
 129 #define BMIDP_OFFSET    0x04
 130 #define BMICS_OFFSET    0x08
 131 #define BMISS_OFFSET    0x0A
 132 #define BMIDS_OFFSET    0x0C
 133
 134 //
 135 // Time Out Value For IDE Device Polling
 136 //
 137
 138 //
 139 // ATATIMEOUT is used for waiting time out for ATA device
 140 //
 141
 142 //
 143 // 1 second
 144 //
 145 #define ATATIMEOUT  1000
 146
 147 //
 148 // ATAPITIMEOUT is used for waiting operation
 149 // except read and write time out for ATAPI device
 150 //
 151
 152 //
 153 // 1 second
 154 //
 155 #define ATAPITIMEOUT  1000
 156
 157 //
 158 // ATAPILONGTIMEOUT is used for waiting read and
 159 // write operation timeout for ATAPI device
 160 //
 161
 162 //
 163 // 2 seconds
 164 //
 165 #define CDROMLONGTIMEOUT  2000
 166
 167 //
 168 // 5 seconds
 169 //
 170 #define ATAPILONGTIMEOUT  5000
 171
 172 //
 173 // 10 seconds
 174 //
 175 #define ATASMARTTIMEOUT   10000
 176
 177
 178 //
 179 // ATAPI6 related data structure definition
 180 //
 181
 182 //
 183 // The maximum sectors count in 28 bit addressing mode
 184 //
 185 #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
 186
 187 #pragma pack(1)
 188
 189 typedef struct {
 190   UINT32  RegionBaseAddr;
 191   UINT16  ByteCount;
 192   UINT16  EndOfTable;
 193 } IDE_DMA_PRD;
 194
 195 #pragma pack()
 196
 197 #define SETFEATURE        TRUE
 198 #define CLEARFEATURE      FALSE
 199
 200 ///
 201 /// PIO mode definition
 202 ///
 203 typedef enum _ATA_PIO_MODE_ {
 204   AtaPioModeBelow2,
 205   AtaPioMode2,
 206   AtaPioMode3,
 207   AtaPioMode4
 208 } ATA_PIO_MODE;
 209
 210 //
 211 // Multi word DMA definition
 212 //
 213 typedef enum _ATA_MDMA_MODE_ {
 214   AtaMdmaMode0,
 215   AtaMdmaMode1,
 216   AtaMdmaMode2
 217 } ATA_MDMA_MODE;
 218
 219 //
 220 // UDMA mode definition
 221 //
 222 typedef enum _ATA_UDMA_MODE_ {
 223   AtaUdmaMode0,
 224   AtaUdmaMode1,
 225   AtaUdmaMode2,
 226   AtaUdmaMode3,
 227   AtaUdmaMode4,
 228   AtaUdmaMode5
 229 } ATA_UDMA_MODE;
 230
 231 #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
 232 #define ATA_MODE_CATEGORY_FLOW_PIO    0x01
 233 #define ATA_MODE_CATEGORY_MDMA        0x04
 234 #define ATA_MODE_CATEGORY_UDMA        0x08
 235
 236 #pragma pack(1)
 237
 238 typedef struct {
 239   UINT8 ModeNumber : 3;
 240   UINT8 ModeCategory : 5;
 241 } ATA_TRANSFER_MODE;
 242
 243 typedef struct {
 244   UINT8 Sector;
 245   UINT8 Heads;
 246   UINT8 MultipleSector;
 247 } ATA_DRIVE_PARMS;
 248
 249 #pragma pack()
 250 //
 251 // IORDY Sample Point field value
 252 //
 253 #define ISP_5_CLK 0
 254 #define ISP_4_CLK 1
 255 #define ISP_3_CLK 2
 256 #define ISP_2_CLK 3
 257
 258 //
 259 // Recovery Time field value
 260 //
 261 #define RECVY_4_CLK 0
 262 #define RECVY_3_CLK 1
 263 #define RECVY_2_CLK 2
 264 #define RECVY_1_CLK 3
 265
 266 //
 267 // Slave IDE Timing Register Enable
 268 //
 269 #define SITRE BIT14
 270
 271 //
 272 // DMA Timing Enable Only Select 1
 273 //
 274 #define DTE1  BIT7
 275
 276 //
 277 // Pre-fetch and Posting Enable Select 1
 278 //
 279 #define PPE1  BIT6
 280
 281 //
 282 // IORDY Sample Point Enable Select 1
 283 //
 284 #define IE1 BIT5
 285
 286 //
 287 // Fast Timing Bank Drive Select 1
 288 //
 289 #define TIME1 BIT4
 290
 291 //
 292 // DMA Timing Enable Only Select 0
 293 //
 294 #define DTE0  BIT3
 295
 296 //
 297 // Pre-fetch and Posting Enable Select 0
 298 //
 299 #define PPE0  BIT2
 300
 301 //
 302 // IOREY Sample Point Enable Select 0
 303 //
 304 #define IE0 BIT1
 305
 306 //
 307 // Fast Timing Bank Drive Select 0
 308 //
 309 #define TIME0 BIT0
 310
 311 #endif