]> git.proxmox.com Git - mirror_edk2.git/blob - IntelFrameworkModulePkg/Bus/Pci/PciBus/Dxe/PciOptionRomSupport.c
f6b371f8a508532dc4afa63531ecc196eb2ed2da
[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBus / Dxe / PciOptionRomSupport.c
1 /*++
2
3 Copyright (c) 2006 - 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module Name:
13
14 PciOptionRomSupport.c
15
16 Abstract:
17
18 PCI Bus Driver
19
20 Revision History
21
22 --*/
23
24 #include "pcibus.h"
25 #include "PciResourceSupport.h"
26
27 //
28 // Min Max
29 //
30 #define EFI_MIN(a, b) (((a) < (b)) ? (a) : (b))
31 #define EFI_MAX(a, b) (((a) > (b)) ? (a) : (b))
32
33
34 EFI_STATUS
35 GetOpRomInfo (
36 IN PCI_IO_DEVICE *PciIoDevice
37 )
38 /*++
39
40 Routine Description:
41
42 Arguments:
43
44 Returns:
45
46 --*/
47 // TODO: PciIoDevice - add argument and description to function comment
48 // TODO: EFI_NOT_FOUND - add return value to function comment
49 // TODO: EFI_SUCCESS - add return value to function comment
50 {
51 UINT8 RomBarIndex;
52 UINT32 AllOnes;
53 UINT64 Address;
54 EFI_STATUS Status;
55 UINT8 Bus;
56 UINT8 Device;
57 UINT8 Function;
58 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
59
60 Bus = PciIoDevice->BusNumber;
61 Device = PciIoDevice->DeviceNumber;
62 Function = PciIoDevice->FunctionNumber;
63
64 PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;
65
66 //
67 // offset is 0x30 if is not ppb
68 //
69
70 //
71 // 0x30
72 //
73 RomBarIndex = PCI_DEVICE_ROMBAR;
74
75 if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
76 //
77 // if is ppb
78 //
79
80 //
81 // 0x38
82 //
83 RomBarIndex = PCI_BRIDGE_ROMBAR;
84 }
85 //
86 // the bit0 is 0 to prevent the enabling of the Rom address decoder
87 //
88 AllOnes = 0xfffffffe;
89 Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);
90
91 Status = PciRootBridgeIoWrite (
92 PciRootBridgeIo,
93 &PciIoDevice->Pci,
94 EfiPciWidthUint32,
95 Address,
96 1,
97 &AllOnes
98 );
99 if (EFI_ERROR (Status)) {
100 return Status;
101 }
102
103 //
104 // read back
105 //
106 Status = PciRootBridgeIoRead (
107 PciRootBridgeIo,
108 &PciIoDevice->Pci,
109 EfiPciWidthUint32,
110 Address,
111 1,
112 &AllOnes
113 );
114 if (EFI_ERROR (Status)) {
115 return Status;
116 }
117 //
118 // Bits [1, 10] are reserved
119 //
120 AllOnes &= 0xFFFFF800;
121 if ((AllOnes == 0) || (AllOnes == 0xFFFFF800)) {
122 return EFI_NOT_FOUND;
123 }
124
125 PciIoDevice->RomSize = (UINT64) ((~AllOnes) + 1);
126 return EFI_SUCCESS;
127 }
128
129 EFI_STATUS
130 LoadOpRomImage (
131 IN PCI_IO_DEVICE *PciDevice,
132 IN UINT64 RomBase
133 )
134 /*++
135
136 Routine Description:
137
138 Load option rom image for specified PCI device
139
140 Arguments:
141
142 Returns:
143
144 --*/
145 // TODO: PciDevice - add argument and description to function comment
146 // TODO: RomBase - add argument and description to function comment
147 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
148 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
149 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
150 {
151 UINT8 RomBarIndex;
152 UINT8 Indicator;
153 UINT16 OffsetPcir;
154 UINT32 RomBarOffset;
155 UINT32 RomBar;
156 EFI_STATUS retStatus;
157 BOOLEAN FirstCheck;
158 UINT8 *Image;
159 PCI_EXPANSION_ROM_HEADER *RomHeader;
160 PCI_DATA_STRUCTURE *RomPcir;
161 UINT64 RomSize;
162 UINT64 RomImageSize;
163 UINT8 *RomInMemory;
164 UINT8 CodeType;
165
166 RomSize = PciDevice->RomSize;
167
168 Indicator = 0;
169 RomImageSize = 0;
170 RomInMemory = NULL;
171 CodeType = 0xFF;
172
173 //
174 // Get the RomBarIndex
175 //
176
177 //
178 // 0x30
179 //
180 RomBarIndex = PCI_DEVICE_ROMBAR;
181 if (IS_PCI_BRIDGE (&(PciDevice->Pci))) {
182 //
183 // if is ppb
184 //
185
186 //
187 // 0x38
188 //
189 RomBarIndex = PCI_BRIDGE_ROMBAR;
190 }
191 //
192 // Allocate memory for Rom header and PCIR
193 //
194 RomHeader = AllocatePool (sizeof (PCI_EXPANSION_ROM_HEADER));
195 if (RomHeader == NULL) {
196 return EFI_OUT_OF_RESOURCES;
197 }
198
199 RomPcir = AllocatePool (sizeof (PCI_DATA_STRUCTURE));
200 if (RomPcir == NULL) {
201 gBS->FreePool (RomHeader);
202 return EFI_OUT_OF_RESOURCES;
203 }
204
205 RomBar = (UINT32) RomBase;
206
207 //
208 // Enable RomBar
209 //
210 RomDecode (PciDevice, RomBarIndex, RomBar, TRUE);
211
212 RomBarOffset = RomBar;
213 retStatus = EFI_NOT_FOUND;
214 FirstCheck = TRUE;
215
216 do {
217 PciDevice->PciRootBridgeIo->Mem.Read (
218 PciDevice->PciRootBridgeIo,
219 EfiPciWidthUint8,
220 RomBarOffset,
221 sizeof (PCI_EXPANSION_ROM_HEADER),
222 (UINT8 *) RomHeader
223 );
224
225 if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
226 RomBarOffset = RomBarOffset + 512;
227 if (FirstCheck) {
228 break;
229 } else {
230 RomImageSize = RomImageSize + 512;
231 continue;
232 }
233 }
234
235 FirstCheck = FALSE;
236 OffsetPcir = RomHeader->PcirOffset;
237 PciDevice->PciRootBridgeIo->Mem.Read (
238 PciDevice->PciRootBridgeIo,
239 EfiPciWidthUint8,
240 RomBarOffset + OffsetPcir,
241 sizeof (PCI_DATA_STRUCTURE),
242 (UINT8 *) RomPcir
243 );
244 if (RomPcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
245 CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
246 }
247 Indicator = RomPcir->Indicator;
248 RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
249 RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
250 } while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize));
251
252 //
253 // Some Legacy Cards do not report the correct ImageLength so used the maximum
254 // of the legacy length and the PCIR Image Length
255 //
256 if (CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
257 RomImageSize = EFI_MAX(RomImageSize, (((EFI_LEGACY_EXPANSION_ROM_HEADER *)RomHeader)->Size512 * 512));
258 }
259
260 if (RomImageSize > 0) {
261 retStatus = EFI_SUCCESS;
262 Image = AllocatePool ((UINT32) RomImageSize);
263 if (Image == NULL) {
264 RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);
265 gBS->FreePool (RomHeader);
266 gBS->FreePool (RomPcir);
267 return EFI_OUT_OF_RESOURCES;
268 }
269
270 //
271 // Copy Rom image into memory
272 //
273 PciDevice->PciRootBridgeIo->Mem.Read (
274 PciDevice->PciRootBridgeIo,
275 EfiPciWidthUint8,
276 RomBar,
277 (UINT32) RomImageSize,
278 Image
279 );
280 RomInMemory = Image;
281 }
282
283 RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);
284
285 PciDevice->PciIo.RomSize = RomImageSize;
286 PciDevice->PciIo.RomImage = RomInMemory;
287
288 PciRomAddImageMapping (
289 NULL,
290 PciDevice->PciRootBridgeIo->SegmentNumber,
291 PciDevice->BusNumber,
292 PciDevice->DeviceNumber,
293 PciDevice->FunctionNumber,
294 (UINT64) (UINTN) PciDevice->PciIo.RomImage,
295 PciDevice->PciIo.RomSize
296 );
297
298 //
299 // Free allocated memory
300 //
301 gBS->FreePool (RomHeader);
302 gBS->FreePool (RomPcir);
303
304 return retStatus;
305 }
306
307 EFI_STATUS
308 RomDecode (
309 IN PCI_IO_DEVICE *PciDevice,
310 IN UINT8 RomBarIndex,
311 IN UINT32 RomBar,
312 IN BOOLEAN Enable
313 )
314 /*++
315
316 Routine Description:
317
318 Arguments:
319
320 Returns:
321
322 --*/
323 // TODO: PciDevice - add argument and description to function comment
324 // TODO: RomBarIndex - add argument and description to function comment
325 // TODO: RomBar - add argument and description to function comment
326 // TODO: Enable - add argument and description to function comment
327 // TODO: EFI_SUCCESS - add return value to function comment
328 {
329 UINT32 Value32;
330 UINT32 Offset;
331 EFI_PCI_IO_PROTOCOL *PciIo;
332
333 PciIo = &PciDevice->PciIo;
334 if (Enable) {
335 //
336 // Clear all bars
337 //
338 for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
339 PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
340 }
341
342 //
343 // set the Rom base address: now is hardcode
344 // enable its decoder
345 //
346 Value32 = RomBar | 0x1;
347 PciIoWrite (
348 PciIo,
349 (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
350 RomBarIndex,
351 1,
352 &Value32
353 );
354
355 //
356 // Programe all upstream bridge
357 //
358 ProgrameUpstreamBridgeForRom(PciDevice, RomBar, TRUE);
359
360 //
361 // Setting the memory space bit in the function's command register
362 //
363 PciEnableCommandRegister(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
364
365 } else {
366
367 //
368 // disable command register decode to memory
369 //
370 PciDisableCommandRegister(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
371
372 //
373 // Destroy the programmed bar in all the upstream bridge.
374 //
375 ProgrameUpstreamBridgeForRom(PciDevice, RomBar, FALSE);
376
377 //
378 // disable rom decode
379 //
380 Value32 = 0xFFFFFFFE;
381 PciIoWrite (
382 PciIo,
383 (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
384 RomBarIndex,
385 1,
386 &Value32
387 );
388
389 }
390
391 return EFI_SUCCESS;
392
393 }
394
395 EFI_STATUS
396 ProcessOpRomImage (
397 PCI_IO_DEVICE *PciDevice
398 )
399 /*++
400
401 Routine Description:
402
403 Process the oprom image.
404
405 Arguments:
406 PciDevice A pointer to a pci device.
407
408 Returns:
409
410 EFI Status.
411
412 --*/
413 {
414 UINT8 Indicator;
415 UINT32 ImageSize;
416 UINT16 ImageOffset;
417 VOID *RomBar;
418 UINT8 *RomBarOffset;
419 EFI_HANDLE ImageHandle;
420 EFI_STATUS Status;
421 EFI_STATUS retStatus;
422 BOOLEAN FirstCheck;
423 BOOLEAN SkipImage;
424 UINT32 DestinationSize;
425 UINT32 ScratchSize;
426 UINT8 *Scratch;
427 VOID *ImageBuffer;
428 VOID *DecompressedImageBuffer;
429 UINT32 ImageLength;
430 EFI_DECOMPRESS_PROTOCOL *Decompress;
431 EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;
432 PCI_DATA_STRUCTURE *Pcir;
433
434 Indicator = 0;
435
436 //
437 // Get the Address of the Rom image
438 //
439 RomBar = PciDevice->PciIo.RomImage;
440 RomBarOffset = (UINT8 *) RomBar;
441 retStatus = EFI_NOT_FOUND;
442 FirstCheck = TRUE;
443
444 do {
445 EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *) RomBarOffset;
446 if (EfiRomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
447 RomBarOffset = RomBarOffset + 512;
448 if (FirstCheck) {
449 break;
450 } else {
451 continue;
452 }
453 }
454
455 FirstCheck = FALSE;
456 Pcir = (PCI_DATA_STRUCTURE *) (RomBarOffset + EfiRomHeader->PcirOffset);
457 ImageSize = (UINT32) (Pcir->ImageLength * 512);
458 Indicator = Pcir->Indicator;
459
460 if ((Pcir->CodeType == PCI_CODE_TYPE_EFI_IMAGE) &&
461 (EfiRomHeader->EfiSignature == EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE)) {
462
463 if ((EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER) ||
464 (EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER)) {
465
466 ImageOffset = EfiRomHeader->EfiImageHeaderOffset;
467 ImageSize = (UINT32) (EfiRomHeader->InitializationSize * 512);
468
469 ImageBuffer = (VOID *) (RomBarOffset + ImageOffset);
470 ImageLength = ImageSize - (UINT32)ImageOffset;
471 DecompressedImageBuffer = NULL;
472
473 //
474 // decompress here if needed
475 //
476 SkipImage = FALSE;
477 if (EfiRomHeader->CompressionType > EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED) {
478 SkipImage = TRUE;
479 }
480
481 if (EfiRomHeader->CompressionType == EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED) {
482 Status = gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID **) &Decompress);
483 if (EFI_ERROR (Status)) {
484 SkipImage = TRUE;
485 } else {
486 SkipImage = TRUE;
487 Status = Decompress->GetInfo (
488 Decompress,
489 ImageBuffer,
490 ImageLength,
491 &DestinationSize,
492 &ScratchSize
493 );
494 if (!EFI_ERROR (Status)) {
495 DecompressedImageBuffer = NULL;
496 DecompressedImageBuffer = AllocatePool (DestinationSize);
497 if (DecompressedImageBuffer != NULL) {
498 Scratch = AllocatePool (ScratchSize);
499 if (Scratch != NULL) {
500 Status = Decompress->Decompress (
501 Decompress,
502 ImageBuffer,
503 ImageLength,
504 DecompressedImageBuffer,
505 DestinationSize,
506 Scratch,
507 ScratchSize
508 );
509 if (!EFI_ERROR (Status)) {
510 ImageBuffer = DecompressedImageBuffer;
511 ImageLength = DestinationSize;
512 SkipImage = FALSE;
513 }
514
515 gBS->FreePool (Scratch);
516 }
517 }
518 }
519 }
520 }
521
522 if (!SkipImage) {
523 //
524 // load image and start image
525 //
526 Status = gBS->LoadImage (
527 FALSE,
528 gPciBusDriverBinding.DriverBindingHandle,
529 PciDevice->Handle,
530 ImageBuffer,
531 ImageLength,
532 &ImageHandle
533 );
534 if (!EFI_ERROR (Status)) {
535 Status = gBS->StartImage (ImageHandle, NULL, NULL);
536 if (!EFI_ERROR (Status)) {
537 AddDriver (PciDevice, ImageHandle);
538 PciRomAddImageMapping (
539 ImageHandle,
540 PciDevice->PciRootBridgeIo->SegmentNumber,
541 PciDevice->BusNumber,
542 PciDevice->DeviceNumber,
543 PciDevice->FunctionNumber,
544 (UINT64) (UINTN) PciDevice->PciIo.RomImage,
545 PciDevice->PciIo.RomSize
546 );
547 retStatus = EFI_SUCCESS;
548 }
549 }
550 }
551
552 RomBarOffset = RomBarOffset + ImageSize;
553 } else {
554 RomBarOffset = RomBarOffset + ImageSize;
555 }
556 } else {
557 RomBarOffset = RomBarOffset + ImageSize;
558 }
559
560 } while (((Indicator & 0x80) == 0x00) && ((UINTN) (RomBarOffset - (UINT8 *) RomBar) < PciDevice->RomSize));
561
562 return retStatus;
563
564 }