IntelFrameworkModulePkg/Bus/Pci/PciBus/Dxe/pcibus.h

   1 /*++
   2
   3 Copyright (c) 2006 - 2007, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14   pcibus.h
  15
  16 Abstract:
  17
  18   PCI Bus Driver
  19
  20 Revision History
  21
  22 --*/
  23
  24 #ifndef _EFI_PCI_BUS_H
  25 #define _EFI_PCI_BUS_H
  26
  27 //
  28 // The package level header files this module uses
  29 //
  30 #include <PiDxe.h>
  31 #include <Common/FrameworkStatusCode.h>
  32 #include <Common/FrameworkStatusCodeDataTypeId.h>
  33 //
  34 // The protocols, PPI and GUID defintions for this module
  35 //
  36 #include <Protocol/LoadedImage.h>
  37 #include <Protocol/PciHostBridgeResourceAllocation.h>
  38 #include <Protocol/PciIo.h>
  39 #include <Guid/PciHotplugDevice.h>
  40 #include <Protocol/PciRootBridgeIo.h>
  41 #include <Protocol/PciHotPlugRequest.h>
  42 #include <Protocol/DevicePath.h>
  43 #include <Protocol/PciPlatform.h>
  44 #include <Protocol/PciHotPlugInit.h>
  45 #include <Protocol/Decompress.h>
  46 #include <Guid/PciOptionRomTable.h>
  47 #include <Protocol/BusSpecificDriverOverride.h>
  48 #include <Protocol/UgaIo.h>
  49 //
  50 // The Library classes this module consumes
  51 //
  52 #include <Library/DebugLib.h>
  53 #include <Library/UefiDriverEntryPoint.h>
  54 #include <Library/BaseLib.h>
  55 #include <Library/UefiLib.h>
  56 #include <Library/BaseMemoryLib.h>
  57 #include <Library/ReportStatusCodeLib.h>
  58 #include <Library/MemoryAllocationLib.h>
  59 #include <Library/UefiBootServicesTableLib.h>
  60 #include <Library/DevicePathLib.h>
  61 #include <Library/PcdLib.h>
  62 #include <Library/PciIncompatibleDeviceSupportLib.h>
  63
  64 #include <IndustryStandard/Pci23.h>
  65 #include <IndustryStandard/PeImage.h>
  66 #include <IndustryStandard/Acpi.h>
  67 #include "ComponentName.h"
  68
  69 //
  70 // Driver Produced Protocol Prototypes
  71 //
  72
  73 #define VGABASE1  0x3B0
  74 #define VGALIMIT1 0x3BB
  75
  76 #define VGABASE2  0x3C0
  77 #define VGALIMIT2 0x3DF
  78
  79 #define ISABASE   0x100
  80 #define ISALIMIT  0x3FF
  81
  82 typedef enum {
  83   PciBarTypeUnknown = 0,
  84   PciBarTypeIo16,
  85   PciBarTypeIo32,
  86   PciBarTypeMem32,
  87   PciBarTypePMem32,
  88   PciBarTypeMem64,
  89   PciBarTypePMem64,
  90   PciBarTypeIo,
  91   PciBarTypeMem,
  92   PciBarTypeMaxType
  93 } PCI_BAR_TYPE;
  94
  95 typedef struct {
  96   UINT64        BaseAddress;
  97   UINT64        Length;
  98   UINT64        Alignment;
  99   PCI_BAR_TYPE  BarType;
 100   BOOLEAN       Prefetchable;
 101   UINT8         MemType;
 102   UINT8         Offset;
 103 } PCI_BAR;
 104
 105 #define PPB_BAR_0                             0
 106 #define PPB_BAR_1                             1
 107 #define PPB_IO_RANGE                          2
 108 #define PPB_MEM32_RANGE                       3
 109 #define PPB_PMEM32_RANGE                      4
 110 #define PPB_PMEM64_RANGE                      5
 111 #define PPB_MEM64_RANGE                       0xFF
 112
 113 #define P2C_BAR_0                             0
 114 #define P2C_MEM_1                             1
 115 #define P2C_MEM_2                             2
 116 #define P2C_IO_1                              3
 117 #define P2C_IO_2                              4
 118
 119 #define PCI_IO_DEVICE_SIGNATURE               EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')
 120
 121 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 122 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 123 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 124 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 125 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 126 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 127 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 128
 129 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 130 //
 131 // Define resource status constant
 132 //
 133 #define EFI_RESOURCE_NONEXISTENT  0xFFFFFFFFFFFFFFFFULL
 134 #define EFI_RESOURCE_LESS         0xFFFFFFFFFFFFFFFEULL
 135 #define EFI_RESOURCE_SATISFIED    0x0000000000000000ULL
 136
 137 //
 138 // Define option for attribute
 139 //
 140 #define EFI_SET_SUPPORTS    0
 141 #define EFI_SET_ATTRIBUTES  1
 142
 143 typedef struct _PCI_IO_DEVICE {
 144   UINT32                                    Signature;
 145   EFI_HANDLE                                Handle;
 146   EFI_PCI_IO_PROTOCOL                       PciIo;
 147   LIST_ENTRY                                Link;
 148
 149   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 150   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 151   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 152
 153   //
 154   // PCI configuration space header type
 155   //
 156   PCI_TYPE00                                Pci;
 157
 158   //
 159   // Bus number, Device number, Function number
 160   //
 161   UINT8                                     BusNumber;
 162   UINT8                                     DeviceNumber;
 163   UINT8                                     FunctionNumber;
 164
 165   //
 166   // BAR for this PCI Device
 167   //
 168   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 169
 170   //
 171   // The bridge device this pci device is subject to
 172   //
 173   struct _PCI_IO_DEVICE                     *Parent;
 174
 175   //
 176   // A linked list for children Pci Device if it is bridge device
 177   //
 178   LIST_ENTRY                                ChildList;
 179
 180   //
 181   // TURE if the PCI bus driver creates the handle for this PCI device
 182   //
 183   BOOLEAN                                   Registered;
 184
 185   //
 186   // TRUE if the PCI bus driver successfully allocates the resource required by
 187   // this PCI device
 188   //
 189   BOOLEAN                                   Allocated;
 190
 191   //
 192   // The attribute this PCI device currently set
 193   //
 194   UINT64                                    Attributes;
 195
 196   //
 197   // The attributes this PCI device actually supports
 198   //
 199   UINT64                                    Supports;
 200
 201   //
 202   // The resource decode the bridge supports
 203   //
 204   UINT32                                    Decodes;
 205
 206   //
 207   // The OptionRom Size
 208   //
 209   UINT64                                    RomSize;
 210
 211   //
 212   // The OptionRom Size
 213   //
 214   UINT64                                    RomBase;
 215
 216   //
 217   // TRUE if all OpROM (in device or in platform specific position) have been processed
 218   //
 219   BOOLEAN                                   AllOpRomProcessed;
 220
 221   //
 222   // TRUE if there is any EFI driver in the OptionRom
 223   //
 224   BOOLEAN                                   BusOverride;
 225
 226   //
 227   //  A list tracking reserved resource on a bridge device
 228   //
 229   LIST_ENTRY                                ReservedResourceList;
 230
 231   //
 232   // A list tracking image handle of platform specific overriding driver
 233   //
 234   LIST_ENTRY                                OptionRomDriverList;
 235
 236   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 237   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 238
 239   BOOLEAN                                   IsPciExp;
 240
 241 } PCI_IO_DEVICE;
 242
 243
 244 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 245   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 246
 247 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 248   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 249
 250 #define PCI_IO_DEVICE_FROM_LINK(a) \
 251   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 252
 253 //
 254 // Global Variables
 255 //
 256 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 257 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 258 extern LIST_ENTRY                                   gPciDevicePool;
 259 extern BOOLEAN                                      gFullEnumeration;
 260 extern UINTN                                        gPciHostBridgeNumber;
 261 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 262 extern UINT64                                       gAllOne;
 263 extern UINT64                                       gAllZero;
 264
 265 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 266
 267 #include "PciIo.h"
 268 #include "PciCommand.h"
 269 #include "PciDeviceSupport.h"
 270 #include "PciEnumerator.h"
 271 #include "PciEnumeratorSupport.h"
 272 #include "PciDriverOverride.h"
 273 #include "PciRomTable.h"
 274 #include "PciOptionRomSupport.h"
 275 #include "PciPowerManagement.h"
 276 #include "PciHotPlugSupport.h"
 277 #include "PciLib.h"
 278
 279 //
 280 // PCI Bus Support Function Prototypes
 281 //
 282 EFI_STATUS
 283 EFIAPI
 284 PciBusDriverBindingSupported (
 285   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 286   IN EFI_HANDLE                     Controller,
 287   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 288   );
 289
 290 EFI_STATUS
 291 EFIAPI
 292 PciBusDriverBindingStart (
 293   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 294   IN EFI_HANDLE                     Controller,
 295   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 296   );
 297
 298 EFI_STATUS
 299 EFIAPI
 300 PciBusDriverBindingStop (
 301   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 302   IN  EFI_HANDLE                    Controller,
 303   IN  UINTN                         NumberOfChildren,
 304   IN  EFI_HANDLE                    *ChildHandleBuffer
 305   );
 306
 307 #endif