IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2   Header files and data structures needed by PCI Bus module.
   3
   4 Copyright (c) 2006 - 2009, Intel Corporation
   5 All rights reserved. This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15
  16 #ifndef _EFI_PCI_BUS_H_
  17 #define _EFI_PCI_BUS_H_
  18
  19 #include <FrameworkDxe.h>
  20
  21 #include <Protocol/LoadedImage.h>
  22 #include <Protocol/PciHostBridgeResourceAllocation.h>
  23 #include <Protocol/PciIo.h>
  24 #include <Protocol/LoadFile2.h>
  25 #include <Protocol/PciRootBridgeIo.h>
  26 #include <Protocol/PciHotPlugRequest.h>
  27 #include <Protocol/DevicePath.h>
  28 #include <Protocol/PciPlatform.h>
  29 #include <Protocol/PciHotPlugInit.h>
  30 #include <Protocol/Decompress.h>
  31 #include <Protocol/BusSpecificDriverOverride.h>
  32 #include <Protocol/IncompatiblePciDeviceSupport.h>
  33
  34 #include <Library/DebugLib.h>
  35 #include <Library/UefiDriverEntryPoint.h>
  36 #include <Library/BaseLib.h>
  37 #include <Library/UefiLib.h>
  38 #include <Library/BaseMemoryLib.h>
  39 #include <Library/ReportStatusCodeLib.h>
  40 #include <Library/MemoryAllocationLib.h>
  41 #include <Library/UefiBootServicesTableLib.h>
  42 #include <Library/DevicePathLib.h>
  43 #include <Library/PcdLib.h>
  44 #include <Library/PeCoffLib.h>
  45
  46 #include <IndustryStandard/Pci.h>
  47 #include <IndustryStandard/PeImage.h>
  48 #include <IndustryStandard/Acpi.h>
  49
  50 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
  51 typedef struct _PCI_BAR                    PCI_BAR;
  52
  53 typedef enum {
  54   PciBarTypeUnknown = 0,
  55   PciBarTypeIo16,
  56   PciBarTypeIo32,
  57   PciBarTypeMem32,
  58   PciBarTypePMem32,
  59   PciBarTypeMem64,
  60   PciBarTypePMem64,
  61   PciBarTypeIo,
  62   PciBarTypeMem,
  63   PciBarTypeMaxType
  64 } PCI_BAR_TYPE;
  65
  66 #include "ComponentName.h"
  67 #include "PciIo.h"
  68 #include "PciCommand.h"
  69 #include "PciDeviceSupport.h"
  70 #include "PciEnumerator.h"
  71 #include "PciEnumeratorSupport.h"
  72 #include "PciDriverOverride.h"
  73 #include "PciRomTable.h"
  74 #include "PciOptionRomSupport.h"
  75 #include "PciPowerManagement.h"
  76 #include "PciHotPlugSupport.h"
  77 #include "PciLib.h"
  78
  79 #define VGABASE1  0x3B0
  80 #define VGALIMIT1 0x3BB
  81
  82 #define VGABASE2  0x3C0
  83 #define VGALIMIT2 0x3DF
  84
  85 #define ISABASE   0x100
  86 #define ISALIMIT  0x3FF
  87
  88 //
  89 // PCI BAR parameters
  90 //
  91 struct _PCI_BAR {
  92   UINT64        BaseAddress;
  93   UINT64        Length;
  94   UINT64        Alignment;
  95   PCI_BAR_TYPE  BarType;
  96   BOOLEAN       Prefetchable;
  97   UINT8         MemType;
  98   UINT8         Offset;
  99 };
 100
 101 //
 102 // defined in PCI Card Specification, 8.0
 103 //
 104 #define PCI_CARD_MEMORY_BASE_0                0x1C
 105 #define PCI_CARD_MEMORY_LIMIT_0               0x20
 106 #define PCI_CARD_MEMORY_BASE_1                0x24
 107 #define PCI_CARD_MEMORY_LIMIT_1               0x28
 108 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
 109 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
 110 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
 111 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
 112 #define PCI_CARD_IO_BASE_1_LOWER              0x34
 113 #define PCI_CARD_IO_BASE_1_UPPER              0x36
 114 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
 115 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
 116 #define PCI_CARD_BRIDGE_CONTROL               0x3E
 117
 118 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
 119 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
 120
 121 #define PPB_BAR_0                             0
 122 #define PPB_BAR_1                             1
 123 #define PPB_IO_RANGE                          2
 124 #define PPB_MEM32_RANGE                       3
 125 #define PPB_PMEM32_RANGE                      4
 126 #define PPB_PMEM64_RANGE                      5
 127 #define PPB_MEM64_RANGE                       0xFF
 128
 129 #define P2C_BAR_0                             0
 130 #define P2C_MEM_1                             1
 131 #define P2C_MEM_2                             2
 132 #define P2C_IO_1                              3
 133 #define P2C_IO_2                              4
 134
 135 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 136 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 137 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 138 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 139 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 140 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 141 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 142
 143 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 144
 145 //
 146 // Define option for attribute
 147 //
 148 #define EFI_SET_SUPPORTS    0
 149 #define EFI_SET_ATTRIBUTES  1
 150
 151 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 152
 153 struct _PCI_IO_DEVICE {
 154   UINT32                                    Signature;
 155   EFI_HANDLE                                Handle;
 156   EFI_PCI_IO_PROTOCOL                       PciIo;
 157   LIST_ENTRY                                Link;
 158
 159   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 160   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 161   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 162   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 163
 164   //
 165   // PCI configuration space header type
 166   //
 167   PCI_TYPE00                                Pci;
 168
 169   //
 170   // Bus number, Device number, Function number
 171   //
 172   UINT8                                     BusNumber;
 173   UINT8                                     DeviceNumber;
 174   UINT8                                     FunctionNumber;
 175
 176   //
 177   // BAR for this PCI Device
 178   //
 179   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 180
 181   //
 182   // The bridge device this pci device is subject to
 183   //
 184   PCI_IO_DEVICE                             *Parent;
 185
 186   //
 187   // A linked list for children Pci Device if it is bridge device
 188   //
 189   LIST_ENTRY                                ChildList;
 190
 191   //
 192   // TURE if the PCI bus driver creates the handle for this PCI device
 193   //
 194   BOOLEAN                                   Registered;
 195
 196   //
 197   // TRUE if the PCI bus driver successfully allocates the resource required by
 198   // this PCI device
 199   //
 200   BOOLEAN                                   Allocated;
 201
 202   //
 203   // The attribute this PCI device currently set
 204   //
 205   UINT64                                    Attributes;
 206
 207   //
 208   // The attributes this PCI device actually supports
 209   //
 210   UINT64                                    Supports;
 211
 212   //
 213   // The resource decode the bridge supports
 214   //
 215   UINT32                                    Decodes;
 216
 217   //
 218   // The OptionRom Size
 219   //
 220   UINT64                                    RomSize;
 221
 222   //
 223   // The OptionRom Size
 224   //
 225   UINT64                                    RomBase;
 226
 227   //
 228   // TRUE if all OpROM (in device or in platform specific position) have been processed
 229   //
 230   BOOLEAN                                   AllOpRomProcessed;
 231
 232   //
 233   // TRUE if there is any EFI driver in the OptionRom
 234   //
 235   BOOLEAN                                   BusOverride;
 236
 237   //
 238   // A list tracking reserved resource on a bridge device
 239   //
 240   LIST_ENTRY                                ReservedResourceList;
 241
 242   //
 243   // A list tracking image handle of platform specific overriding driver
 244   //
 245   LIST_ENTRY                                OptionRomDriverList;
 246
 247   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 248   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 249
 250   BOOLEAN                                   IsPciExp;
 251
 252 };
 253
 254 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 255   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 256
 257 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 258   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 259
 260 #define PCI_IO_DEVICE_FROM_LINK(a) \
 261   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 262
 263 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 264   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 265
 266
 267
 268 //
 269 // Global Variables
 270 //
 271 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
 272 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 273 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 274 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 275 extern BOOLEAN                                      gFullEnumeration;
 276 extern UINTN                                        gPciHostBridgeNumber;
 277 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 278 extern UINT64                                       gAllOne;
 279 extern UINT64                                       gAllZero;
 280 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 281
 282
 283 /**
 284   Macro that checks whether device is a GFX device.
 285
 286   @param  _p      Specified device.
 287
 288   @retval TRUE    Device is a a GFX device.
 289   @retval FALSE   Device is not a a GFX device.
 290
 291 **/
 292 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 293
 294 /**
 295   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 296   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 297
 298   @param  This                Protocol instance pointer.
 299   @param  Controller          Handle of device to test.
 300   @param  RemainingDevicePath Optional parameter use to pick a specific child.
 301                               device to start.
 302
 303   @retval EFI_SUCCESS         This driver supports this device.
 304   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 305   @retval other               This driver does not support this device.
 306
 307 **/
 308 EFI_STATUS
 309 EFIAPI
 310 PciBusDriverBindingSupported (
 311   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 312   IN EFI_HANDLE                     Controller,
 313   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 314   );
 315
 316 /**
 317   Start this driver on ControllerHandle and enumerate Pci bus and start
 318   all device under PCI bus.
 319
 320   @param  This                 Protocol instance pointer.
 321   @param  Controller           Handle of device to bind driver to.
 322   @param  RemainingDevicePath  Optional parameter use to pick a specific child.
 323                                device to start.
 324
 325   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 326   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 327   @retval other                This driver does not support this device.
 328
 329 **/
 330 EFI_STATUS
 331 EFIAPI
 332 PciBusDriverBindingStart (
 333   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 334   IN EFI_HANDLE                     Controller,
 335   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 336   );
 337
 338 /**
 339   Stop this driver on ControllerHandle. Support stoping any child handles
 340   created by this driver.
 341
 342   @param  This              Protocol instance pointer.
 343   @param  Controller        Handle of device to stop driver on.
 344   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 345                             children is zero stop the entire bus driver.
 346   @param  ChildHandleBuffer List of Child Handles to Stop.
 347
 348   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 349   @retval other             This driver was not removed from this device.
 350
 351 **/
 352 EFI_STATUS
 353 EFIAPI
 354 PciBusDriverBindingStop (
 355   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 356   IN  EFI_HANDLE                    Controller,
 357   IN  UINTN                         NumberOfChildren,
 358   IN  EFI_HANDLE                    *ChildHandleBuffer
 359   );
 360
 361 #endif