]> git.proxmox.com Git - mirror_edk2.git/blob - IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
projects / mirror_edk2.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Refine include file for PCI Platform Protocol, and update C source code accordingly.
[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciEnumerator.c
1 /** @file
2
3 Copyright (c) 2006 - 2009, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 **/
13
14
15 #include "PciBus.h"
16 #include "PciEnumerator.h"
17 #include "PciOptionRomSupport.h"
18
19 /**
20 This routine is used to enumerate entire pci bus system
21 in a given platform.
22
23 @param Controller Parent controller handle.
24
25 @return Status of enumerating.
26 **/
27 EFI_STATUS
28 PciEnumerator (
29 IN EFI_HANDLE Controller
30 )
31 {
32
33 EFI_HANDLE HostBridgeHandle;
34 EFI_STATUS Status;
35 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;
36 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
37
38 //
39 // If PCI bus has already done the full enumeration, never do it again
40 //
41 if (!gFullEnumeration) {
42 return PciEnumeratorLight (Controller);
43 }
44
45 //
46 // Get the rootbridge Io protocol to find the host bridge handle
47 //
48 Status = gBS->OpenProtocol (
49 Controller,
50 &gEfiPciRootBridgeIoProtocolGuid,
51 (VOID **) &PciRootBridgeIo,
52 gPciBusDriverBinding.DriverBindingHandle,
53 Controller,
54 EFI_OPEN_PROTOCOL_GET_PROTOCOL
55 );
56
57 if (EFI_ERROR (Status)) {
58 return Status;
59 }
60
61 //
62 // Get the host bridge handle
63 //
64 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
65
66 //
67 // Get the pci host bridge resource allocation protocol
68 //
69 Status = gBS->OpenProtocol (
70 HostBridgeHandle,
71 &gEfiPciHostBridgeResourceAllocationProtocolGuid,
72 (VOID **) &PciResAlloc,
73 gPciBusDriverBinding.DriverBindingHandle,
74 Controller,
75 EFI_OPEN_PROTOCOL_GET_PROTOCOL
76 );
77
78 if (EFI_ERROR (Status)) {
79 return Status;
80 }
81
82 //
83 // Notify the pci bus enumeration is about to begin
84 //
85 NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);
86
87 //
88 // Start the bus allocation phase
89 //
90 Status = PciHostBridgeEnumerator (PciResAlloc);
91
92 if (EFI_ERROR (Status)) {
93 return Status;
94 }
95
96 //
97 // Submit the resource request
98 //
99 Status = PciHostBridgeResourceAllocator (PciResAlloc);
100
101 if (EFI_ERROR (Status)) {
102 return Status;
103 }
104
105 //
106 // Process P2C
107 //
108 Status = PciHostBridgeP2CProcess (PciResAlloc);
109
110 if (EFI_ERROR (Status)) {
111 return Status;
112 }
113
114 //
115 // Process attributes for devices on this host bridge
116 //
117 Status = PciHostBridgeDeviceAttribute (PciResAlloc);
118 if (EFI_ERROR (Status)) {
119 return Status;
120 }
121
122 gFullEnumeration = FALSE;
123
124 return EFI_SUCCESS;
125 }
126
127 /**
128 Enumerate PCI root bridge
129
130 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
131 @param RootBridgeDev Instance of root bridge device.
132
133 @retval EFI_SUCCESS Success to enumerate root bridge.
134 @retval Others Fail to enumerate root bridge.
135
136 **/
137 EFI_STATUS
138 PciRootBridgeEnumerator (
139 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
140 IN PCI_IO_DEVICE *RootBridgeDev
141 )
142 {
143 EFI_STATUS Status;
144 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
145 UINT8 SubBusNumber;
146 UINT8 StartBusNumber;
147 UINT8 PaddedBusRange;
148 EFI_HANDLE RootBridgeHandle;
149
150 SubBusNumber = 0;
151 StartBusNumber = 0;
152 PaddedBusRange = 0;
153
154 //
155 // Get the root bridge handle
156 //
157 RootBridgeHandle = RootBridgeDev->Handle;
158
159 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
160 EFI_PROGRESS_CODE,
161 EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_BUS_ENUM,
162 RootBridgeDev->DevicePath
163 );
164
165 //
166 // Get the Bus information
167 //
168 Status = PciResAlloc->StartBusEnumeration (
169 PciResAlloc,
170 RootBridgeHandle,
171 (VOID **) &Configuration
172 );
173
174 if (EFI_ERROR (Status)) {
175 return Status;
176 }
177
178 //
179 // Get the bus number to start with
180 //
181 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);
182 PaddedBusRange = (UINT8) (Configuration->AddrRangeMax);
183
184 //
185 // Initialize the subordinate bus number
186 //
187 SubBusNumber = StartBusNumber;
188
189 //
190 // Reset all assigned PCI bus number
191 //
192 ResetAllPpbBusNumber (
193 RootBridgeDev,
194 StartBusNumber
195 );
196
197 //
198 // Assign bus number
199 //
200 Status = PciScanBus (
201 RootBridgeDev,
202 (UINT8) (Configuration->AddrRangeMin),
203 &SubBusNumber,
204 &PaddedBusRange
205 );
206
207 if (EFI_ERROR (Status)) {
208 return Status;
209 }
210
211
212 //
213 // Assign max bus number scanned
214 //
215 Configuration->AddrLen = SubBusNumber - StartBusNumber + 1 + PaddedBusRange;
216
217 //
218 // Set bus number
219 //
220 Status = PciResAlloc->SetBusNumbers (
221 PciResAlloc,
222 RootBridgeHandle,
223 Configuration
224 );
225
226 gBS->FreePool (Configuration);
227
228 if (EFI_ERROR (Status)) {
229 return Status;
230 }
231
232 return EFI_SUCCESS;
233 }
234
235 /**
236 This routine is used to process option rom on a certain root bridge
237
238 @param Bridge Given parent's root bridge
239 @param RomBase Base address of ROM driver loaded from
240 @param MaxLength Max rom size
241
242 @retval EFI_SUCCESS Success to process option rom image.
243 **/
244 EFI_STATUS
245 ProcessOptionRom (
246 IN PCI_IO_DEVICE *Bridge,
247 IN UINT64 RomBase,
248 IN UINT64 MaxLength
249 )
250 {
251 LIST_ENTRY *CurrentLink;
252 PCI_IO_DEVICE *Temp;
253
254 //
255 // Go through bridges to reach all devices
256 //
257 CurrentLink = Bridge->ChildList.ForwardLink;
258 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
259 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
260 if (!IsListEmpty (&Temp->ChildList)) {
261
262 //
263 // Go further to process the option rom under this bridge
264 //
265 ProcessOptionRom (Temp, RomBase, MaxLength);
266 }
267
268 if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {
269
270 //
271 // Load and process the option rom
272 //
273 LoadOpRomImage (Temp, RomBase);
274 }
275
276 CurrentLink = CurrentLink->ForwardLink;
277 }
278
279 return EFI_SUCCESS;
280 }
281
282 /**
283 This routine is used to assign bus number to the given PCI bus system
284
285 @param Bridge Parent root bridge instance.
286 @param StartBusNumber Number of beginning.
287 @param SubBusNumber the number of sub bus.
288
289 @retval EFI_SUCCESS Success to assign bus number.
290 **/
291 EFI_STATUS
292 PciAssignBusNumber (
293 IN PCI_IO_DEVICE *Bridge,
294 IN UINT8 StartBusNumber,
295 OUT UINT8 *SubBusNumber
296 )
297 {
298 EFI_STATUS Status;
299 PCI_TYPE00 Pci;
300 UINT8 Device;
301 UINT8 Func;
302 UINT64 Address;
303 UINTN SecondBus;
304 UINT16 Register;
305 UINT8 Register8;
306 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
307
308 PciRootBridgeIo = Bridge->PciRootBridgeIo;
309
310 SecondBus = 0;
311 Register = 0;
312
313 *SubBusNumber = StartBusNumber;
314
315 //
316 // First check to see whether the parent is ppb
317 //
318 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
319 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
320
321 //
322 // Check to see whether a pci device is present
323 //
324
325 Status = PciDevicePresent (
326 PciRootBridgeIo,
327 &Pci,
328 StartBusNumber,
329 Device,
330 Func
331 );
332
333 if (!EFI_ERROR (Status) &&
334 (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {
335
336 //
337 // Reserved one bus for cardbus bridge
338 //
339 SecondBus = ++(*SubBusNumber);
340
341 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
342
343 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
344
345 Status = PciRootBridgeIoWrite (
346 PciRootBridgeIo,
347 &Pci,
348 EfiPciWidthUint16,
349 Address,
350 1,
351 &Register
352 );
353
354 //
355 // Initialize SubBusNumber to SecondBus
356 //
357 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
358 Status = PciRootBridgeIoWrite (
359 PciRootBridgeIo,
360 &Pci,
361 EfiPciWidthUint8,
362 Address,
363 1,
364 SubBusNumber
365 );
366 //
367 // If it is PPB, resursively search down this bridge
368 //
369 if (IS_PCI_BRIDGE (&Pci)) {
370
371 Register8 = 0xFF;
372 Status = PciRootBridgeIoWrite (
373 PciRootBridgeIo,
374 &Pci,
375 EfiPciWidthUint8,
376 Address,
377 1,
378 &Register8
379 );
380
381 Status = PciAssignBusNumber (
382 Bridge,
383 (UINT8) (SecondBus),
384 SubBusNumber
385 );
386
387 if (EFI_ERROR (Status)) {
388 return EFI_DEVICE_ERROR;
389 }
390 }
391
392 //
393 // Set the current maximum bus number under the PPB
394 //
395
396 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
397
398 Status = PciRootBridgeIoWrite (
399 PciRootBridgeIo,
400 &Pci,
401 EfiPciWidthUint8,
402 Address,
403 1,
404 SubBusNumber
405 );
406
407 }
408
409 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
410
411 //
412 // Skip sub functions, this is not a multi function device
413 //
414
415 Func = PCI_MAX_FUNC;
416 }
417 }
418 }
419
420 return EFI_SUCCESS;
421 }
422
423 /**
424 This routine is used to determine the root bridge attribute by interfacing
425 the host bridge resource allocation protocol.
426
427 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
428 @param RootBridgeDev Root bridge instance
429
430 @retval EFI_SUCCESS Success to get root bridge's attribute
431 @retval Others Fail to get attribute
432 **/
433 EFI_STATUS
434 DetermineRootBridgeAttributes (
435 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
436 IN PCI_IO_DEVICE *RootBridgeDev
437 )
438 {
439 UINT64 Attributes;
440 EFI_STATUS Status;
441 EFI_HANDLE RootBridgeHandle;
442
443 Attributes = 0;
444 RootBridgeHandle = RootBridgeDev->Handle;
445
446 //
447 // Get root bridge attribute by calling into pci host bridge resource allocation protocol
448 //
449 Status = PciResAlloc->GetAllocAttributes (
450 PciResAlloc,
451 RootBridgeHandle,
452 &Attributes
453 );
454
455 if (EFI_ERROR (Status)) {
456 return Status;
457 }
458
459 //
460 // Here is the point where PCI bus driver calls HOST bridge allocation protocol
461 // Currently we hardcoded for ea815
462 //
463
464 if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {
465 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;
466 }
467
468 if ((Attributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0) {
469 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;
470 }
471
472 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;
473 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
474 RootBridgeDev->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;
475
476 return EFI_SUCCESS;
477 }
478
479 /**
480 Get Max Option Rom size on this bridge
481
482 @param Bridge Bridge device instance.
483 @return Max size of option rom.
484 **/
485 UINT64
486 GetMaxOptionRomSize (
487 IN PCI_IO_DEVICE *Bridge
488 )
489 {
490 LIST_ENTRY *CurrentLink;
491 PCI_IO_DEVICE *Temp;
492 UINT64 MaxOptionRomSize;
493 UINT64 TempOptionRomSize;
494
495 MaxOptionRomSize = 0;
496
497 //
498 // Go through bridges to reach all devices
499 //
500 CurrentLink = Bridge->ChildList.ForwardLink;
501 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
502 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
503 if (!IsListEmpty (&Temp->ChildList)) {
504
505 //
506 // Get max option rom size under this bridge
507 //
508 TempOptionRomSize = GetMaxOptionRomSize (Temp);
509
510 //
511 // Compare with the option rom size of the bridge
512 // Get the larger one
513 //
514 if (Temp->RomSize > TempOptionRomSize) {
515 TempOptionRomSize = Temp->RomSize;
516 }
517
518 } else {
519
520 //
521 // For devices get the rom size directly
522 //
523 TempOptionRomSize = Temp->RomSize;
524 }
525
526 //
527 // Get the largest rom size on this bridge
528 //
529 if (TempOptionRomSize > MaxOptionRomSize) {
530 MaxOptionRomSize = TempOptionRomSize;
531 }
532
533 CurrentLink = CurrentLink->ForwardLink;
534 }
535
536 return MaxOptionRomSize;
537 }
538
539 /**
540 Process attributes of devices on this host bridge
541
542 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
543
544 @retval EFI_NOT_FOUND Can not find the specific root bridge device.
545 @retval EFI_SUCCESS Success Process attribute.
546 @retval Others Can not determine the root bridge device's attribute.
547 **/
548 EFI_STATUS
549 PciHostBridgeDeviceAttribute (
550 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
551 )
552 {
553 EFI_HANDLE RootBridgeHandle;
554 PCI_IO_DEVICE *RootBridgeDev;
555 EFI_STATUS Status;
556
557 RootBridgeHandle = NULL;
558
559 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
560
561 //
562 // Get RootBridg Device by handle
563 //
564 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
565
566 if (RootBridgeDev == NULL) {
567 return EFI_NOT_FOUND;
568 }
569
570 //
571 // Set the attributes for devcies behind the Root Bridge
572 //
573 Status = DetermineDeviceAttribute (RootBridgeDev);
574 if (EFI_ERROR (Status)) {
575 return Status;
576 }
577
578 }
579
580 return EFI_SUCCESS;
581 }
582
583 /**
584 Get resource allocation status from the ACPI pointer
585
586 @param AcpiConfig Point to Acpi configuration table
587 @param IoResStatus Return the status of I/O resource
588 @param Mem32ResStatus Return the status of 32-bit Memory resource
589 @param PMem32ResStatus Return the status of 32-bit PMemory resource
590 @param Mem64ResStatus Return the status of 64-bit Memory resource
591 @param PMem64ResStatus Return the status of 64-bit PMemory resource
592
593 @retval EFI_SUCCESS Success to get resource allocation status from ACPI configuration table.
594 **/
595 EFI_STATUS
596 GetResourceAllocationStatus (
597 VOID *AcpiConfig,
598 OUT UINT64 *IoResStatus,
599 OUT UINT64 *Mem32ResStatus,
600 OUT UINT64 *PMem32ResStatus,
601 OUT UINT64 *Mem64ResStatus,
602 OUT UINT64 *PMem64ResStatus
603 )
604 {
605
606 UINT8 *Temp;
607 UINT64 ResStatus;
608 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;
609
610 Temp = (UINT8 *) AcpiConfig;
611
612 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
613
614 ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
615 ResStatus = ACPIAddressDesc->AddrTranslationOffset;
616
617 switch (ACPIAddressDesc->ResType) {
618 case 0:
619 if (ACPIAddressDesc->AddrSpaceGranularity == 32) {
620 if (ACPIAddressDesc->SpecificFlag == 0x06) {
621 //
622 // Pmem32
623 //
624 *PMem32ResStatus = ResStatus;
625 } else {
626 //
627 // Mem32
628 //
629 *Mem32ResStatus = ResStatus;
630 }
631 }
632
633 if (ACPIAddressDesc->AddrSpaceGranularity == 64) {
634 if (ACPIAddressDesc->SpecificFlag == 0x06) {
635 //
636 // PMem64
637 //
638 *PMem64ResStatus = ResStatus;
639 } else {
640 //
641 // Mem64
642 //
643 *Mem64ResStatus = ResStatus;
644 }
645 }
646
647 break;
648
649 case 1:
650 //
651 // Io
652 //
653 *IoResStatus = ResStatus;
654 break;
655
656 default:
657 break;
658 }
659
660 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
661 }
662
663 return EFI_SUCCESS;
664 }
665
666 /**
667 Remove a PCI device from device pool and mark its bar
668
669 @param PciDevice Instance of Pci device.
670
671 @retval EFI_SUCCESS Success Operation.
672 @retval EFI_ABORTED Pci device is a root bridge.
673 **/
674 EFI_STATUS
675 RejectPciDevice (
676 IN PCI_IO_DEVICE *PciDevice
677 )
678 {
679 PCI_IO_DEVICE *Bridge;
680 PCI_IO_DEVICE *Temp;
681 LIST_ENTRY *CurrentLink;
682
683 //
684 // Remove the padding resource from a bridge
685 //
686 if ( IS_PCI_BRIDGE(&PciDevice->Pci) && \
687 PciDevice->ResourcePaddingDescriptors != NULL ) {
688 gBS->FreePool (PciDevice->ResourcePaddingDescriptors);
689 PciDevice->ResourcePaddingDescriptors = NULL;
690 return EFI_SUCCESS;
691 }
692
693 //
694 // Skip RB and PPB
695 //
696 if (IS_PCI_BRIDGE (&PciDevice->Pci) || (PciDevice->Parent == NULL)) {
697 return EFI_ABORTED;
698 }
699
700 if (IS_CARDBUS_BRIDGE (&PciDevice->Pci)) {
701 //
702 // Get the root bridge device
703 //
704 Bridge = PciDevice;
705 while (Bridge->Parent != NULL) {
706 Bridge = Bridge->Parent;
707 }
708
709 RemoveAllPciDeviceOnBridge (Bridge->Handle, PciDevice);
710
711 //
712 // Mark its bar
713 //
714 InitializeP2C (PciDevice);
715 }
716
717 //
718 // Remove the device
719 //
720 Bridge = PciDevice->Parent;
721 CurrentLink = Bridge->ChildList.ForwardLink;
722 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
723 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
724 if (Temp == PciDevice) {
725 InitializePciDevice (Temp);
726 RemoveEntryList (CurrentLink);
727 FreePciDevice (Temp);
728 return EFI_SUCCESS;
729 }
730
731 CurrentLink = CurrentLink->ForwardLink;
732 }
733
734 return EFI_ABORTED;
735 }
736
737 /**
738 Determine whethter a PCI device can be rejected.
739
740 @param PciResNode Pointer to Pci resource node instance.
741
742 @return whethter a PCI device can be rejected.
743 **/
744 BOOLEAN
745 IsRejectiveDevice (
746 IN PCI_RESOURCE_NODE *PciResNode
747 )
748 {
749 PCI_IO_DEVICE *Temp;
750
751 Temp = PciResNode->PciDev;
752
753 //
754 // Ensure the device is present
755 //
756 if (Temp == NULL) {
757 return FALSE;
758 }
759
760 //
761 // PPB and RB should go ahead
762 //
763 if (IS_PCI_BRIDGE (&Temp->Pci) || (Temp->Parent == NULL)) {
764 return TRUE;
765 }
766
767 //
768 // Skip device on Bus0
769 //
770 if ((Temp->Parent != NULL) && (Temp->BusNumber == 0)) {
771 return FALSE;
772 }
773
774 //
775 // Skip VGA
776 //
777 if (IS_PCI_VGA (&Temp->Pci)) {
778 return FALSE;
779 }
780
781 return TRUE;
782 }
783
784 /**
785 Compare two resource node and get the larger resource consumer
786
787 @param PciResNode1 resource node 1 want to be compared
788 @param PciResNode2 resource node 2 want to be compared
789
790 @return Larger resource consumer.
791 **/
792 PCI_RESOURCE_NODE *
793 GetLargerConsumerDevice (
794 IN PCI_RESOURCE_NODE *PciResNode1,
795 IN PCI_RESOURCE_NODE *PciResNode2
796 )
797 {
798 if (PciResNode2 == NULL) {
799 return PciResNode1;
800 }
801
802 if ((IS_PCI_BRIDGE(&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \
803 && (PciResNode2->ResourceUsage != PciResUsagePadding) )
804 {
805 return PciResNode1;
806 }
807
808 if (PciResNode1 == NULL) {
809 return PciResNode2;
810 }
811
812 if ((PciResNode1->Length) > (PciResNode2->Length)) {
813 return PciResNode1;
814 }
815
816 return PciResNode2;
817
818 }
819
820
821 /**
822 Get the max resource consumer in the host resource pool.
823
824 @param ResPool Pointer to resource pool node.
825
826 @return the max resource consumer in the host resource pool.
827 **/
828 PCI_RESOURCE_NODE *
829 GetMaxResourceConsumerDevice (
830 IN PCI_RESOURCE_NODE *ResPool
831 )
832 {
833 PCI_RESOURCE_NODE *Temp;
834 LIST_ENTRY *CurrentLink;
835 PCI_RESOURCE_NODE *PciResNode;
836 PCI_RESOURCE_NODE *PPBResNode;
837
838 PciResNode = NULL;
839
840 CurrentLink = ResPool->ChildList.ForwardLink;
841 while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {
842
843 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
844
845 if (!IsRejectiveDevice (Temp)) {
846 CurrentLink = CurrentLink->ForwardLink;
847 continue;
848 }
849
850 if ((IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \
851 && (Temp->ResourceUsage != PciResUsagePadding))
852 {
853 PPBResNode = GetMaxResourceConsumerDevice (Temp);
854 PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);
855 } else {
856 PciResNode = GetLargerConsumerDevice (PciResNode, Temp);
857 }
858
859 CurrentLink = CurrentLink->ForwardLink;
860 }
861
862 return PciResNode;
863 }
864
865 /**
866 Adjust host bridge allocation so as to reduce resource requirement
867
868 @param IoPool Pointer to instance of I/O resource Node.
869 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.
870 @param PMem32Pool Pointer to instance of 32-bit Pmemory resource node.
871 @param Mem64Pool Pointer to instance of 64-bit memory resource node.
872 @param PMem64Pool Pointer to instance of 64-bit Pmemory resource node.
873 @param IoResStatus Status of I/O resource Node.
874 @param Mem32ResStatus Status of 32-bit memory resource Node.
875 @param PMem32ResStatus Status of 32-bit Pmemory resource node.
876 @param Mem64ResStatus Status of 64-bit memory resource node.
877 @param PMem64ResStatus Status of 64-bit Pmemory resource node.
878 **/
879 EFI_STATUS
880 PciHostBridgeAdjustAllocation (
881 IN PCI_RESOURCE_NODE *IoPool,
882 IN PCI_RESOURCE_NODE *Mem32Pool,
883 IN PCI_RESOURCE_NODE *PMem32Pool,
884 IN PCI_RESOURCE_NODE *Mem64Pool,
885 IN PCI_RESOURCE_NODE *PMem64Pool,
886 IN UINT64 IoResStatus,
887 IN UINT64 Mem32ResStatus,
888 IN UINT64 PMem32ResStatus,
889 IN UINT64 Mem64ResStatus,
890 IN UINT64 PMem64ResStatus
891 )
892 {
893 BOOLEAN AllocationAjusted;
894 PCI_RESOURCE_NODE *PciResNode;
895 PCI_RESOURCE_NODE *ResPool[5];
896 PCI_IO_DEVICE *RemovedPciDev[5];
897 UINT64 ResStatus[5];
898 UINTN RemovedPciDevNum;
899 UINTN DevIndex;
900 UINTN ResType;
901 EFI_STATUS Status;
902 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;
903
904 PciResNode = NULL;
905 ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));
906 RemovedPciDevNum = 0;
907
908 ResPool[0] = IoPool;
909 ResPool[1] = Mem32Pool;
910 ResPool[2] = PMem32Pool;
911 ResPool[3] = Mem64Pool;
912 ResPool[4] = PMem64Pool;
913
914 ResStatus[0] = IoResStatus;
915 ResStatus[1] = Mem32ResStatus;
916 ResStatus[2] = PMem32ResStatus;
917 ResStatus[3] = Mem64ResStatus;
918 ResStatus[4] = PMem64ResStatus;
919
920 AllocationAjusted = FALSE;
921
922 for (ResType = 0; ResType < 5; ResType++) {
923
924 if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {
925 continue;
926 }
927
928 if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {
929 //
930 // Hostbridge hasn't this resource type
931 //
932 return EFI_ABORTED;
933 }
934
935 //
936 // Hostbridge hasn't enough resource
937 //
938 PciResNode = GetMaxResourceConsumerDevice (ResPool[ResType]);
939 if (PciResNode == NULL) {
940 continue;
941 }
942
943 //
944 // Check if the device has been removed before
945 //
946 for (DevIndex = 0; DevIndex < RemovedPciDevNum; DevIndex++) {
947 if (PciResNode->PciDev == RemovedPciDev[DevIndex]) {
948 break;
949 }
950 }
951
952 if (DevIndex != RemovedPciDevNum) {
953 continue;
954 }
955
956 //
957 // Remove the device if it isn't in the array
958 //
959 Status = RejectPciDevice (PciResNode->PciDev);
960 if (Status == EFI_SUCCESS) {
961
962 //
963 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
964 //
965 //
966 // Have no way to get ReqRes, AllocRes & Bar here
967 //
968 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));
969 AllocFailExtendedData.DevicePathSize = sizeof (EFI_DEVICE_PATH_PROTOCOL);
970 AllocFailExtendedData.DevicePath = (UINT8 *) PciResNode->PciDev->DevicePath;
971 AllocFailExtendedData.Bar = PciResNode->Bar;
972
973 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
974 EFI_PROGRESS_CODE,
975 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
976 (VOID *) &AllocFailExtendedData,
977 sizeof (AllocFailExtendedData)
978 );
979
980 //
981 // Add it to the array and indicate at least a device has been rejected
982 //
983 RemovedPciDev[RemovedPciDevNum++] = PciResNode->PciDev;
984 AllocationAjusted = TRUE;
985 }
986 }
987 //
988 // End for
989 //
990
991 if (AllocationAjusted) {
992 return EFI_SUCCESS;
993 } else {
994 return EFI_ABORTED;
995 }
996 }
997
998 /**
999 Summary requests for all resource type, and contruct ACPI resource
1000 requestor instance.
1001
1002 @param Bridge detecting bridge
1003 @param IoNode Pointer to instance of I/O resource Node
1004 @param Mem32Node Pointer to instance of 32-bit memory resource Node
1005 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node
1006 @param Mem64Node Pointer to instance of 64-bit memory resource node
1007 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node
1008 @param Config Output buffer holding new constructed APCI resource requestor
1009 **/
1010 EFI_STATUS
1011 ConstructAcpiResourceRequestor (
1012 IN PCI_IO_DEVICE *Bridge,
1013 IN PCI_RESOURCE_NODE *IoNode,
1014 IN PCI_RESOURCE_NODE *Mem32Node,
1015 IN PCI_RESOURCE_NODE *PMem32Node,
1016 IN PCI_RESOURCE_NODE *Mem64Node,
1017 IN PCI_RESOURCE_NODE *PMem64Node,
1018 OUT VOID **Config
1019 )
1020 {
1021 UINT8 NumConfig;
1022 UINT8 Aperture;
1023 UINT8 *Configuration;
1024 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1025 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
1026
1027 NumConfig = 0;
1028 Aperture = 0;
1029
1030 *Config = NULL;
1031
1032 //
1033 // if there is io request, add to the io aperture
1034 //
1035 if (ResourceRequestExisted (IoNode)) {
1036 NumConfig++;
1037 Aperture |= 0x01;
1038 }
1039
1040 //
1041 // if there is mem32 request, add to the mem32 aperture
1042 //
1043 if (ResourceRequestExisted (Mem32Node)) {
1044 NumConfig++;
1045 Aperture |= 0x02;
1046 }
1047
1048 //
1049 // if there is pmem32 request, add to the pmem32 aperture
1050 //
1051 if (ResourceRequestExisted (PMem32Node)) {
1052 NumConfig++;
1053 Aperture |= 0x04;
1054 }
1055
1056 //
1057 // if there is mem64 request, add to the mem64 aperture
1058 //
1059 if (ResourceRequestExisted (Mem64Node)) {
1060 NumConfig++;
1061 Aperture |= 0x08;
1062 }
1063
1064 //
1065 // if there is pmem64 request, add to the pmem64 aperture
1066 //
1067 if (ResourceRequestExisted (PMem64Node)) {
1068 NumConfig++;
1069 Aperture |= 0x10;
1070 }
1071
1072 if (NumConfig != 0) {
1073
1074 //
1075 // If there is at least one type of resource request,
1076 // allocate a acpi resource node
1077 //
1078 Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1079 if (Configuration == NULL) {
1080 return EFI_OUT_OF_RESOURCES;
1081 }
1082
1083 ZeroMem (
1084 Configuration,
1085 sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
1086 );
1087
1088 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
1089
1090 //
1091 // Deal with io aperture
1092 //
1093 if ((Aperture & 0x01) != 0) {
1094 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1095 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1096 //
1097 // Io
1098 //
1099 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
1100 //
1101 // non ISA range
1102 //
1103 Ptr->SpecificFlag = 1;
1104 Ptr->AddrLen = IoNode->Length;
1105 Ptr->AddrRangeMax = IoNode->Alignment;
1106
1107 Ptr++;
1108 }
1109 //
1110 // Deal with mem32 aperture
1111 //
1112 if ((Aperture & 0x02) != 0) {
1113 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1114 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1115 //
1116 // Mem
1117 //
1118 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1119 //
1120 // Nonprefechable
1121 //
1122 Ptr->SpecificFlag = 0;
1123 //
1124 // 32 bit
1125 //
1126 Ptr->AddrSpaceGranularity = 32;
1127 Ptr->AddrLen = Mem32Node->Length;
1128 Ptr->AddrRangeMax = Mem32Node->Alignment;
1129
1130 Ptr++;
1131 }
1132
1133 //
1134 // Deal with Pmem32 aperture
1135 //
1136 if ((Aperture & 0x04) != 0) {
1137 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1138 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1139 //
1140 // Mem
1141 //
1142 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1143 //
1144 // prefechable
1145 //
1146 Ptr->SpecificFlag = 0x6;
1147 //
1148 // 32 bit
1149 //
1150 Ptr->AddrSpaceGranularity = 32;
1151 Ptr->AddrLen = PMem32Node->Length;
1152 Ptr->AddrRangeMax = PMem32Node->Alignment;
1153
1154 Ptr++;
1155 }
1156 //
1157 // Deal with mem64 aperture
1158 //
1159 if ((Aperture & 0x08) != 0) {
1160 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1161 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1162 //
1163 // Mem
1164 //
1165 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1166 //
1167 // nonprefechable
1168 //
1169 Ptr->SpecificFlag = 0;
1170 //
1171 // 64 bit
1172 //
1173 Ptr->AddrSpaceGranularity = 64;
1174 Ptr->AddrLen = Mem64Node->Length;
1175 Ptr->AddrRangeMax = Mem64Node->Alignment;
1176
1177 Ptr++;
1178 }
1179 //
1180 // Deal with Pmem64 aperture
1181 //
1182 if ((Aperture & 0x10) != 0) {
1183 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1184 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1185 //
1186 // Mem
1187 //
1188 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1189 //
1190 // prefechable
1191 //
1192 Ptr->SpecificFlag = 0x06;
1193 //
1194 // 64 bit
1195 //
1196 Ptr->AddrSpaceGranularity = 64;
1197 Ptr->AddrLen = PMem64Node->Length;
1198 Ptr->AddrRangeMax = PMem64Node->Alignment;
1199
1200 Ptr++;
1201 }
1202
1203 //
1204 // put the checksum
1205 //
1206 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr;
1207
1208 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
1209 PtrEnd->Checksum = 0;
1210
1211 } else {
1212
1213 //
1214 // If there is no resource request
1215 //
1216 Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1217 if (Configuration == NULL) {
1218 return EFI_OUT_OF_RESOURCES;
1219 }
1220
1221 ZeroMem (Configuration, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1222
1223 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);
1224 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1225
1226 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Ptr + 1);
1227 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
1228 PtrEnd->Checksum = 0;
1229 }
1230
1231 *Config = Configuration;
1232
1233 return EFI_SUCCESS;
1234 }
1235
1236 /**
1237 Get resource base from an acpi configuration descriptor.
1238
1239 @param Config an acpi configuration descriptor.
1240 @param IoBase output of I/O resource base address.
1241 @param Mem32Base output of 32-bit memory base address.
1242 @param PMem32Base output of 32-bit pmemory base address.
1243 @param Mem64Base output of 64-bit memory base address.
1244 @param PMem64Base output of 64-bit pmemory base address.
1245
1246 @return EFI_SUCCESS Get resource base address successfully.
1247
1248 **/
1249 EFI_STATUS
1250 GetResourceBase (
1251 IN VOID *Config,
1252 OUT UINT64 *IoBase,
1253 OUT UINT64 *Mem32Base,
1254 OUT UINT64 *PMem32Base,
1255 OUT UINT64 *Mem64Base,
1256 OUT UINT64 *PMem64Base
1257 )
1258 {
1259 UINT8 *Temp;
1260 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1261 UINT64 ResStatus;
1262
1263 ASSERT (Config != NULL);
1264
1265 *IoBase = 0xFFFFFFFFFFFFFFFFULL;
1266 *Mem32Base = 0xFFFFFFFFFFFFFFFFULL;
1267 *PMem32Base = 0xFFFFFFFFFFFFFFFFULL;
1268 *Mem64Base = 0xFFFFFFFFFFFFFFFFULL;
1269 *PMem64Base = 0xFFFFFFFFFFFFFFFFULL;
1270
1271 Temp = (UINT8 *) Config;
1272
1273 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
1274
1275 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
1276 ResStatus = Ptr->AddrTranslationOffset;
1277
1278 if (ResStatus == EFI_RESOURCE_SATISFIED) {
1279
1280 switch (Ptr->ResType) {
1281
1282 //
1283 // Memory type aperture
1284 //
1285 case 0:
1286
1287 //
1288 // Check to see the granularity
1289 //
1290 if (Ptr->AddrSpaceGranularity == 32) {
1291 if ((Ptr->SpecificFlag & 0x06) != 0) {
1292 *PMem32Base = Ptr->AddrRangeMin;
1293 } else {
1294 *Mem32Base = Ptr->AddrRangeMin;
1295 }
1296 }
1297
1298 if (Ptr->AddrSpaceGranularity == 64) {
1299 if ((Ptr->SpecificFlag & 0x06) != 0) {
1300 *PMem64Base = Ptr->AddrRangeMin;
1301 } else {
1302 *Mem64Base = Ptr->AddrRangeMin;
1303 }
1304 }
1305 break;
1306
1307 case 1:
1308
1309 //
1310 // Io type aperture
1311 //
1312 *IoBase = Ptr->AddrRangeMin;
1313 break;
1314
1315 default:
1316 break;
1317
1318 }
1319 //
1320 // End switch
1321 //
1322 }
1323 //
1324 // End for
1325 //
1326 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1327 }
1328
1329 return EFI_SUCCESS;
1330 }
1331
1332 /**
1333 Enumerate pci bridge, allocate resource and determine attribute
1334 for devices on this bridge
1335
1336 @param BridgeDev Pointer to instance of bridge device.
1337
1338 @retval EFI_SUCCESS Success operation.
1339 @retval Others Fail to enumerate.
1340 **/
1341 EFI_STATUS
1342 PciBridgeEnumerator (
1343 IN PCI_IO_DEVICE *BridgeDev
1344 )
1345 {
1346 UINT8 SubBusNumber;
1347 UINT8 StartBusNumber;
1348 EFI_PCI_IO_PROTOCOL *PciIo;
1349 EFI_STATUS Status;
1350
1351 SubBusNumber = 0;
1352 StartBusNumber = 0;
1353 PciIo = &(BridgeDev->PciIo);
1354 Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
1355
1356 if (EFI_ERROR (Status)) {
1357 return Status;
1358 }
1359
1360 Status = PciAssignBusNumber (
1361 BridgeDev,
1362 StartBusNumber,
1363 &SubBusNumber
1364 );
1365
1366 if (EFI_ERROR (Status)) {
1367 return Status;
1368 }
1369
1370 Status = PciPciDeviceInfoCollector (BridgeDev, StartBusNumber);
1371
1372 if (EFI_ERROR (Status)) {
1373 return Status;
1374 }
1375
1376 Status = PciBridgeResourceAllocator (BridgeDev);
1377
1378 if (EFI_ERROR (Status)) {
1379 return Status;
1380 }
1381
1382 Status = DetermineDeviceAttribute (BridgeDev);
1383
1384 if (EFI_ERROR (Status)) {
1385 return Status;
1386 }
1387
1388 return EFI_SUCCESS;
1389
1390 }
1391
1392 /**
1393 Allocate all kinds of resource for bridge
1394
1395 @param Bridge Pointer to bridge instance.
1396
1397 @retval EFI_SUCCESS Success operation.
1398 @retval Others Fail to allocate resource for bridge.
1399 **/
1400 EFI_STATUS
1401 PciBridgeResourceAllocator (
1402 IN PCI_IO_DEVICE *Bridge
1403 )
1404 {
1405 PCI_RESOURCE_NODE *IoBridge;
1406 PCI_RESOURCE_NODE *Mem32Bridge;
1407 PCI_RESOURCE_NODE *PMem32Bridge;
1408 PCI_RESOURCE_NODE *Mem64Bridge;
1409 PCI_RESOURCE_NODE *PMem64Bridge;
1410 UINT64 IoBase;
1411 UINT64 Mem32Base;
1412 UINT64 PMem32Base;
1413 UINT64 Mem64Base;
1414 UINT64 PMem64Base;
1415 EFI_STATUS Status;
1416
1417 IoBridge = CreateResourceNode (
1418 Bridge,
1419 0,
1420 0xFFF,
1421 0,
1422 PciBarTypeIo16,
1423 PciResUsageTypical
1424 );
1425
1426 Mem32Bridge = CreateResourceNode (
1427 Bridge,
1428 0,
1429 0xFFFFF,
1430 0,
1431 PciBarTypeMem32,
1432 PciResUsageTypical
1433 );
1434
1435 PMem32Bridge = CreateResourceNode (
1436 Bridge,
1437 0,
1438 0xFFFFF,
1439 0,
1440 PciBarTypePMem32,
1441 PciResUsageTypical
1442 );
1443
1444 Mem64Bridge = CreateResourceNode (
1445 Bridge,
1446 0,
1447 0xFFFFF,
1448 0,
1449 PciBarTypeMem64,
1450 PciResUsageTypical
1451 );
1452
1453 PMem64Bridge = CreateResourceNode (
1454 Bridge,
1455 0,
1456 0xFFFFF,
1457 0,
1458 PciBarTypePMem64,
1459 PciResUsageTypical
1460 );
1461
1462 //
1463 // Create resourcemap by going through all the devices subject to this root bridge
1464 //
1465 Status = CreateResourceMap (
1466 Bridge,
1467 IoBridge,
1468 Mem32Bridge,
1469 PMem32Bridge,
1470 Mem64Bridge,
1471 PMem64Bridge
1472 );
1473
1474 if (EFI_ERROR (Status)) {
1475 return Status;
1476 }
1477
1478 Status = GetResourceBaseFromBridge (
1479 Bridge,
1480 &IoBase,
1481 &Mem32Base,
1482 &PMem32Base,
1483 &Mem64Base,
1484 &PMem64Base
1485 );
1486
1487 if (EFI_ERROR (Status)) {
1488 return Status;
1489 }
1490
1491 //
1492 // Program IO resources
1493 //
1494 ProgramResource (
1495 IoBase,
1496 IoBridge
1497 );
1498
1499 //
1500 // Program Mem32 resources
1501 //
1502 ProgramResource (
1503 Mem32Base,
1504 Mem32Bridge
1505 );
1506
1507 //
1508 // Program PMem32 resources
1509 //
1510 ProgramResource (
1511 PMem32Base,
1512 PMem32Bridge
1513 );
1514
1515 //
1516 // Program Mem64 resources
1517 //
1518 ProgramResource (
1519 Mem64Base,
1520 Mem64Bridge
1521 );
1522
1523 //
1524 // Program PMem64 resources
1525 //
1526 ProgramResource (
1527 PMem64Base,
1528 PMem64Bridge
1529 );
1530
1531 DestroyResourceTree (IoBridge);
1532 DestroyResourceTree (Mem32Bridge);
1533 DestroyResourceTree (PMem32Bridge);
1534 DestroyResourceTree (PMem64Bridge);
1535 DestroyResourceTree (Mem64Bridge);
1536
1537 gBS->FreePool (IoBridge);
1538 gBS->FreePool (Mem32Bridge);
1539 gBS->FreePool (PMem32Bridge);
1540 gBS->FreePool (PMem64Bridge);
1541 gBS->FreePool (Mem64Bridge);
1542
1543 return EFI_SUCCESS;
1544 }
1545
1546 /**
1547 Get resource base address for a pci bridge device
1548
1549 @param Bridge Given Pci driver instance.
1550 @param IoBase output for base address of I/O type resource.
1551 @param Mem32Base output for base address of 32-bit memory type resource.
1552 @param PMem32Base output for base address of 32-bit Pmemory type resource.
1553 @param Mem64Base output for base address of 64-bit memory type resource.
1554 @param PMem64Base output for base address of 64-bit Pmemory type resource.
1555
1556 @retval EFI_SUCCESS Succes to get resource base address.
1557 **/
1558 EFI_STATUS
1559 GetResourceBaseFromBridge (
1560 IN PCI_IO_DEVICE *Bridge,
1561 OUT UINT64 *IoBase,
1562 OUT UINT64 *Mem32Base,
1563 OUT UINT64 *PMem32Base,
1564 OUT UINT64 *Mem64Base,
1565 OUT UINT64 *PMem64Base
1566 )
1567 {
1568 if (!Bridge->Allocated) {
1569 return EFI_OUT_OF_RESOURCES;
1570 }
1571
1572 *IoBase = gAllOne;
1573 *Mem32Base = gAllOne;
1574 *PMem32Base = gAllOne;
1575 *Mem64Base = gAllOne;
1576 *PMem64Base = gAllOne;
1577
1578 if (IS_PCI_BRIDGE (&Bridge->Pci)) {
1579
1580 if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {
1581 *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;
1582 }
1583
1584 if (Bridge->PciBar[PPB_MEM32_RANGE].Length > 0) {
1585 *Mem32Base = Bridge->PciBar[PPB_MEM32_RANGE].BaseAddress;
1586 }
1587
1588 if (Bridge->PciBar[PPB_PMEM32_RANGE].Length > 0) {
1589 *PMem32Base = Bridge->PciBar[PPB_PMEM32_RANGE].BaseAddress;
1590 }
1591
1592 if (Bridge->PciBar[PPB_PMEM64_RANGE].Length > 0) {
1593 *PMem64Base = Bridge->PciBar[PPB_PMEM64_RANGE].BaseAddress;
1594 } else {
1595 *PMem64Base = gAllOne;
1596 }
1597
1598 }
1599
1600 if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {
1601 if (Bridge->PciBar[P2C_IO_1].Length > 0) {
1602 *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress;
1603 } else {
1604 if (Bridge->PciBar[P2C_IO_2].Length > 0) {
1605 *IoBase = Bridge->PciBar[P2C_IO_2].BaseAddress;
1606 }
1607 }
1608
1609 if (Bridge->PciBar[P2C_MEM_1].Length > 0) {
1610 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypePMem32) {
1611 *PMem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;
1612 }
1613
1614 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypeMem32) {
1615 *Mem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;
1616 }
1617 }
1618
1619 if (Bridge->PciBar[P2C_MEM_2].Length > 0) {
1620 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypePMem32) {
1621 *PMem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;
1622 }
1623
1624 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypeMem32) {
1625 *Mem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;
1626 }
1627 }
1628 }
1629
1630 return EFI_SUCCESS;
1631 }
1632
1633 /**
1634 These are the notifications from the PCI bus driver that it is about to enter a certain
1635 phase of the PCI enumeration process.
1636
1637 This member function can be used to notify the host bridge driver to perform specific actions,
1638 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
1639 Eight notification points are defined at this time. See belows:
1640 EfiPciHostBridgeBeginEnumeration - Resets the host bridge PCI apertures and internal data
1641 structures. The PCI enumerator should issue this notification
1642 before starting a fresh enumeration process. Enumeration cannot
1643 be restarted after sending any other notification such as
1644 EfiPciHostBridgeBeginBusAllocation.
1645 EfiPciHostBridgeBeginBusAllocation - The bus allocation phase is about to begin. No specific action is
1646 required here. This notification can be used to perform any
1647 chipset-specific programming.
1648 EfiPciHostBridgeEndBusAllocation - The bus allocation and bus programming phase is complete. No
1649 specific action is required here. This notification can be used to
1650 perform any chipset-specific programming.
1651 EfiPciHostBridgeBeginResourceAllocation - The resource allocation phase is about to begin. No specific
1652 action is required here. This notification can be used to perform
1653 any chipset-specific programming.
1654 EfiPciHostBridgeAllocateResources - Allocates resources per previously submitted requests for all the PCI
1655 root bridges. These resource settings are returned on the next call to
1656 GetProposedResources(). Before calling NotifyPhase() with a Phase of
1657 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible for gathering I/O and memory requests for
1658 all the PCI root bridges and submitting these requests using
1659 SubmitResources(). This function pads the resource amount
1660 to suit the root bridge hardware, takes care of dependencies between
1661 the PCI root bridges, and calls the Global Coherency Domain (GCD)
1662 with the allocation request. In the case of padding, the allocated range
1663 could be bigger than what was requested.
1664 EfiPciHostBridgeSetResources - Programs the host bridge hardware to decode previously allocated
1665 resources (proposed resources) for all the PCI root bridges. After the
1666 hardware is programmed, reassigning resources will not be supported.
1667 The bus settings are not affected.
1668 EfiPciHostBridgeFreeResources - Deallocates resources that were previously allocated for all the PCI
1669 root bridges and resets the I/O and memory apertures to their initial
1670 state. The bus settings are not affected. If the request to allocate
1671 resources fails, the PCI enumerator can use this notification to
1672 deallocate previous resources, adjust the requests, and retry
1673 allocation.
1674 EfiPciHostBridgeEndResourceAllocation- The resource allocation phase is completed. No specific action is
1675 required here. This notification can be used to perform any chipsetspecific
1676 programming.
1677
1678 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
1679 @param[in] Phase The phase during enumeration
1680
1681 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
1682 is valid for a Phase of EfiPciHostBridgeAllocateResources if
1683 SubmitResources() has not been called for one or more
1684 PCI root bridges before this call
1685 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
1686 for a Phase of EfiPciHostBridgeSetResources.
1687 @retval EFI_INVALID_PARAMETER Invalid phase parameter
1688 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1689 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
1690 previously submitted resource requests cannot be fulfilled or
1691 were only partially fulfilled.
1692 @retval EFI_SUCCESS The notification was accepted without any errors.
1693
1694 **/
1695 EFI_STATUS
1696 NotifyPhase (
1697 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
1698 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
1699 )
1700 {
1701 EFI_HANDLE HostBridgeHandle;
1702 EFI_HANDLE RootBridgeHandle;
1703 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
1704 EFI_STATUS Status;
1705
1706 HostBridgeHandle = NULL;
1707 RootBridgeHandle = NULL;
1708 if (gPciPlatformProtocol != NULL) {
1709 //
1710 // Get Host Bridge Handle.
1711 //
1712 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);
1713
1714 //
1715 // Get the rootbridge Io protocol to find the host bridge handle
1716 //
1717 Status = gBS->HandleProtocol (
1718 RootBridgeHandle,
1719 &gEfiPciRootBridgeIoProtocolGuid,
1720 (VOID **) &PciRootBridgeIo
1721 );
1722
1723 if (EFI_ERROR (Status)) {
1724 return EFI_NOT_FOUND;
1725 }
1726
1727 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
1728
1729 //
1730 // Call PlatformPci::PlatformNotify() if the protocol is present.
1731 //
1732 gPciPlatformProtocol->PlatformNotify (
1733 gPciPlatformProtocol,
1734 HostBridgeHandle,
1735 Phase,
1736 ChipsetEntry
1737 );
1738 }
1739
1740 Status = PciResAlloc->NotifyPhase (
1741 PciResAlloc,
1742 Phase
1743 );
1744
1745 if (gPciPlatformProtocol != NULL) {
1746 //
1747 // Call PlatformPci::PlatformNotify() if the protocol is present.
1748 //
1749 gPciPlatformProtocol->PlatformNotify (
1750 gPciPlatformProtocol,
1751 HostBridgeHandle,
1752 Phase,
1753 ChipsetExit
1754 );
1755
1756 }
1757
1758 return EFI_SUCCESS;
1759 }
1760
1761 /**
1762 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1763 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1764 PCI controllers before enumeration.
1765
1766 This function is called during the PCI enumeration process. No specific action is expected from this
1767 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1768 enumeration.
1769
1770 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1771 @param Bus The bus number of the pci device.
1772 @param Device The device number of the pci device.
1773 @param Func The function number of the pci device.
1774 @param Phase The phase of the PCI device enumeration.
1775
1776 @retval EFI_SUCCESS The requested parameters were returned.
1777 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1778 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
1779 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1780 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
1781 not enumerate this device, including its child devices if it is a PCI-to-PCI
1782 bridge.
1783
1784 **/
1785 EFI_STATUS
1786 PreprocessController (
1787 IN PCI_IO_DEVICE *Bridge,
1788 IN UINT8 Bus,
1789 IN UINT8 Device,
1790 IN UINT8 Func,
1791 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
1792 )
1793 {
1794 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress;
1795 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;
1796 EFI_HANDLE RootBridgeHandle;
1797 EFI_HANDLE HostBridgeHandle;
1798 EFI_STATUS Status;
1799
1800 //
1801 // Get the host bridge handle
1802 //
1803 HostBridgeHandle = Bridge->PciRootBridgeIo->ParentHandle;
1804
1805 //
1806 // Get the pci host bridge resource allocation protocol
1807 //
1808 Status = gBS->OpenProtocol (
1809 HostBridgeHandle,
1810 &gEfiPciHostBridgeResourceAllocationProtocolGuid,
1811 (VOID **) &PciResAlloc,
1812 NULL,
1813 NULL,
1814 EFI_OPEN_PROTOCOL_GET_PROTOCOL
1815 );
1816
1817 if (EFI_ERROR (Status)) {
1818 return EFI_UNSUPPORTED;
1819 }
1820
1821 //
1822 // Get Root Brige Handle
1823 //
1824 while (Bridge->Parent != NULL) {
1825 Bridge = Bridge->Parent;
1826 }
1827
1828 RootBridgeHandle = Bridge->Handle;
1829
1830 RootBridgePciAddress.Register = 0;
1831 RootBridgePciAddress.Function = Func;
1832 RootBridgePciAddress.Device = Device;
1833 RootBridgePciAddress.Bus = Bus;
1834 RootBridgePciAddress.ExtendedRegister = 0;
1835
1836 if (gPciPlatformProtocol != NULL) {
1837 //
1838 // Call PlatformPci::PrepController() if the protocol is present.
1839 //
1840 gPciPlatformProtocol->PlatformPrepController (
1841 gPciPlatformProtocol,
1842 HostBridgeHandle,
1843 RootBridgeHandle,
1844 RootBridgePciAddress,
1845 Phase,
1846 ChipsetEntry
1847 );
1848 }
1849
1850 Status = PciResAlloc->PreprocessController (
1851 PciResAlloc,
1852 RootBridgeHandle,
1853 RootBridgePciAddress,
1854 Phase
1855 );
1856
1857 if (gPciPlatformProtocol != NULL) {
1858 //
1859 // Call PlatformPci::PrepController() if the protocol is present.
1860 //
1861 gPciPlatformProtocol->PlatformPrepController (
1862 gPciPlatformProtocol,
1863 HostBridgeHandle,
1864 RootBridgeHandle,
1865 RootBridgePciAddress,
1866 Phase,
1867 ChipsetExit
1868 );
1869 }
1870
1871 return EFI_SUCCESS;
1872 }
1873
1874 /**
1875 Hot plug request notify.
1876
1877 @param This - A pointer to the hot plug request protocol.
1878 @param Operation - The operation.
1879 @param Controller - A pointer to the controller.
1880 @param RemainingDevicePath - A pointer to the device path.
1881 @param NumberOfChildren - A the number of child handle in the ChildHandleBuffer.
1882 @param ChildHandleBuffer - A pointer to the array contain the child handle.
1883
1884 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.
1885 @retval EFI_SUCCESS Success operating.
1886 **/
1887 EFI_STATUS
1888 EFIAPI
1889 PciHotPlugRequestNotify (
1890 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,
1891 IN EFI_PCI_HOTPLUG_OPERATION Operation,
1892 IN EFI_HANDLE Controller,
1893 IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,
1894 IN OUT UINT8 *NumberOfChildren,
1895 IN OUT EFI_HANDLE * ChildHandleBuffer
1896 )
1897 {
1898 PCI_IO_DEVICE *Bridge;
1899 PCI_IO_DEVICE *Temp;
1900 EFI_PCI_IO_PROTOCOL *PciIo;
1901 UINTN Index;
1902 EFI_HANDLE RootBridgeHandle;
1903 EFI_STATUS Status;
1904
1905 Status = gBS->OpenProtocol (
1906 Controller,
1907 &gEfiPciIoProtocolGuid,
1908 (VOID **) &PciIo,
1909 gPciBusDriverBinding.DriverBindingHandle,
1910 Controller,
1911 EFI_OPEN_PROTOCOL_GET_PROTOCOL
1912 );
1913
1914 if (EFI_ERROR (Status)) {
1915 return EFI_NOT_FOUND;
1916 }
1917
1918 Bridge = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
1919
1920 //
1921 // Get root bridge handle
1922 //
1923 Temp = Bridge;
1924 while (Temp->Parent != NULL) {
1925 Temp = Temp->Parent;
1926 }
1927
1928 RootBridgeHandle = Temp->Handle;
1929
1930 if (Operation == EfiPciHotPlugRequestAdd) {
1931
1932 if (NumberOfChildren != NULL) {
1933 *NumberOfChildren = 0;
1934 }
1935
1936 if (IsListEmpty (&Bridge->ChildList)) {
1937
1938 Status = PciBridgeEnumerator (Bridge);
1939
1940 if (EFI_ERROR (Status)) {
1941 return Status;
1942 }
1943 }
1944
1945 Status = StartPciDevicesOnBridge (
1946 RootBridgeHandle,
1947 Bridge,
1948 RemainingDevicePath,
1949 NumberOfChildren,
1950 ChildHandleBuffer
1951 );
1952
1953 return EFI_SUCCESS;
1954 }
1955
1956 if (Operation == EfiPciHotplugRequestRemove) {
1957
1958 if (*NumberOfChildren == 0) {
1959 //
1960 // Remove all devices on the bridge
1961 //
1962 Status = RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);
1963 return Status;
1964
1965 }
1966
1967 for (Index = 0; Index < *NumberOfChildren; Index++) {
1968 //
1969 // De register all the pci device
1970 //
1971 Status = DeRegisterPciDevice (RootBridgeHandle, ChildHandleBuffer[Index]);
1972
1973 if (EFI_ERROR (Status)) {
1974 return Status;
1975 }
1976
1977 }
1978 //
1979 // End for
1980 //
1981 return EFI_SUCCESS;
1982 }
1983
1984 return EFI_SUCCESS;
1985 }
1986
1987 /**
1988 Search hostbridge according to given handle
1989
1990 @param RootBridgeHandle - Host bridge handle.
1991
1992 @return TRUE Found.
1993 @return FALSE Not found.
1994 **/
1995 BOOLEAN
1996 SearchHostBridgeHandle (
1997 IN EFI_HANDLE RootBridgeHandle
1998 )
1999 {
2000 EFI_HANDLE HostBridgeHandle;
2001 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
2002 UINTN Index;
2003 EFI_STATUS Status;
2004
2005 //
2006 // Get the rootbridge Io protocol to find the host bridge handle
2007 //
2008 Status = gBS->OpenProtocol (
2009 RootBridgeHandle,
2010 &gEfiPciRootBridgeIoProtocolGuid,
2011 (VOID **) &PciRootBridgeIo,
2012 gPciBusDriverBinding.DriverBindingHandle,
2013 RootBridgeHandle,
2014 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2015 );
2016
2017 if (EFI_ERROR (Status)) {
2018 return FALSE;
2019 }
2020
2021 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
2022 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {
2023 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {
2024 return TRUE;
2025 }
2026 }
2027
2028 return FALSE;
2029 }
2030
2031 /**
2032 Add host bridge handle to global variable for enumating.
2033
2034 @param HostBridgeHandle host bridge handle.
2035 **/
2036 EFI_STATUS
2037 AddHostBridgeEnumerator (
2038 IN EFI_HANDLE HostBridgeHandle
2039 )
2040 {
2041 UINTN Index;
2042
2043 if (HostBridgeHandle == NULL) {
2044 return EFI_ABORTED;
2045 }
2046
2047 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {
2048 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {
2049 return EFI_ABORTED;
2050 }
2051 }
2052
2053 if (Index < PCI_MAX_HOST_BRIDGE_NUM) {
2054 gPciHostBrigeHandles[Index] = HostBridgeHandle;
2055 gPciHostBridgeNumber++;
2056 }
2057
2058 return EFI_SUCCESS;
2059 }
2060
EFI Development Kit II mirror for PVE