IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/pcibus.h

   1 /**@file
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 **/
  13
  14
  15 #ifndef _EFI_PCI_BUS_H
  16 #define _EFI_PCI_BUS_H
  17
  18
  19 #include <FrameworkDxe.h>
  20
  21
  22 #include <Protocol/LoadedImage.h>
  23 #include <Protocol/PciHostBridgeResourceAllocation.h>
  24 #include <Protocol/PciIo.h>
  25 #include <Guid/PciHotplugDevice.h>
  26 #include <Protocol/PciRootBridgeIo.h>
  27 #include <Protocol/PciHotPlugRequest.h>
  28 #include <Protocol/DevicePath.h>
  29 #include <Protocol/PciPlatform.h>
  30 #include <Protocol/PciHotPlugInit.h>
  31 #include <Protocol/Decompress.h>
  32 #include <Guid/PciOptionRomTable.h>
  33 #include <Protocol/BusSpecificDriverOverride.h>
  34 #include <Protocol/UgaIo.h>
  35
  36 #include <Library/DebugLib.h>
  37 #include <Library/UefiDriverEntryPoint.h>
  38 #include <Library/BaseLib.h>
  39 #include <Library/UefiLib.h>
  40 #include <Library/BaseMemoryLib.h>
  41 #include <Library/ReportStatusCodeLib.h>
  42 #include <Library/MemoryAllocationLib.h>
  43 #include <Library/UefiBootServicesTableLib.h>
  44 #include <Library/DevicePathLib.h>
  45 #include <Library/PcdLib.h>
  46 #include <Library/PciIncompatibleDeviceSupportLib.h>
  47
  48 #include <IndustryStandard/Pci23.h>
  49 #include <IndustryStandard/PeImage.h>
  50 #include <IndustryStandard/Acpi.h>
  51 #include "ComponentName.h"
  52
  53 //
  54 // Driver Produced Protocol Prototypes
  55 //
  56
  57 #define VGABASE1  0x3B0
  58 #define VGALIMIT1 0x3BB
  59
  60 #define VGABASE2  0x3C0
  61 #define VGALIMIT2 0x3DF
  62
  63 #define ISABASE   0x100
  64 #define ISALIMIT  0x3FF
  65
  66 typedef enum {
  67   PciBarTypeUnknown = 0,
  68   PciBarTypeIo16,
  69   PciBarTypeIo32,
  70   PciBarTypeMem32,
  71   PciBarTypePMem32,
  72   PciBarTypeMem64,
  73   PciBarTypePMem64,
  74   PciBarTypeIo,
  75   PciBarTypeMem,
  76   PciBarTypeMaxType
  77 } PCI_BAR_TYPE;
  78
  79 typedef struct {
  80   UINT64        BaseAddress;
  81   UINT64        Length;
  82   UINT64        Alignment;
  83   PCI_BAR_TYPE  BarType;
  84   BOOLEAN       Prefetchable;
  85   UINT8         MemType;
  86   UINT8         Offset;
  87 } PCI_BAR;
  88
  89 #define PPB_BAR_0                             0
  90 #define PPB_BAR_1                             1
  91 #define PPB_IO_RANGE                          2
  92 #define PPB_MEM32_RANGE                       3
  93 #define PPB_PMEM32_RANGE                      4
  94 #define PPB_PMEM64_RANGE                      5
  95 #define PPB_MEM64_RANGE                       0xFF
  96
  97 #define P2C_BAR_0                             0
  98 #define P2C_MEM_1                             1
  99 #define P2C_MEM_2                             2
 100 #define P2C_IO_1                              3
 101 #define P2C_IO_2                              4
 102
 103 #define PCI_IO_DEVICE_SIGNATURE               EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')
 104
 105 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 106 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 107 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 108 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 109 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 110 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 111 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 112
 113 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 114 //
 115 // Define resource status constant
 116 //
 117 #define EFI_RESOURCE_NONEXISTENT  0xFFFFFFFFFFFFFFFFULL
 118 #define EFI_RESOURCE_LESS         0xFFFFFFFFFFFFFFFEULL
 119 #define EFI_RESOURCE_SATISFIED    0x0000000000000000ULL
 120
 121 //
 122 // Define option for attribute
 123 //
 124 #define EFI_SET_SUPPORTS    0
 125 #define EFI_SET_ATTRIBUTES  1
 126
 127 typedef struct _PCI_IO_DEVICE {
 128   UINT32                                    Signature;
 129   EFI_HANDLE                                Handle;
 130   EFI_PCI_IO_PROTOCOL                       PciIo;
 131   LIST_ENTRY                                Link;
 132
 133   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 134   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 135   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 136
 137   //
 138   // PCI configuration space header type
 139   //
 140   PCI_TYPE00                                Pci;
 141
 142   //
 143   // Bus number, Device number, Function number
 144   //
 145   UINT8                                     BusNumber;
 146   UINT8                                     DeviceNumber;
 147   UINT8                                     FunctionNumber;
 148
 149   //
 150   // BAR for this PCI Device
 151   //
 152   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 153
 154   //
 155   // The bridge device this pci device is subject to
 156   //
 157   struct _PCI_IO_DEVICE                     *Parent;
 158
 159   //
 160   // A linked list for children Pci Device if it is bridge device
 161   //
 162   LIST_ENTRY                                ChildList;
 163
 164   //
 165   // TURE if the PCI bus driver creates the handle for this PCI device
 166   //
 167   BOOLEAN                                   Registered;
 168
 169   //
 170   // TRUE if the PCI bus driver successfully allocates the resource required by
 171   // this PCI device
 172   //
 173   BOOLEAN                                   Allocated;
 174
 175   //
 176   // The attribute this PCI device currently set
 177   //
 178   UINT64                                    Attributes;
 179
 180   //
 181   // The attributes this PCI device actually supports
 182   //
 183   UINT64                                    Supports;
 184
 185   //
 186   // The resource decode the bridge supports
 187   //
 188   UINT32                                    Decodes;
 189
 190   //
 191   // The OptionRom Size
 192   //
 193   UINT64                                    RomSize;
 194
 195   //
 196   // The OptionRom Size
 197   //
 198   UINT64                                    RomBase;
 199
 200   //
 201   // TRUE if all OpROM (in device or in platform specific position) have been processed
 202   //
 203   BOOLEAN                                   AllOpRomProcessed;
 204
 205   //
 206   // TRUE if there is any EFI driver in the OptionRom
 207   //
 208   BOOLEAN                                   BusOverride;
 209
 210   //
 211   //  A list tracking reserved resource on a bridge device
 212   //
 213   LIST_ENTRY                                ReservedResourceList;
 214
 215   //
 216   // A list tracking image handle of platform specific overriding driver
 217   //
 218   LIST_ENTRY                                OptionRomDriverList;
 219
 220   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 221   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 222
 223   BOOLEAN                                   IsPciExp;
 224
 225 } PCI_IO_DEVICE;
 226
 227
 228 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 229   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 230
 231 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 232   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 233
 234 #define PCI_IO_DEVICE_FROM_LINK(a) \
 235   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 236
 237 //
 238 // Global Variables
 239 //
 240 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 241 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 242 extern LIST_ENTRY                                   gPciDevicePool;
 243 extern BOOLEAN                                      gFullEnumeration;
 244 extern UINTN                                        gPciHostBridgeNumber;
 245 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 246 extern UINT64                                       gAllOne;
 247 extern UINT64                                       gAllZero;
 248
 249 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 250
 251 #include "PciIo.h"
 252 #include "PciCommand.h"
 253 #include "PciDeviceSupport.h"
 254 #include "PciEnumerator.h"
 255 #include "PciEnumeratorSupport.h"
 256 #include "PciDriverOverride.h"
 257 #include "PciRomTable.h"
 258 #include "PciOptionRomSupport.h"
 259 #include "PciPowerManagement.h"
 260 #include "PciHotPlugSupport.h"
 261 #include "PciLib.h"
 262
 263 //
 264 // PCI Bus Support Function Prototypes
 265 //
 266 EFI_STATUS
 267 EFIAPI
 268 PciBusDriverBindingSupported (
 269   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 270   IN EFI_HANDLE                     Controller,
 271   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 272   );
 273
 274 EFI_STATUS
 275 EFIAPI
 276 PciBusDriverBindingStart (
 277   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 278   IN EFI_HANDLE                     Controller,
 279   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 280   );
 281
 282 EFI_STATUS
 283 EFIAPI
 284 PciBusDriverBindingStop (
 285   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 286   IN  EFI_HANDLE                    Controller,
 287   IN  UINTN                         NumberOfChildren,
 288   IN  EFI_HANDLE                    *ChildHandleBuffer
 289   );
 290
 291 #endif