IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/pcibus.h

   1 /**@file
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 **/
  13
  14
  15 #ifndef _EFI_PCI_BUS_H
  16 #define _EFI_PCI_BUS_H
  17
  18
  19 #include <FrameworkDxe.h>
  20
  21
  22 #include <Protocol/LoadedImage.h>
  23 #include <Protocol/PciHostBridgeResourceAllocation.h>
  24 #include <Protocol/PciIo.h>
  25 #include <Guid/PciHotplugDevice.h>
  26 #include <Protocol/PciRootBridgeIo.h>
  27 #include <Protocol/PciHotPlugRequest.h>
  28 #include <Protocol/DevicePath.h>
  29 #include <Protocol/PciPlatform.h>
  30 #include <Protocol/PciHotPlugInit.h>
  31 #include <Protocol/Decompress.h>
  32 #include <Guid/PciOptionRomTable.h>
  33 #include <Protocol/BusSpecificDriverOverride.h>
  34 #include <Protocol/UgaIo.h>
  35 #include <Protocol/IncompatiblePciDeviceSupport.h>
  36
  37 #include <Library/DebugLib.h>
  38 #include <Library/UefiDriverEntryPoint.h>
  39 #include <Library/BaseLib.h>
  40 #include <Library/UefiLib.h>
  41 #include <Library/BaseMemoryLib.h>
  42 #include <Library/ReportStatusCodeLib.h>
  43 #include <Library/MemoryAllocationLib.h>
  44 #include <Library/UefiBootServicesTableLib.h>
  45 #include <Library/DevicePathLib.h>
  46 #include <Library/PcdLib.h>
  47 #include <Library/PciIncompatibleDeviceSupportLib.h>
  48
  49 #include <IndustryStandard/Pci23.h>
  50 #include <IndustryStandard/PeImage.h>
  51 #include <IndustryStandard/Acpi.h>
  52 #include "ComponentName.h"
  53
  54 //
  55 // Driver Produced Protocol Prototypes
  56 //
  57
  58 #define VGABASE1  0x3B0
  59 #define VGALIMIT1 0x3BB
  60
  61 #define VGABASE2  0x3C0
  62 #define VGALIMIT2 0x3DF
  63
  64 #define ISABASE   0x100
  65 #define ISALIMIT  0x3FF
  66
  67 typedef enum {
  68   PciBarTypeUnknown = 0,
  69   PciBarTypeIo16,
  70   PciBarTypeIo32,
  71   PciBarTypeMem32,
  72   PciBarTypePMem32,
  73   PciBarTypeMem64,
  74   PciBarTypePMem64,
  75   PciBarTypeIo,
  76   PciBarTypeMem,
  77   PciBarTypeMaxType
  78 } PCI_BAR_TYPE;
  79
  80 typedef struct {
  81   UINT64        BaseAddress;
  82   UINT64        Length;
  83   UINT64        Alignment;
  84   PCI_BAR_TYPE  BarType;
  85   BOOLEAN       Prefetchable;
  86   UINT8         MemType;
  87   UINT8         Offset;
  88 } PCI_BAR;
  89
  90 #define PPB_BAR_0                             0
  91 #define PPB_BAR_1                             1
  92 #define PPB_IO_RANGE                          2
  93 #define PPB_MEM32_RANGE                       3
  94 #define PPB_PMEM32_RANGE                      4
  95 #define PPB_PMEM64_RANGE                      5
  96 #define PPB_MEM64_RANGE                       0xFF
  97
  98 #define P2C_BAR_0                             0
  99 #define P2C_MEM_1                             1
 100 #define P2C_MEM_2                             2
 101 #define P2C_IO_1                              3
 102 #define P2C_IO_2                              4
 103
 104 #define PCI_IO_DEVICE_SIGNATURE               EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')
 105
 106 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 107 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 108 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 109 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 110 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 111 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 112 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 113
 114 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 115 //
 116 // Define resource status constant
 117 //
 118 #define EFI_RESOURCE_NONEXISTENT  0xFFFFFFFFFFFFFFFFULL
 119 #define EFI_RESOURCE_LESS         0xFFFFFFFFFFFFFFFEULL
 120 #define EFI_RESOURCE_SATISFIED    0x0000000000000000ULL
 121
 122 //
 123 // Define option for attribute
 124 //
 125 #define EFI_SET_SUPPORTS    0
 126 #define EFI_SET_ATTRIBUTES  1
 127
 128 typedef struct _PCI_IO_DEVICE {
 129   UINT32                                    Signature;
 130   EFI_HANDLE                                Handle;
 131   EFI_PCI_IO_PROTOCOL                       PciIo;
 132   LIST_ENTRY                                Link;
 133
 134   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 135   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 136   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 137
 138   //
 139   // PCI configuration space header type
 140   //
 141   PCI_TYPE00                                Pci;
 142
 143   //
 144   // Bus number, Device number, Function number
 145   //
 146   UINT8                                     BusNumber;
 147   UINT8                                     DeviceNumber;
 148   UINT8                                     FunctionNumber;
 149
 150   //
 151   // BAR for this PCI Device
 152   //
 153   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 154
 155   //
 156   // The bridge device this pci device is subject to
 157   //
 158   struct _PCI_IO_DEVICE                     *Parent;
 159
 160   //
 161   // A linked list for children Pci Device if it is bridge device
 162   //
 163   LIST_ENTRY                                ChildList;
 164
 165   //
 166   // TURE if the PCI bus driver creates the handle for this PCI device
 167   //
 168   BOOLEAN                                   Registered;
 169
 170   //
 171   // TRUE if the PCI bus driver successfully allocates the resource required by
 172   // this PCI device
 173   //
 174   BOOLEAN                                   Allocated;
 175
 176   //
 177   // The attribute this PCI device currently set
 178   //
 179   UINT64                                    Attributes;
 180
 181   //
 182   // The attributes this PCI device actually supports
 183   //
 184   UINT64                                    Supports;
 185
 186   //
 187   // The resource decode the bridge supports
 188   //
 189   UINT32                                    Decodes;
 190
 191   //
 192   // The OptionRom Size
 193   //
 194   UINT64                                    RomSize;
 195
 196   //
 197   // The OptionRom Size
 198   //
 199   UINT64                                    RomBase;
 200
 201   //
 202   // TRUE if all OpROM (in device or in platform specific position) have been processed
 203   //
 204   BOOLEAN                                   AllOpRomProcessed;
 205
 206   //
 207   // TRUE if there is any EFI driver in the OptionRom
 208   //
 209   BOOLEAN                                   BusOverride;
 210
 211   //
 212   //  A list tracking reserved resource on a bridge device
 213   //
 214   LIST_ENTRY                                ReservedResourceList;
 215
 216   //
 217   // A list tracking image handle of platform specific overriding driver
 218   //
 219   LIST_ENTRY                                OptionRomDriverList;
 220
 221   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 222   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 223
 224   BOOLEAN                                   IsPciExp;
 225
 226 } PCI_IO_DEVICE;
 227
 228
 229 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 230   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 231
 232 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 233   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 234
 235 #define PCI_IO_DEVICE_FROM_LINK(a) \
 236   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 237
 238 //
 239 // Global Variables
 240 //
 241 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
 242 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 243 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 244 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 245 extern LIST_ENTRY                                   gPciDevicePool;
 246 extern BOOLEAN                                      gFullEnumeration;
 247 extern UINTN                                        gPciHostBridgeNumber;
 248 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 249 extern UINT64                                       gAllOne;
 250 extern UINT64                                       gAllZero;
 251
 252 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 253
 254 #include "PciIo.h"
 255 #include "PciCommand.h"
 256 #include "PciDeviceSupport.h"
 257 #include "PciEnumerator.h"
 258 #include "PciEnumeratorSupport.h"
 259 #include "PciDriverOverride.h"
 260 #include "PciRomTable.h"
 261 #include "PciOptionRomSupport.h"
 262 #include "PciPowerManagement.h"
 263 #include "PciHotPlugSupport.h"
 264 #include "PciLib.h"
 265
 266 //
 267 // PCI Bus Support Function Prototypes
 268 //
 269 EFI_STATUS
 270 EFIAPI
 271 PciBusDriverBindingSupported (
 272   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 273   IN EFI_HANDLE                     Controller,
 274   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 275   );
 276
 277 EFI_STATUS
 278 EFIAPI
 279 PciBusDriverBindingStart (
 280   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 281   IN EFI_HANDLE                     Controller,
 282   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 283   );
 284
 285 EFI_STATUS
 286 EFIAPI
 287 PciBusDriverBindingStop (
 288   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 289   IN  EFI_HANDLE                    Controller,
 290   IN  UINTN                         NumberOfChildren,
 291   IN  EFI_HANDLE                    *ChildHandleBuffer
 292   );
 293
 294 #endif