IntelFrameworkPkg/Library/DxeIoLibCpuIo/IoLib.c

   1 /** @file
   2   I/O Library.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  IoLib.c
  14
  15 **/
  16
  17 #include "DxeCpuIoLibInternal.h"
  18
  19 //
  20 // Globle varible to cache pointer to CpuIo protocol.
  21 //
  22 STATIC EFI_CPU_IO_PROTOCOL              *mCpuIo = NULL;
  23 STATIC EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *mPciRootBridgeIo = NULL;
  24
  25 /**
  26   The constructor function caches the pointer to CpuIo protocol.
  27
  28   The constructor function locates CpuIo protocol from protocol database.
  29   It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
  30
  31   @param  ImageHandle   The firmware allocated handle for the EFI image.
  32   @param  SystemTable   A pointer to the EFI System Table.
  33
  34   @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.
  35
  36 **/
  37 EFI_STATUS
  38 EFIAPI
  39 IoLibConstructor (
  40   IN      EFI_HANDLE                ImageHandle,
  41   IN      EFI_SYSTEM_TABLE          *SystemTable
  42   )
  43 {
  44   EFI_STATUS                        Status;
  45
  46   Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, &mPciRootBridgeIo);
  47   if (EFI_ERROR (Status)) {
  48     Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, &mCpuIo);
  49   }
  50   ASSERT_EFI_ERROR (Status);
  51
  52   return Status;
  53 }
  54
  55 /**
  56   Reads registers in the EFI CPU I/O space.
  57
  58   Reads the I/O port specified by Port with registers width specified by Width.
  59   The read value is returned. If such operations are not supported, then ASSERT().
  60   This function must guarantee that all I/O read and write operations are serialized.
  61
  62   @param  Port          The base address of the I/O operation.
  63                         The caller is responsible for aligning the Address if required.
  64   @param  Width         The width of the I/O operation.
  65
  66   @return Data read from registers in the EFI CPU I/O space.
  67
  68 **/
  69 UINT64
  70 EFIAPI
  71 IoReadWorker (
  72   IN      UINTN                     Port,
  73   IN      EFI_CPU_IO_PROTOCOL_WIDTH Width
  74   )
  75 {
  76   EFI_STATUS                        Status;
  77   UINT64                            Data;
  78
  79   if (mPciRootBridgeIo != NULL) {
  80     Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, Width, Port, 1, &Data);
  81   } else {
  82     Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);
  83   }
  84   ASSERT_EFI_ERROR (Status);
  85
  86   return Data;
  87 }
  88
  89 /**
  90   Writes registers in the EFI CPU I/O space.
  91
  92   Writes the I/O port specified by Port with registers width and value specified by Width
  93   and Data respectively.  Data is returned. If such operations are not supported, then ASSERT().
  94   This function must guarantee that all I/O read and write operations are serialized.
  95
  96   @param  Port          The base address of the I/O operation.
  97                         The caller is responsible for aligning the Address if required.
  98   @param  Width         The width of the I/O operation.
  99   @param  Data          The value to write to the I/O port.
 100
 101   @return The paramter of Data.
 102
 103 **/
 104 UINT64
 105 EFIAPI
 106 IoWriteWorker (
 107   IN      UINTN                     Port,
 108   IN      EFI_CPU_IO_PROTOCOL_WIDTH Width,
 109   IN      UINT64                    Data
 110   )
 111 {
 112   EFI_STATUS                        Status;
 113
 114   if (mPciRootBridgeIo != NULL) {
 115     Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, Width, Port, 1, &Data);
 116   } else {
 117     Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);
 118   }
 119   ASSERT_EFI_ERROR (Status);
 120
 121   return Data;
 122 }
 123
 124 /**
 125   Reads memory-mapped registers in the EFI system memory space.
 126
 127   Reads the MMIO registers specified by Address with registers width specified by Width.
 128   The read value is returned. If such operations are not supported, then ASSERT().
 129   This function must guarantee that all MMIO read and write operations are serialized.
 130
 131   @param  Address       The MMIO register to read.
 132                         The caller is responsible for aligning the Address if required.
 133   @param  Width         The width of the I/O operation.
 134
 135   @return Data read from registers in the EFI system memory space.
 136
 137 **/
 138 UINT64
 139 EFIAPI
 140 MmioReadWorker (
 141   IN      UINTN                     Address,
 142   IN      EFI_CPU_IO_PROTOCOL_WIDTH Width
 143   )
 144 {
 145   EFI_STATUS                        Status;
 146   UINT64                            Data;
 147
 148   if (mPciRootBridgeIo != NULL) {
 149     Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, Width, Address, 1, &Data);
 150   } else {
 151     Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);
 152   }
 153   ASSERT_EFI_ERROR (Status);
 154
 155   return Data;
 156 }
 157
 158 /**
 159   Writes memory-mapped registers in the EFI system memory space.
 160
 161   Writes the MMIO registers specified by Address with registers width and value specified by Width
 162   and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
 163   This function must guarantee that all MMIO read and write operations are serialized.
 164
 165   @param  Address       The MMIO register to read.
 166                         The caller is responsible for aligning the Address if required.
 167   @param  Width         The width of the I/O operation.
 168
 169   @return Data read from registers in the EFI system memory space.
 170
 171 **/
 172 UINT64
 173 EFIAPI
 174 MmioWriteWorker (
 175   IN      UINTN                     Address,
 176   IN      EFI_CPU_IO_PROTOCOL_WIDTH Width,
 177   IN      UINT64                    Data
 178   )
 179 {
 180   EFI_STATUS                        Status;
 181
 182   if (mPciRootBridgeIo != NULL) {
 183     Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, Width, Address, 1, &Data);
 184   } else {
 185     Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);
 186   }
 187   ASSERT_EFI_ERROR (Status);
 188
 189   return Data;
 190 }
 191
 192 /**
 193   Reads an 8-bit I/O port.
 194
 195   Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
 196   This function must guarantee that all I/O read and write operations are
 197   serialized.
 198
 199   If 8-bit I/O port operations are not supported, then ASSERT().
 200
 201   @param  Port  The I/O port to read.
 202
 203   @return The value read.
 204
 205 **/
 206 UINT8
 207 EFIAPI
 208 IoRead8 (
 209   IN      UINTN                     Port
 210   )
 211 {
 212   return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);
 213 }
 214
 215 /**
 216   Writes an 8-bit I/O port.
 217
 218   Writes the 8-bit I/O port specified by Port with the value specified by Value
 219   and returns Value. This function must guarantee that all I/O read and write
 220   operations are serialized.
 221
 222   If 8-bit I/O port operations are not supported, then ASSERT().
 223
 224   @param  Port  The I/O port to write.
 225   @param  Value The value to write to the I/O port.
 226
 227   @return The value written the I/O port.
 228
 229 **/
 230 UINT8
 231 EFIAPI
 232 IoWrite8 (
 233   IN      UINTN                     Port,
 234   IN      UINT8                     Value
 235   )
 236 {
 237   return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);
 238 }
 239
 240 /**
 241   Reads a 16-bit I/O port.
 242
 243   Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
 244   This function must guarantee that all I/O read and write operations are
 245   serialized.
 246
 247   If 16-bit I/O port operations are not supported, then ASSERT().
 248
 249   @param  Port  The I/O port to read.
 250
 251   @return The value read.
 252
 253 **/
 254 UINT16
 255 EFIAPI
 256 IoRead16 (
 257   IN      UINTN                     Port
 258   )
 259 {
 260   //
 261   // Make sure Port is aligned on a 16-bit boundary.
 262   //
 263   ASSERT ((Port & 1) == 0);
 264   return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);
 265 }
 266
 267 /**
 268   Writes a 16-bit I/O port.
 269
 270   Writes the 16-bit I/O port specified by Port with the value specified by Value
 271   and returns Value. This function must guarantee that all I/O read and write
 272   operations are serialized.
 273
 274   If 16-bit I/O port operations are not supported, then ASSERT().
 275
 276   @param  Port  The I/O port to write.
 277   @param  Value The value to write to the I/O port.
 278
 279   @return The value written the I/O port.
 280
 281 **/
 282 UINT16
 283 EFIAPI
 284 IoWrite16 (
 285   IN      UINTN                     Port,
 286   IN      UINT16                    Value
 287   )
 288 {
 289   //
 290   // Make sure Port is aligned on a 16-bit boundary.
 291   //
 292   ASSERT ((Port & 1) == 0);
 293   return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);
 294 }
 295
 296 /**
 297   Reads a 32-bit I/O port.
 298
 299   Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
 300   This function must guarantee that all I/O read and write operations are
 301   serialized.
 302
 303   If 32-bit I/O port operations are not supported, then ASSERT().
 304
 305   @param  Port  The I/O port to read.
 306
 307   @return The value read.
 308
 309 **/
 310 UINT32
 311 EFIAPI
 312 IoRead32 (
 313   IN      UINTN                     Port
 314   )
 315 {
 316   //
 317   // Make sure Port is aligned on a 32-bit boundary.
 318   //
 319   ASSERT ((Port & 3) == 0);
 320   return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);
 321 }
 322
 323 /**
 324   Writes a 32-bit I/O port.
 325
 326   Writes the 32-bit I/O port specified by Port with the value specified by Value
 327   and returns Value. This function must guarantee that all I/O read and write
 328   operations are serialized.
 329
 330   If 32-bit I/O port operations are not supported, then ASSERT().
 331
 332   @param  Port  The I/O port to write.
 333   @param  Value The value to write to the I/O port.
 334
 335   @return The value written the I/O port.
 336
 337 **/
 338 UINT32
 339 EFIAPI
 340 IoWrite32 (
 341   IN      UINTN                     Port,
 342   IN      UINT32                    Value
 343   )
 344 {
 345   //
 346   // Make sure Port is aligned on a 32-bit boundary.
 347   //
 348   ASSERT ((Port & 3) == 0);
 349   return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);
 350 }
 351
 352 /**
 353   Reads a 64-bit I/O port.
 354
 355   Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
 356   This function must guarantee that all I/O read and write operations are
 357   serialized.
 358
 359   If 64-bit I/O port operations are not supported, then ASSERT().
 360
 361   @param  Port  The I/O port to read.
 362
 363   @return The value read.
 364
 365 **/
 366 UINT64
 367 EFIAPI
 368 IoRead64 (
 369   IN      UINTN                     Port
 370   )
 371 {
 372   //
 373   // Make sure Port is aligned on a 64-bit boundary.
 374   //
 375   ASSERT ((Port & 7) == 0);
 376   return IoReadWorker (Port, EfiCpuIoWidthUint64);
 377 }
 378
 379 /**
 380   Writes a 64-bit I/O port.
 381
 382   Writes the 64-bit I/O port specified by Port with the value specified by Value
 383   and returns Value. This function must guarantee that all I/O read and write
 384   operations are serialized.
 385
 386   If 64-bit I/O port operations are not supported, then ASSERT().
 387
 388   @param  Port  The I/O port to write.
 389   @param  Value The value to write to the I/O port.
 390
 391   @return The value written the I/O port.
 392
 393 **/
 394 UINT64
 395 EFIAPI
 396 IoWrite64 (
 397   IN      UINTN                     Port,
 398   IN      UINT64                    Value
 399   )
 400 {
 401   //
 402   // Make sure Port is aligned on a 64-bit boundary.
 403   //
 404   ASSERT ((Port & 7) == 0);
 405   return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);
 406 }
 407
 408 /**
 409   Reads an 8-bit MMIO register.
 410
 411   Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
 412   returned. This function must guarantee that all MMIO read and write
 413   operations are serialized.
 414
 415   If 8-bit MMIO register operations are not supported, then ASSERT().
 416
 417   @param  Address The MMIO register to read.
 418
 419   @return The value read.
 420
 421 **/
 422 UINT8
 423 EFIAPI
 424 MmioRead8 (
 425   IN      UINTN                     Address
 426   )
 427 {
 428   return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);
 429 }
 430
 431 /**
 432   Writes an 8-bit MMIO register.
 433
 434   Writes the 8-bit MMIO register specified by Address with the value specified
 435   by Value and returns Value. This function must guarantee that all MMIO read
 436   and write operations are serialized.
 437
 438   If 8-bit MMIO register operations are not supported, then ASSERT().
 439
 440   @param  Address The MMIO register to write.
 441   @param  Value   The value to write to the MMIO register.
 442
 443 **/
 444 UINT8
 445 EFIAPI
 446 MmioWrite8 (
 447   IN      UINTN                     Address,
 448   IN      UINT8                     Value
 449   )
 450 {
 451   return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);
 452 }
 453
 454 /**
 455   Reads a 16-bit MMIO register.
 456
 457   Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
 458   returned. This function must guarantee that all MMIO read and write
 459   operations are serialized.
 460
 461   If 16-bit MMIO register operations are not supported, then ASSERT().
 462
 463   @param  Address The MMIO register to read.
 464
 465   @return The value read.
 466
 467 **/
 468 UINT16
 469 EFIAPI
 470 MmioRead16 (
 471   IN      UINTN                     Address
 472   )
 473 {
 474   //
 475   // Make sure Address is aligned on a 16-bit boundary.
 476   //
 477   ASSERT ((Address & 1) == 0);
 478   return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);
 479 }
 480
 481 /**
 482   Writes a 16-bit MMIO register.
 483
 484   Writes the 16-bit MMIO register specified by Address with the value specified
 485   by Value and returns Value. This function must guarantee that all MMIO read
 486   and write operations are serialized.
 487
 488   If 16-bit MMIO register operations are not supported, then ASSERT().
 489
 490   @param  Address The MMIO register to write.
 491   @param  Value   The value to write to the MMIO register.
 492
 493 **/
 494 UINT16
 495 EFIAPI
 496 MmioWrite16 (
 497   IN      UINTN                     Address,
 498   IN      UINT16                    Value
 499   )
 500 {
 501   //
 502   // Make sure Address is aligned on a 16-bit boundary.
 503   //
 504   ASSERT ((Address & 1) == 0);
 505   return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);
 506 }
 507
 508 /**
 509   Reads a 32-bit MMIO register.
 510
 511   Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
 512   returned. This function must guarantee that all MMIO read and write
 513   operations are serialized.
 514
 515   If 32-bit MMIO register operations are not supported, then ASSERT().
 516
 517   @param  Address The MMIO register to read.
 518
 519   @return The value read.
 520
 521 **/
 522 UINT32
 523 EFIAPI
 524 MmioRead32 (
 525   IN      UINTN                     Address
 526   )
 527 {
 528   //
 529   // Make sure Address is aligned on a 32-bit boundary.
 530   //
 531   ASSERT ((Address & 3) == 0);
 532   return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);
 533 }
 534
 535 /**
 536   Writes a 32-bit MMIO register.
 537
 538   Writes the 32-bit MMIO register specified by Address with the value specified
 539   by Value and returns Value. This function must guarantee that all MMIO read
 540   and write operations are serialized.
 541
 542   If 32-bit MMIO register operations are not supported, then ASSERT().
 543
 544   @param  Address The MMIO register to write.
 545   @param  Value   The value to write to the MMIO register.
 546
 547 **/
 548 UINT32
 549 EFIAPI
 550 MmioWrite32 (
 551   IN      UINTN                     Address,
 552   IN      UINT32                    Value
 553   )
 554 {
 555   //
 556   // Make sure Address is aligned on a 32-bit boundary.
 557   //
 558   ASSERT ((Address & 3) == 0);
 559   return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);
 560 }
 561
 562 /**
 563   Reads a 64-bit MMIO register.
 564
 565   Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
 566   returned. This function must guarantee that all MMIO read and write
 567   operations are serialized.
 568
 569   If 64-bit MMIO register operations are not supported, then ASSERT().
 570
 571   @param  Address The MMIO register to read.
 572
 573   @return The value read.
 574
 575 **/
 576 UINT64
 577 EFIAPI
 578 MmioRead64 (
 579   IN      UINTN                     Address
 580   )
 581 {
 582   //
 583   // Make sure Address is aligned on a 64-bit boundary.
 584   //
 585   ASSERT ((Address & 7) == 0);
 586   return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);
 587 }
 588
 589 /**
 590   Writes a 64-bit MMIO register.
 591
 592   Writes the 64-bit MMIO register specified by Address with the value specified
 593   by Value and returns Value. This function must guarantee that all MMIO read
 594   and write operations are serialized.
 595
 596   If 64-bit MMIO register operations are not supported, then ASSERT().
 597
 598   @param  Address The MMIO register to write.
 599   @param  Value   The value to write to the MMIO register.
 600
 601 **/
 602 UINT64
 603 EFIAPI
 604 MmioWrite64 (
 605   IN      UINTN                     Address,
 606   IN      UINT64                    Value
 607   )
 608 {
 609   //
 610   // Make sure Address is aligned on a 64-bit boundary.
 611   //
 612   ASSERT ((Address & 7) == 0);
 613   return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);
 614 }