e124e39b6cae59ddfeaf9c75bcb4e2cc4a5e09da
[mirror_edk2.git] / IntelFrameworkPkg / Library / DxeIoLibCpuIo / IoLib.c
1 /** @file
2 I/O Library.
3
4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 Module Name: IoLib.c
14
15 **/
16
17 //
18 // Include common header file for this module.
19 //
20 #include "CommonHeader.h"
21
22 #include "DxeCpuIoLibInternal.h"
23
24 //
25 // Globle varible to cache pointer to CpuIo protocol.
26 //
27 STATIC EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;
28 STATIC EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;
29
30 /**
31 The constructor function caches the pointer to CpuIo protocol.
32
33 The constructor function locates CpuIo protocol from protocol database.
34 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
35
36 @param ImageHandle The firmware allocated handle for the EFI image.
37 @param SystemTable A pointer to the EFI System Table.
38
39 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
40
41 **/
42 EFI_STATUS
43 EFIAPI
44 IoLibConstructor (
45 IN EFI_HANDLE ImageHandle,
46 IN EFI_SYSTEM_TABLE *SystemTable
47 )
48 {
49 EFI_STATUS Status;
50
51 Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, &mPciRootBridgeIo);
52 if (EFI_ERROR (Status)) {
53 Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, &mCpuIo);
54 }
55 ASSERT_EFI_ERROR (Status);
56
57 return Status;
58 }
59
60 /**
61 Reads registers in the EFI CPU I/O space.
62
63 Reads the I/O port specified by Port with registers width specified by Width.
64 The read value is returned. If such operations are not supported, then ASSERT().
65 This function must guarantee that all I/O read and write operations are serialized.
66
67 @param Port The base address of the I/O operation.
68 The caller is responsible for aligning the Address if required.
69 @param Width The width of the I/O operation.
70
71 @return Data read from registers in the EFI CPU I/O space.
72
73 **/
74 UINT64
75 EFIAPI
76 IoReadWorker (
77 IN UINTN Port,
78 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
79 )
80 {
81 EFI_STATUS Status;
82 UINT64 Data;
83
84 if (mPciRootBridgeIo != NULL) {
85 Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, Width, Port, 1, &Data);
86 } else {
87 Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);
88 }
89 ASSERT_EFI_ERROR (Status);
90
91 return Data;
92 }
93
94 /**
95 Writes registers in the EFI CPU I/O space.
96
97 Writes the I/O port specified by Port with registers width and value specified by Width
98 and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
99 This function must guarantee that all I/O read and write operations are serialized.
100
101 @param Port The base address of the I/O operation.
102 The caller is responsible for aligning the Address if required.
103 @param Width The width of the I/O operation.
104 @param Data The value to write to the I/O port.
105
106 @return The paramter of Data.
107
108 **/
109 UINT64
110 EFIAPI
111 IoWriteWorker (
112 IN UINTN Port,
113 IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
114 IN UINT64 Data
115 )
116 {
117 EFI_STATUS Status;
118
119 if (mPciRootBridgeIo != NULL) {
120 Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, Width, Port, 1, &Data);
121 } else {
122 Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);
123 }
124 ASSERT_EFI_ERROR (Status);
125
126 return Data;
127 }
128
129 /**
130 Reads memory-mapped registers in the EFI system memory space.
131
132 Reads the MMIO registers specified by Address with registers width specified by Width.
133 The read value is returned. If such operations are not supported, then ASSERT().
134 This function must guarantee that all MMIO read and write operations are serialized.
135
136 @param Address The MMIO register to read.
137 The caller is responsible for aligning the Address if required.
138 @param Width The width of the I/O operation.
139
140 @return Data read from registers in the EFI system memory space.
141
142 **/
143 UINT64
144 EFIAPI
145 MmioReadWorker (
146 IN UINTN Address,
147 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
148 )
149 {
150 EFI_STATUS Status;
151 UINT64 Data;
152
153 if (mPciRootBridgeIo != NULL) {
154 Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, Width, Address, 1, &Data);
155 } else {
156 Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);
157 }
158 ASSERT_EFI_ERROR (Status);
159
160 return Data;
161 }
162
163 /**
164 Writes memory-mapped registers in the EFI system memory space.
165
166 Writes the MMIO registers specified by Address with registers width and value specified by Width
167 and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
168 This function must guarantee that all MMIO read and write operations are serialized.
169
170 @param Address The MMIO register to read.
171 The caller is responsible for aligning the Address if required.
172 @param Width The width of the I/O operation.
173
174 @return Data read from registers in the EFI system memory space.
175
176 **/
177 UINT64
178 EFIAPI
179 MmioWriteWorker (
180 IN UINTN Address,
181 IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
182 IN UINT64 Data
183 )
184 {
185 EFI_STATUS Status;
186
187 if (mPciRootBridgeIo != NULL) {
188 Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, Width, Address, 1, &Data);
189 } else {
190 Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);
191 }
192 ASSERT_EFI_ERROR (Status);
193
194 return Data;
195 }
196
197 /**
198 Reads an 8-bit I/O port.
199
200 Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
201 This function must guarantee that all I/O read and write operations are
202 serialized.
203
204 If 8-bit I/O port operations are not supported, then ASSERT().
205
206 @param Port The I/O port to read.
207
208 @return The value read.
209
210 **/
211 UINT8
212 EFIAPI
213 IoRead8 (
214 IN UINTN Port
215 )
216 {
217 return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);
218 }
219
220 /**
221 Writes an 8-bit I/O port.
222
223 Writes the 8-bit I/O port specified by Port with the value specified by Value
224 and returns Value. This function must guarantee that all I/O read and write
225 operations are serialized.
226
227 If 8-bit I/O port operations are not supported, then ASSERT().
228
229 @param Port The I/O port to write.
230 @param Value The value to write to the I/O port.
231
232 @return The value written the I/O port.
233
234 **/
235 UINT8
236 EFIAPI
237 IoWrite8 (
238 IN UINTN Port,
239 IN UINT8 Value
240 )
241 {
242 return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);
243 }
244
245 /**
246 Reads a 16-bit I/O port.
247
248 Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
249 This function must guarantee that all I/O read and write operations are
250 serialized.
251
252 If 16-bit I/O port operations are not supported, then ASSERT().
253
254 @param Port The I/O port to read.
255
256 @return The value read.
257
258 **/
259 UINT16
260 EFIAPI
261 IoRead16 (
262 IN UINTN Port
263 )
264 {
265 //
266 // Make sure Port is aligned on a 16-bit boundary.
267 //
268 ASSERT ((Port & 1) == 0);
269 return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);
270 }
271
272 /**
273 Writes a 16-bit I/O port.
274
275 Writes the 16-bit I/O port specified by Port with the value specified by Value
276 and returns Value. This function must guarantee that all I/O read and write
277 operations are serialized.
278
279 If 16-bit I/O port operations are not supported, then ASSERT().
280
281 @param Port The I/O port to write.
282 @param Value The value to write to the I/O port.
283
284 @return The value written the I/O port.
285
286 **/
287 UINT16
288 EFIAPI
289 IoWrite16 (
290 IN UINTN Port,
291 IN UINT16 Value
292 )
293 {
294 //
295 // Make sure Port is aligned on a 16-bit boundary.
296 //
297 ASSERT ((Port & 1) == 0);
298 return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);
299 }
300
301 /**
302 Reads a 32-bit I/O port.
303
304 Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
305 This function must guarantee that all I/O read and write operations are
306 serialized.
307
308 If 32-bit I/O port operations are not supported, then ASSERT().
309
310 @param Port The I/O port to read.
311
312 @return The value read.
313
314 **/
315 UINT32
316 EFIAPI
317 IoRead32 (
318 IN UINTN Port
319 )
320 {
321 //
322 // Make sure Port is aligned on a 32-bit boundary.
323 //
324 ASSERT ((Port & 3) == 0);
325 return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);
326 }
327
328 /**
329 Writes a 32-bit I/O port.
330
331 Writes the 32-bit I/O port specified by Port with the value specified by Value
332 and returns Value. This function must guarantee that all I/O read and write
333 operations are serialized.
334
335 If 32-bit I/O port operations are not supported, then ASSERT().
336
337 @param Port The I/O port to write.
338 @param Value The value to write to the I/O port.
339
340 @return The value written the I/O port.
341
342 **/
343 UINT32
344 EFIAPI
345 IoWrite32 (
346 IN UINTN Port,
347 IN UINT32 Value
348 )
349 {
350 //
351 // Make sure Port is aligned on a 32-bit boundary.
352 //
353 ASSERT ((Port & 3) == 0);
354 return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);
355 }
356
357 /**
358 Reads a 64-bit I/O port.
359
360 Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
361 This function must guarantee that all I/O read and write operations are
362 serialized.
363
364 If 64-bit I/O port operations are not supported, then ASSERT().
365
366 @param Port The I/O port to read.
367
368 @return The value read.
369
370 **/
371 UINT64
372 EFIAPI
373 IoRead64 (
374 IN UINTN Port
375 )
376 {
377 //
378 // Make sure Port is aligned on a 64-bit boundary.
379 //
380 ASSERT ((Port & 7) == 0);
381 return IoReadWorker (Port, EfiCpuIoWidthUint64);
382 }
383
384 /**
385 Writes a 64-bit I/O port.
386
387 Writes the 64-bit I/O port specified by Port with the value specified by Value
388 and returns Value. This function must guarantee that all I/O read and write
389 operations are serialized.
390
391 If 64-bit I/O port operations are not supported, then ASSERT().
392
393 @param Port The I/O port to write.
394 @param Value The value to write to the I/O port.
395
396 @return The value written the I/O port.
397
398 **/
399 UINT64
400 EFIAPI
401 IoWrite64 (
402 IN UINTN Port,
403 IN UINT64 Value
404 )
405 {
406 //
407 // Make sure Port is aligned on a 64-bit boundary.
408 //
409 ASSERT ((Port & 7) == 0);
410 return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);
411 }
412
413 /**
414 Reads an 8-bit MMIO register.
415
416 Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
417 returned. This function must guarantee that all MMIO read and write
418 operations are serialized.
419
420 If 8-bit MMIO register operations are not supported, then ASSERT().
421
422 @param Address The MMIO register to read.
423
424 @return The value read.
425
426 **/
427 UINT8
428 EFIAPI
429 MmioRead8 (
430 IN UINTN Address
431 )
432 {
433 return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);
434 }
435
436 /**
437 Writes an 8-bit MMIO register.
438
439 Writes the 8-bit MMIO register specified by Address with the value specified
440 by Value and returns Value. This function must guarantee that all MMIO read
441 and write operations are serialized.
442
443 If 8-bit MMIO register operations are not supported, then ASSERT().
444
445 @param Address The MMIO register to write.
446 @param Value The value to write to the MMIO register.
447
448 **/
449 UINT8
450 EFIAPI
451 MmioWrite8 (
452 IN UINTN Address,
453 IN UINT8 Value
454 )
455 {
456 return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);
457 }
458
459 /**
460 Reads a 16-bit MMIO register.
461
462 Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
463 returned. This function must guarantee that all MMIO read and write
464 operations are serialized.
465
466 If 16-bit MMIO register operations are not supported, then ASSERT().
467
468 @param Address The MMIO register to read.
469
470 @return The value read.
471
472 **/
473 UINT16
474 EFIAPI
475 MmioRead16 (
476 IN UINTN Address
477 )
478 {
479 //
480 // Make sure Address is aligned on a 16-bit boundary.
481 //
482 ASSERT ((Address & 1) == 0);
483 return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);
484 }
485
486 /**
487 Writes a 16-bit MMIO register.
488
489 Writes the 16-bit MMIO register specified by Address with the value specified
490 by Value and returns Value. This function must guarantee that all MMIO read
491 and write operations are serialized.
492
493 If 16-bit MMIO register operations are not supported, then ASSERT().
494
495 @param Address The MMIO register to write.
496 @param Value The value to write to the MMIO register.
497
498 **/
499 UINT16
500 EFIAPI
501 MmioWrite16 (
502 IN UINTN Address,
503 IN UINT16 Value
504 )
505 {
506 //
507 // Make sure Address is aligned on a 16-bit boundary.
508 //
509 ASSERT ((Address & 1) == 0);
510 return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);
511 }
512
513 /**
514 Reads a 32-bit MMIO register.
515
516 Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
517 returned. This function must guarantee that all MMIO read and write
518 operations are serialized.
519
520 If 32-bit MMIO register operations are not supported, then ASSERT().
521
522 @param Address The MMIO register to read.
523
524 @return The value read.
525
526 **/
527 UINT32
528 EFIAPI
529 MmioRead32 (
530 IN UINTN Address
531 )
532 {
533 //
534 // Make sure Address is aligned on a 32-bit boundary.
535 //
536 ASSERT ((Address & 3) == 0);
537 return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);
538 }
539
540 /**
541 Writes a 32-bit MMIO register.
542
543 Writes the 32-bit MMIO register specified by Address with the value specified
544 by Value and returns Value. This function must guarantee that all MMIO read
545 and write operations are serialized.
546
547 If 32-bit MMIO register operations are not supported, then ASSERT().
548
549 @param Address The MMIO register to write.
550 @param Value The value to write to the MMIO register.
551
552 **/
553 UINT32
554 EFIAPI
555 MmioWrite32 (
556 IN UINTN Address,
557 IN UINT32 Value
558 )
559 {
560 //
561 // Make sure Address is aligned on a 32-bit boundary.
562 //
563 ASSERT ((Address & 3) == 0);
564 return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);
565 }
566
567 /**
568 Reads a 64-bit MMIO register.
569
570 Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
571 returned. This function must guarantee that all MMIO read and write
572 operations are serialized.
573
574 If 64-bit MMIO register operations are not supported, then ASSERT().
575
576 @param Address The MMIO register to read.
577
578 @return The value read.
579
580 **/
581 UINT64
582 EFIAPI
583 MmioRead64 (
584 IN UINTN Address
585 )
586 {
587 //
588 // Make sure Address is aligned on a 64-bit boundary.
589 //
590 ASSERT ((Address & 7) == 0);
591 return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);
592 }
593
594 /**
595 Writes a 64-bit MMIO register.
596
597 Writes the 64-bit MMIO register specified by Address with the value specified
598 by Value and returns Value. This function must guarantee that all MMIO read
599 and write operations are serialized.
600
601 If 64-bit MMIO register operations are not supported, then ASSERT().
602
603 @param Address The MMIO register to write.
604 @param Value The value to write to the MMIO register.
605
606 **/
607 UINT64
608 EFIAPI
609 MmioWrite64 (
610 IN UINTN Address,
611 IN UINT64 Value
612 )
613 {
614 //
615 // Make sure Address is aligned on a 64-bit boundary.
616 //
617 ASSERT ((Address & 7) == 0);
618 return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);
619 }