IntelFrameworkPkg/Library/DxeIoLibCpuIo/IoLib.c

   1 /** @file
   2   I/O Library.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  IoLib.c
  14
  15 **/
  16
  17
  18 #include "DxeCpuIoLibInternal.h"
  19
  20 //
  21 // Globle varible to cache pointer to CpuIo protocol.
  22 //
  23 STATIC EFI_CPU_IO_PROTOCOL              *mCpuIo = NULL;
  24 STATIC EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *mPciRootBridgeIo = NULL;
  25
  26 /**
  27   The constructor function caches the pointer to CpuIo protocol.
  28
  29   The constructor function locates CpuIo protocol from protocol database.
  30   It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
  31
  32   @param  ImageHandle   The firmware allocated handle for the EFI image.
  33   @param  SystemTable   A pointer to the EFI System Table.
  34
  35   @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.
  36
  37 **/
  38 EFI_STATUS
  39 EFIAPI
  40 IoLibConstructor (
  41   IN      EFI_HANDLE                ImageHandle,
  42   IN      EFI_SYSTEM_TABLE          *SystemTable
  43   )
  44 {
  45   EFI_STATUS                        Status;
  46
  47   Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, &mPciRootBridgeIo);
  48   if (EFI_ERROR (Status)) {
  49     Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, &mCpuIo);
  50   }
  51   ASSERT_EFI_ERROR (Status);
  52
  53   return Status;
  54 }
  55
  56 /**
  57   Reads registers in the EFI CPU I/O space.
  58
  59   Reads the I/O port specified by Port with registers width specified by Width.
  60   The read value is returned. If such operations are not supported, then ASSERT().
  61   This function must guarantee that all I/O read and write operations are serialized.
  62
  63   @param  Port          The base address of the I/O operation.
  64                         The caller is responsible for aligning the Address if required.
  65   @param  Width         The width of the I/O operation.
  66
  67   @return Data read from registers in the EFI CPU I/O space.
  68
  69 **/
  70 UINT64
  71 EFIAPI
  72 IoReadWorker (
  73   IN      UINTN                     Port,
  74   IN      EFI_CPU_IO_PROTOCOL_WIDTH Width
  75   )
  76 {
  77   EFI_STATUS                        Status;
  78   UINT64                            Data;
  79
  80   if (mPciRootBridgeIo != NULL) {
  81     Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, Width, Port, 1, &Data);
  82   } else {
  83     Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);
  84   }
  85   ASSERT_EFI_ERROR (Status);
  86
  87   return Data;
  88 }
  89
  90 /**
  91   Writes registers in the EFI CPU I/O space.
  92
  93   Writes the I/O port specified by Port with registers width and value specified by Width
  94   and Data respectively.  Data is returned. If such operations are not supported, then ASSERT().
  95   This function must guarantee that all I/O read and write operations are serialized.
  96
  97   @param  Port          The base address of the I/O operation.
  98                         The caller is responsible for aligning the Address if required.
  99   @param  Width         The width of the I/O operation.
 100   @param  Data          The value to write to the I/O port.
 101
 102   @return The paramter of Data.
 103
 104 **/
 105 UINT64
 106 EFIAPI
 107 IoWriteWorker (
 108   IN      UINTN                     Port,
 109   IN      EFI_CPU_IO_PROTOCOL_WIDTH Width,
 110   IN      UINT64                    Data
 111   )
 112 {
 113   EFI_STATUS                        Status;
 114
 115   if (mPciRootBridgeIo != NULL) {
 116     Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, Width, Port, 1, &Data);
 117   } else {
 118     Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);
 119   }
 120   ASSERT_EFI_ERROR (Status);
 121
 122   return Data;
 123 }
 124
 125 /**
 126   Reads memory-mapped registers in the EFI system memory space.
 127
 128   Reads the MMIO registers specified by Address with registers width specified by Width.
 129   The read value is returned. If such operations are not supported, then ASSERT().
 130   This function must guarantee that all MMIO read and write operations are serialized.
 131
 132   @param  Address       The MMIO register to read.
 133                         The caller is responsible for aligning the Address if required.
 134   @param  Width         The width of the I/O operation.
 135
 136   @return Data read from registers in the EFI system memory space.
 137
 138 **/
 139 UINT64
 140 EFIAPI
 141 MmioReadWorker (
 142   IN      UINTN                     Address,
 143   IN      EFI_CPU_IO_PROTOCOL_WIDTH Width
 144   )
 145 {
 146   EFI_STATUS                        Status;
 147   UINT64                            Data;
 148
 149   if (mPciRootBridgeIo != NULL) {
 150     Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, Width, Address, 1, &Data);
 151   } else {
 152     Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);
 153   }
 154   ASSERT_EFI_ERROR (Status);
 155
 156   return Data;
 157 }
 158
 159 /**
 160   Writes memory-mapped registers in the EFI system memory space.
 161
 162   Writes the MMIO registers specified by Address with registers width and value specified by Width
 163   and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
 164   This function must guarantee that all MMIO read and write operations are serialized.
 165
 166   @param  Address       The MMIO register to read.
 167                         The caller is responsible for aligning the Address if required.
 168   @param  Width         The width of the I/O operation.
 169
 170   @return Data read from registers in the EFI system memory space.
 171
 172 **/
 173 UINT64
 174 EFIAPI
 175 MmioWriteWorker (
 176   IN      UINTN                     Address,
 177   IN      EFI_CPU_IO_PROTOCOL_WIDTH Width,
 178   IN      UINT64                    Data
 179   )
 180 {
 181   EFI_STATUS                        Status;
 182
 183   if (mPciRootBridgeIo != NULL) {
 184     Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, Width, Address, 1, &Data);
 185   } else {
 186     Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);
 187   }
 188   ASSERT_EFI_ERROR (Status);
 189
 190   return Data;
 191 }
 192
 193 /**
 194   Reads an 8-bit I/O port.
 195
 196   Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
 197   This function must guarantee that all I/O read and write operations are
 198   serialized.
 199
 200   If 8-bit I/O port operations are not supported, then ASSERT().
 201
 202   @param  Port  The I/O port to read.
 203
 204   @return The value read.
 205
 206 **/
 207 UINT8
 208 EFIAPI
 209 IoRead8 (
 210   IN      UINTN                     Port
 211   )
 212 {
 213   return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);
 214 }
 215
 216 /**
 217   Writes an 8-bit I/O port.
 218
 219   Writes the 8-bit I/O port specified by Port with the value specified by Value
 220   and returns Value. This function must guarantee that all I/O read and write
 221   operations are serialized.
 222
 223   If 8-bit I/O port operations are not supported, then ASSERT().
 224
 225   @param  Port  The I/O port to write.
 226   @param  Value The value to write to the I/O port.
 227
 228   @return The value written the I/O port.
 229
 230 **/
 231 UINT8
 232 EFIAPI
 233 IoWrite8 (
 234   IN      UINTN                     Port,
 235   IN      UINT8                     Value
 236   )
 237 {
 238   return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);
 239 }
 240
 241 /**
 242   Reads a 16-bit I/O port.
 243
 244   Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
 245   This function must guarantee that all I/O read and write operations are
 246   serialized.
 247
 248   If 16-bit I/O port operations are not supported, then ASSERT().
 249
 250   @param  Port  The I/O port to read.
 251
 252   @return The value read.
 253
 254 **/
 255 UINT16
 256 EFIAPI
 257 IoRead16 (
 258   IN      UINTN                     Port
 259   )
 260 {
 261   //
 262   // Make sure Port is aligned on a 16-bit boundary.
 263   //
 264   ASSERT ((Port & 1) == 0);
 265   return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);
 266 }
 267
 268 /**
 269   Writes a 16-bit I/O port.
 270
 271   Writes the 16-bit I/O port specified by Port with the value specified by Value
 272   and returns Value. This function must guarantee that all I/O read and write
 273   operations are serialized.
 274
 275   If 16-bit I/O port operations are not supported, then ASSERT().
 276
 277   @param  Port  The I/O port to write.
 278   @param  Value The value to write to the I/O port.
 279
 280   @return The value written the I/O port.
 281
 282 **/
 283 UINT16
 284 EFIAPI
 285 IoWrite16 (
 286   IN      UINTN                     Port,
 287   IN      UINT16                    Value
 288   )
 289 {
 290   //
 291   // Make sure Port is aligned on a 16-bit boundary.
 292   //
 293   ASSERT ((Port & 1) == 0);
 294   return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);
 295 }
 296
 297 /**
 298   Reads a 32-bit I/O port.
 299
 300   Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
 301   This function must guarantee that all I/O read and write operations are
 302   serialized.
 303
 304   If 32-bit I/O port operations are not supported, then ASSERT().
 305
 306   @param  Port  The I/O port to read.
 307
 308   @return The value read.
 309
 310 **/
 311 UINT32
 312 EFIAPI
 313 IoRead32 (
 314   IN      UINTN                     Port
 315   )
 316 {
 317   //
 318   // Make sure Port is aligned on a 32-bit boundary.
 319   //
 320   ASSERT ((Port & 3) == 0);
 321   return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);
 322 }
 323
 324 /**
 325   Writes a 32-bit I/O port.
 326
 327   Writes the 32-bit I/O port specified by Port with the value specified by Value
 328   and returns Value. This function must guarantee that all I/O read and write
 329   operations are serialized.
 330
 331   If 32-bit I/O port operations are not supported, then ASSERT().
 332
 333   @param  Port  The I/O port to write.
 334   @param  Value The value to write to the I/O port.
 335
 336   @return The value written the I/O port.
 337
 338 **/
 339 UINT32
 340 EFIAPI
 341 IoWrite32 (
 342   IN      UINTN                     Port,
 343   IN      UINT32                    Value
 344   )
 345 {
 346   //
 347   // Make sure Port is aligned on a 32-bit boundary.
 348   //
 349   ASSERT ((Port & 3) == 0);
 350   return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);
 351 }
 352
 353 /**
 354   Reads a 64-bit I/O port.
 355
 356   Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
 357   This function must guarantee that all I/O read and write operations are
 358   serialized.
 359
 360   If 64-bit I/O port operations are not supported, then ASSERT().
 361
 362   @param  Port  The I/O port to read.
 363
 364   @return The value read.
 365
 366 **/
 367 UINT64
 368 EFIAPI
 369 IoRead64 (
 370   IN      UINTN                     Port
 371   )
 372 {
 373   //
 374   // Make sure Port is aligned on a 64-bit boundary.
 375   //
 376   ASSERT ((Port & 7) == 0);
 377   return IoReadWorker (Port, EfiCpuIoWidthUint64);
 378 }
 379
 380 /**
 381   Writes a 64-bit I/O port.
 382
 383   Writes the 64-bit I/O port specified by Port with the value specified by Value
 384   and returns Value. This function must guarantee that all I/O read and write
 385   operations are serialized.
 386
 387   If 64-bit I/O port operations are not supported, then ASSERT().
 388
 389   @param  Port  The I/O port to write.
 390   @param  Value The value to write to the I/O port.
 391
 392   @return The value written the I/O port.
 393
 394 **/
 395 UINT64
 396 EFIAPI
 397 IoWrite64 (
 398   IN      UINTN                     Port,
 399   IN      UINT64                    Value
 400   )
 401 {
 402   //
 403   // Make sure Port is aligned on a 64-bit boundary.
 404   //
 405   ASSERT ((Port & 7) == 0);
 406   return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);
 407 }
 408
 409 /**
 410   Reads an 8-bit MMIO register.
 411
 412   Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
 413   returned. This function must guarantee that all MMIO read and write
 414   operations are serialized.
 415
 416   If 8-bit MMIO register operations are not supported, then ASSERT().
 417
 418   @param  Address The MMIO register to read.
 419
 420   @return The value read.
 421
 422 **/
 423 UINT8
 424 EFIAPI
 425 MmioRead8 (
 426   IN      UINTN                     Address
 427   )
 428 {
 429   return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);
 430 }
 431
 432 /**
 433   Writes an 8-bit MMIO register.
 434
 435   Writes the 8-bit MMIO register specified by Address with the value specified
 436   by Value and returns Value. This function must guarantee that all MMIO read
 437   and write operations are serialized.
 438
 439   If 8-bit MMIO register operations are not supported, then ASSERT().
 440
 441   @param  Address The MMIO register to write.
 442   @param  Value   The value to write to the MMIO register.
 443
 444 **/
 445 UINT8
 446 EFIAPI
 447 MmioWrite8 (
 448   IN      UINTN                     Address,
 449   IN      UINT8                     Value
 450   )
 451 {
 452   return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);
 453 }
 454
 455 /**
 456   Reads a 16-bit MMIO register.
 457
 458   Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
 459   returned. This function must guarantee that all MMIO read and write
 460   operations are serialized.
 461
 462   If 16-bit MMIO register operations are not supported, then ASSERT().
 463
 464   @param  Address The MMIO register to read.
 465
 466   @return The value read.
 467
 468 **/
 469 UINT16
 470 EFIAPI
 471 MmioRead16 (
 472   IN      UINTN                     Address
 473   )
 474 {
 475   //
 476   // Make sure Address is aligned on a 16-bit boundary.
 477   //
 478   ASSERT ((Address & 1) == 0);
 479   return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);
 480 }
 481
 482 /**
 483   Writes a 16-bit MMIO register.
 484
 485   Writes the 16-bit MMIO register specified by Address with the value specified
 486   by Value and returns Value. This function must guarantee that all MMIO read
 487   and write operations are serialized.
 488
 489   If 16-bit MMIO register operations are not supported, then ASSERT().
 490
 491   @param  Address The MMIO register to write.
 492   @param  Value   The value to write to the MMIO register.
 493
 494 **/
 495 UINT16
 496 EFIAPI
 497 MmioWrite16 (
 498   IN      UINTN                     Address,
 499   IN      UINT16                    Value
 500   )
 501 {
 502   //
 503   // Make sure Address is aligned on a 16-bit boundary.
 504   //
 505   ASSERT ((Address & 1) == 0);
 506   return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);
 507 }
 508
 509 /**
 510   Reads a 32-bit MMIO register.
 511
 512   Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
 513   returned. This function must guarantee that all MMIO read and write
 514   operations are serialized.
 515
 516   If 32-bit MMIO register operations are not supported, then ASSERT().
 517
 518   @param  Address The MMIO register to read.
 519
 520   @return The value read.
 521
 522 **/
 523 UINT32
 524 EFIAPI
 525 MmioRead32 (
 526   IN      UINTN                     Address
 527   )
 528 {
 529   //
 530   // Make sure Address is aligned on a 32-bit boundary.
 531   //
 532   ASSERT ((Address & 3) == 0);
 533   return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);
 534 }
 535
 536 /**
 537   Writes a 32-bit MMIO register.
 538
 539   Writes the 32-bit MMIO register specified by Address with the value specified
 540   by Value and returns Value. This function must guarantee that all MMIO read
 541   and write operations are serialized.
 542
 543   If 32-bit MMIO register operations are not supported, then ASSERT().
 544
 545   @param  Address The MMIO register to write.
 546   @param  Value   The value to write to the MMIO register.
 547
 548 **/
 549 UINT32
 550 EFIAPI
 551 MmioWrite32 (
 552   IN      UINTN                     Address,
 553   IN      UINT32                    Value
 554   )
 555 {
 556   //
 557   // Make sure Address is aligned on a 32-bit boundary.
 558   //
 559   ASSERT ((Address & 3) == 0);
 560   return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);
 561 }
 562
 563 /**
 564   Reads a 64-bit MMIO register.
 565
 566   Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
 567   returned. This function must guarantee that all MMIO read and write
 568   operations are serialized.
 569
 570   If 64-bit MMIO register operations are not supported, then ASSERT().
 571
 572   @param  Address The MMIO register to read.
 573
 574   @return The value read.
 575
 576 **/
 577 UINT64
 578 EFIAPI
 579 MmioRead64 (
 580   IN      UINTN                     Address
 581   )
 582 {
 583   //
 584   // Make sure Address is aligned on a 64-bit boundary.
 585   //
 586   ASSERT ((Address & 7) == 0);
 587   return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);
 588 }
 589
 590 /**
 591   Writes a 64-bit MMIO register.
 592
 593   Writes the 64-bit MMIO register specified by Address with the value specified
 594   by Value and returns Value. This function must guarantee that all MMIO read
 595   and write operations are serialized.
 596
 597   If 64-bit MMIO register operations are not supported, then ASSERT().
 598
 599   @param  Address The MMIO register to write.
 600   @param  Value   The value to write to the MMIO register.
 601
 602 **/
 603 UINT64
 604 EFIAPI
 605 MmioWrite64 (
 606   IN      UINTN                     Address,
 607   IN      UINT64                    Value
 608   )
 609 {
 610   //
 611   // Make sure Address is aligned on a 64-bit boundary.
 612   //
 613   ASSERT ((Address & 7) == 0);
 614   return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);
 615 }