IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc

   1 ;------------------------------------------------------------------------------
   2 ;
   3 ; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   4 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   5 ;
   6 ; Abstract:
   7 ;
   8 ;   Provide macro for register save/restore using SSE registers
   9 ;
  10 ;------------------------------------------------------------------------------
  11
  12 ;
  13 ; Define SSE instruction set
  14 ;
  15 %ifdef USE_SSE41_FLAG
  16 ;
  17 ; Define SSE macros using SSE 4.1 instructions
  18 ; args 1:XMM, 2:IDX, 3:REG
  19 %macro SXMMN           3
  20              pinsrd  %1, %3, (%2 & 3)
  21              %endmacro
  22
  23 ;
  24 ;args 1:XMM, 2:REG, 3:IDX
  25 ;
  26 %macro LXMMN           3
  27              pextrd  %2, %1, (%3 & 3)
  28              %endmacro
  29 %else
  30 ;
  31 ; Define SSE macros using SSE 2 instructions
  32 ; args 1:XMM, 2:IDX, 3:REG
  33 %macro SXMMN       3
  34              pinsrw  %1, %3, (%2 & 3) * 2
  35              ror     %3, 16
  36              pinsrw  %1, %3, (%2 & 3) * 2 + 1
  37              rol     %3, 16
  38              %endmacro
  39
  40 ;
  41 ;args 1:XMM, 2:REG,  3:IDX
  42 ;
  43 %macro LXMMN    3
  44              pshufd  %1, %1,  ((0E4E4E4h >> (%3 * 2))  & 0FFh)
  45              movd    %2, %1
  46              pshufd  %1, %1,  ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)
  47              %endmacro
  48 %endif
  49
  50 ;
  51 ; XMM7 to save/restore EBP, EBX, ESI, EDI
  52 ;
  53 %macro SAVE_REGS   0
  54   SXMMN      xmm7, 0, ebp
  55   SXMMN      xmm7, 1, ebx
  56   SXMMN      xmm7, 2, esi
  57   SXMMN      xmm7, 3, edi
  58   SAVE_ESP
  59              %endmacro
  60
  61 %macro LOAD_REGS    0
  62   LXMMN      xmm7, ebp, 0
  63   LXMMN      xmm7, ebx, 1
  64   LXMMN      xmm7, esi, 2
  65   LXMMN      xmm7, edi, 3
  66   LOAD_ESP
  67              %endmacro
  68
  69 ;
  70 ; XMM6 to save/restore EAX, EDX, ECX, ESP
  71 ;
  72 %macro LOAD_EAX     0
  73   LXMMN      xmm6, eax, 1
  74              %endmacro
  75
  76 %macro SAVE_EAX     0
  77   SXMMN      xmm6, 1, eax
  78              %endmacro
  79
  80 %macro LOAD_EDX     0
  81   LXMMN      xmm6, edx, 2
  82              %endmacro
  83
  84 %macro SAVE_EDX     0
  85   SXMMN      xmm6, 2, edx
  86              %endmacro
  87
  88 %macro SAVE_ECX     0
  89   SXMMN      xmm6, 3, ecx
  90              %endmacro
  91
  92 %macro LOAD_ECX     0
  93   LXMMN      xmm6, ecx, 3
  94              %endmacro
  95
  96 %macro SAVE_ESP     0
  97   SXMMN      xmm6, 0, esp
  98              %endmacro
  99
 100 %macro LOAD_ESP     0
 101   movd       esp,  xmm6
 102              %endmacro
 103 ;
 104 ; XMM5 for calling stack
 105 ; arg 1:Entry
 106 %macro CALL_XMM       1
 107              mov     esi, %%ReturnAddress
 108              pslldq  xmm5, 4
 109 %ifdef USE_SSE41_FLAG
 110              pinsrd  xmm5, esi, 0
 111 %else
 112              pinsrw  xmm5, esi, 0
 113              ror     esi,  16
 114              pinsrw  xmm5, esi, 1
 115 %endif
 116              mov     esi,  %1
 117              jmp     esi
 118 %%ReturnAddress:
 119              %endmacro
 120
 121 %macro RET_XMM       0
 122              movd    esi, xmm5
 123              psrldq  xmm5, 4
 124              jmp     esi
 125              %endmacro
 126
 127 %macro ENABLE_SSE   0
 128             ;
 129             ; Initialize floating point units
 130             ;
 131             jmp     NextAddress
 132 align 4
 133             ;
 134             ; Float control word initial value:
 135             ; all exceptions masked, double-precision, round-to-nearest
 136             ;
 137 FpuControlWord       DW      027Fh
 138             ;
 139             ; Multimedia-extensions control word:
 140             ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
 141             ;
 142 MmxControlWord       DD      01F80h
 143 SseError:
 144             ;
 145             ; Processor has to support SSE
 146             ;
 147             jmp     SseError
 148 NextAddress:
 149             finit
 150             fldcw   [FpuControlWord]
 151
 152             ;
 153             ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 154             ; whether the processor supports SSE instruction.
 155             ;
 156             mov     eax, 1
 157             cpuid
 158             bt      edx, 25
 159             jnc     SseError
 160
 161 %ifdef USE_SSE41_FLAG
 162             ;
 163             ; SSE 4.1 support
 164             ;
 165             bt      ecx, 19
 166             jnc     SseError
 167 %endif
 168
 169             ;
 170             ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
 171             ;
 172             mov     eax, cr4
 173             or      eax, 00000600h
 174             mov     cr4, eax
 175
 176             ;
 177             ; The processor should support SSE instruction and we can use
 178             ; ldmxcsr instruction
 179             ;
 180             ldmxcsr [MmxControlWord]
 181             %endmacro