IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
   4 # SPDX-License-Identifier: BSD-2-Clause-Patent
   5 #
   6 # Abstract:
   7 #
   8 #------------------------------------------------------------------------------
   9
  10 #
  11 # Float control word initial value:
  12 # all exceptions masked, double-precision, round-to-nearest
  13 #
  14 ASM_PFX(mFpuControlWord): .word     0x027F
  15 #
  16 # Multimedia-extensions control word:
  17 # all exceptions masked, round-to-nearest, flush to zero for masked underflow
  18 #
  19 ASM_PFX(mMmxControlWord): .long     0x01F80
  20
  21
  22
  23 #
  24 # Initializes floating point units for requirement of UEFI specification.
  25 #
  26 # This function initializes floating-point control word to 0x027F (all exceptions
  27 # masked,double-precision, round-to-nearest) and multimedia-extensions control word
  28 # (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  29 # for masked underflow).
  30 #
  31 ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
  32 ASM_PFX(InitializeFloatingPointUnits):
  33
  34     pushl   %ebx
  35
  36     #
  37     # Initialize floating point units
  38     #
  39     finit
  40     fldcw   ASM_PFX(mFpuControlWord)
  41
  42     #
  43     # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  44     # whether the processor supports SSE instruction.
  45     #
  46     movl    $1,  %eax
  47     cpuid
  48     btl     $25, %edx
  49     jnc     Done
  50
  51     #
  52     # Set OSFXSR bit 9 in CR4
  53     #
  54     movl    %cr4, %eax
  55     orl     $BIT9, %eax
  56     movl    %eax, %cr4
  57
  58     #
  59     # The processor should support SSE instruction and we can use
  60     # ldmxcsr instruction
  61     #
  62     ldmxcsr ASM_PFX(mMmxControlWord)
  63
  64 Done:
  65     popl    %ebx
  66
  67     ret