IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc

   1 ;------------------------------------------------------------------------------
   2 ;
   3 ; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
   4 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   5 ;
   6 ; Abstract:
   7 ;
   8 ;   Provide macro for register save/restore using SSE registers
   9 ;
  10 ;------------------------------------------------------------------------------
  11
  12 ;
  13 ; Define SSE instruction set
  14 ;
  15 IFDEF USE_SSE41_FLAG
  16 ;
  17 ; Define SSE macros using SSE 4.1 instructions
  18 ;
  19 SXMMN        MACRO   XMM, IDX, REG
  20              pinsrd  XMM, REG, (IDX AND 3)
  21              ENDM
  22
  23 LXMMN        MACRO   XMM, REG, IDX
  24              pextrd  REG, XMM, (IDX AND 3)
  25              ENDM
  26 ELSE
  27 ;
  28 ; Define SSE macros using SSE 2 instructions
  29 ;
  30 SXMMN        MACRO   XMM, IDX, REG
  31              pinsrw  XMM, REG, (IDX AND 3) * 2
  32              ror     REG, 16
  33              pinsrw  XMM, REG, (IDX AND 3) * 2 + 1
  34              rol     REG, 16
  35              ENDM
  36
  37 LXMMN        MACRO   XMM, REG, IDX
  38              pshufd  XMM, XMM,  (0E4E4E4h SHR (IDX * 2))  AND 0FFh
  39              movd    REG, XMM
  40              pshufd  XMM, XMM,  (0E4E4E4h SHR (IDX * 2 + (IDX AND 1) * 4)) AND 0FFh
  41              ENDM
  42 ENDIF
  43
  44 ;
  45 ; XMM7 to save/restore EBP, EBX, ESI, EDI
  46 ;
  47 SAVE_REGS    MACRO
  48   SXMMN      xmm7, 0, ebp
  49   SXMMN      xmm7, 1, ebx
  50   SXMMN      xmm7, 2, esi
  51   SXMMN      xmm7, 3, edi
  52   SAVE_ESP
  53              ENDM
  54
  55 LOAD_REGS    MACRO
  56   LXMMN      xmm7, ebp, 0
  57   LXMMN      xmm7, ebx, 1
  58   LXMMN      xmm7, esi, 2
  59   LXMMN      xmm7, edi, 3
  60   LOAD_ESP
  61              ENDM
  62
  63 ;
  64 ; XMM6 to save/restore EAX, EDX, ECX, ESP
  65 ;
  66 LOAD_EAX     MACRO
  67   LXMMN      xmm6, eax, 1
  68              ENDM
  69
  70 SAVE_EAX     MACRO
  71   SXMMN      xmm6, 1, eax
  72              ENDM
  73
  74 LOAD_EDX     MACRO
  75   LXMMN      xmm6, edx, 2
  76              ENDM
  77
  78 SAVE_EDX     MACRO
  79   SXMMN      xmm6, 2, edx
  80              ENDM
  81
  82 SAVE_ECX     MACRO
  83   SXMMN      xmm6, 3, ecx
  84              ENDM
  85
  86 LOAD_ECX     MACRO
  87   LXMMN      xmm6, ecx, 3
  88              ENDM
  89
  90 SAVE_ESP     MACRO
  91   SXMMN      xmm6, 0, esp
  92              ENDM
  93
  94 LOAD_ESP     MACRO
  95   movd       esp,  xmm6
  96              ENDM
  97
  98 ;
  99 ; XMM5 for calling stack
 100 ;
 101 CALL_XMM     MACRO  Entry
 102              local   ReturnAddress
 103              mov     esi, offset ReturnAddress
 104              pslldq  xmm5, 4
 105 IFDEF USE_SSE41_FLAG
 106              pinsrd  xmm5, esi, 0
 107 ELSE
 108              pinsrw  xmm5, esi, 0
 109              ror     esi,  16
 110              pinsrw  xmm5, esi, 1
 111 ENDIF
 112              mov     esi,  Entry
 113              jmp     esi
 114 ReturnAddress:
 115              ENDM
 116
 117 RET_XMM      MACRO
 118              movd    esi, xmm5
 119              psrldq  xmm5, 4
 120              jmp     esi
 121              ENDM
 122
 123 ENABLE_SSE   MACRO
 124             ;
 125             ; Initialize floating point units
 126             ;
 127             local   NextAddress
 128             jmp     NextAddress
 129 ALIGN 4
 130             ;
 131             ; Float control word initial value:
 132             ; all exceptions masked, double-precision, round-to-nearest
 133             ;
 134 FpuControlWord       DW      027Fh
 135             ;
 136             ; Multimedia-extensions control word:
 137             ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
 138             ;
 139 MmxControlWord       DD      01F80h
 140 SseError:
 141             ;
 142             ; Processor has to support SSE
 143             ;
 144             jmp     SseError
 145 NextAddress:
 146             finit
 147             fldcw   FpuControlWord
 148
 149             ;
 150             ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 151             ; whether the processor supports SSE instruction.
 152             ;
 153             mov     eax, 1
 154             cpuid
 155             bt      edx, 25
 156             jnc     SseError
 157
 158 IFDEF USE_SSE41_FLAG
 159             ;
 160             ; SSE 4.1 support
 161             ;
 162             bt      ecx, 19
 163             jnc     SseError
 164 ENDIF
 165
 166             ;
 167             ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
 168             ;
 169             mov     eax, cr4
 170             or      eax, 00000600h
 171             mov     cr4, eax
 172
 173             ;
 174             ; The processor should support SSE instruction and we can use
 175             ; ldmxcsr instruction
 176             ;
 177             ldmxcsr MmxControlWord
 178             ENDM