1 ;------------------------------------------------------------------------------
3 ; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
4 ; SPDX-License-Identifier: BSD-2-Clause-Patent
8 ; Provide macro for register save/restore using SSE registers
10 ;------------------------------------------------------------------------------
13 ; Define SSE instruction set
17 ; Define SSE macros using SSE 4.1 instructions
19 SXMMN MACRO XMM, IDX, REG
20 pinsrd XMM, REG, (IDX AND 3)
23 LXMMN MACRO XMM, REG, IDX
24 pextrd REG, XMM, (IDX AND 3)
28 ; Define SSE macros using SSE 2 instructions
30 SXMMN MACRO XMM, IDX, REG
31 pinsrw XMM, REG, (IDX AND 3) * 2
33 pinsrw XMM, REG, (IDX AND 3) * 2 + 1
37 LXMMN MACRO XMM, REG, IDX
38 pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2)) AND 0FFh
40 pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2 + (IDX AND 1) * 4)) AND 0FFh
45 ; XMM7 to save/restore EBP, EBX, ESI, EDI
64 ; XMM6 to save/restore EAX, EDX, ECX, ESP
99 ; XMM5 for calling stack
103 mov esi, offset ReturnAddress
125 ; Initialize floating point units
131 ; Float control word initial value:
132 ; all exceptions masked, double-precision, round-to-nearest
134 FpuControlWord DW 027Fh
136 ; Multimedia-extensions control word:
137 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
139 MmxControlWord DD 01F80h
142 ; Processor has to support SSE
150 ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
151 ; whether the processor supports SSE instruction.
167 ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
174 ; The processor should support SSE instruction and we can use
175 ; ldmxcsr instruction
177 ldmxcsr MmxControlWord