IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc

   1 ;------------------------------------------------------------------------------
   2 ;
   3 ; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
   4 ; This program and the accompanying materials
   5 ; are licensed and made available under the terms and conditions of the BSD License
   6 ; which accompanies this distribution.  The full text of the license may be found at
   7 ; http://opensource.org/licenses/bsd-license.php.
   8 ;
   9 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 ;
  12 ; Abstract:
  13 ;
  14 ;   Provide macro for register save/restore using SSE registers
  15 ;
  16 ;------------------------------------------------------------------------------
  17
  18 ;
  19 ; Define SSE instruction set
  20 ;
  21 IFDEF USE_SSE41_FLAG
  22 ;
  23 ; Define SSE macros using SSE 4.1 instructions
  24 ;
  25 SXMMN        MACRO   XMM, IDX, REG
  26              pinsrd  XMM, REG, (IDX AND 3)
  27              ENDM
  28
  29 LXMMN        MACRO   XMM, REG, IDX
  30              pextrd  REG, XMM, (IDX AND 3)
  31              ENDM
  32 ELSE
  33 ;
  34 ; Define SSE macros using SSE 2 instructions
  35 ;
  36 SXMMN        MACRO   XMM, IDX, REG
  37              pinsrw  XMM, REG, (IDX AND 3) * 2
  38              ror     REG, 16
  39              pinsrw  XMM, REG, (IDX AND 3) * 2 + 1
  40              rol     REG, 16
  41              ENDM
  42
  43 LXMMN        MACRO   XMM, REG, IDX
  44              pshufd  XMM, XMM,  (0E4E4E4h SHR (IDX * 2))  AND 0FFh
  45              movd    REG, XMM
  46              pshufd  XMM, XMM,  (0E4E4E4h SHR (IDX * 2 + (IDX AND 1) * 4)) AND 0FFh
  47              ENDM
  48 ENDIF
  49
  50 ;
  51 ; XMM7 to save/restore EBP, EBX, ESI, EDI
  52 ;
  53 SAVE_REGS    MACRO
  54   SXMMN      xmm7, 0, ebp
  55   SXMMN      xmm7, 1, ebx
  56   SXMMN      xmm7, 2, esi
  57   SXMMN      xmm7, 3, edi
  58   SAVE_ESP
  59              ENDM
  60
  61 LOAD_REGS    MACRO
  62   LXMMN      xmm7, ebp, 0
  63   LXMMN      xmm7, ebx, 1
  64   LXMMN      xmm7, esi, 2
  65   LXMMN      xmm7, edi, 3
  66   LOAD_ESP
  67              ENDM
  68
  69 ;
  70 ; XMM6 to save/restore EAX, EDX, ECX, ESP
  71 ;
  72 LOAD_EAX     MACRO
  73   LXMMN      xmm6, eax, 1
  74              ENDM
  75
  76 SAVE_EAX     MACRO
  77   SXMMN      xmm6, 1, eax
  78              ENDM
  79
  80 LOAD_EDX     MACRO
  81   LXMMN      xmm6, edx, 2
  82              ENDM
  83
  84 SAVE_EDX     MACRO
  85   SXMMN      xmm6, 2, edx
  86              ENDM
  87
  88 SAVE_ECX     MACRO
  89   SXMMN      xmm6, 3, ecx
  90              ENDM
  91
  92 LOAD_ECX     MACRO
  93   LXMMN      xmm6, ecx, 3
  94              ENDM
  95
  96 SAVE_ESP     MACRO
  97   SXMMN      xmm6, 0, esp
  98              ENDM
  99
 100 LOAD_ESP     MACRO
 101   movd       esp,  xmm6
 102              ENDM
 103
 104 ;
 105 ; XMM5 for calling stack
 106 ;
 107 CALL_XMM     MACRO  Entry
 108              local   ReturnAddress
 109              mov     esi, offset ReturnAddress
 110              pslldq  xmm5, 4
 111 IFDEF USE_SSE41_FLAG
 112              pinsrd  xmm5, esi, 0
 113 ELSE
 114              pinsrw  xmm5, esi, 0
 115              ror     esi,  16
 116              pinsrw  xmm5, esi, 1
 117 ENDIF
 118              mov     esi,  Entry
 119              jmp     esi
 120 ReturnAddress:
 121              ENDM
 122
 123 RET_XMM      MACRO
 124              movd    esi, xmm5
 125              psrldq  xmm5, 4
 126              jmp     esi
 127              ENDM
 128
 129 ENABLE_SSE   MACRO
 130             ;
 131             ; Initialize floating point units
 132             ;
 133             local   NextAddress
 134             jmp     NextAddress
 135 ALIGN 4
 136             ;
 137             ; Float control word initial value:
 138             ; all exceptions masked, double-precision, round-to-nearest
 139             ;
 140 FpuControlWord       DW      027Fh
 141             ;
 142             ; Multimedia-extensions control word:
 143             ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
 144             ;
 145 MmxControlWord       DD      01F80h
 146 SseError:
 147             ;
 148             ; Processor has to support SSE
 149             ;
 150             jmp     SseError
 151 NextAddress:
 152             finit
 153             fldcw   FpuControlWord
 154
 155             ;
 156             ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 157             ; whether the processor supports SSE instruction.
 158             ;
 159             mov     eax, 1
 160             cpuid
 161             bt      edx, 25
 162             jnc     SseError
 163
 164 IFDEF USE_SSE41_FLAG
 165             ;
 166             ; SSE 4.1 support
 167             ;
 168             bt      ecx, 19
 169             jnc     SseError
 170 ENDIF
 171
 172             ;
 173             ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
 174             ;
 175             mov     eax, cr4
 176             or      eax, 00000600h
 177             mov     cr4, eax
 178
 179             ;
 180             ; The processor should support SSE instruction and we can use
 181             ; ldmxcsr instruction
 182             ;
 183             ldmxcsr MmxControlWord
 184             ENDM