3033659ea01e5c07f936ed229c36dd10abe046f8
[mirror_edk2.git] / IntelFspPkg / Include / FspInfoHeader.h
1 /** @file
2 Intel FSP Info Header definition from Intel Firmware Support Package External
3 Architecture Specification, April 2014, revision 001.
4
5 Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _FSP_INFO_HEADER_H_
17 #define _FSP_INFO_HEADER_H_
18
19 #define FSP_HEADER_REVISION_1 1
20 #define FSP_HEADER_REVISION_2 2
21
22 #define FSPE_HEADER_REVISION_1 1
23 #define FSPP_HEADER_REVISION_1 1
24
25 ///
26 /// Fixed FSP header offset in the FSP image
27 ///
28 #define FSP_INFO_HEADER_OFF 0x94
29
30 #define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
31
32 #pragma pack(1)
33
34 typedef struct {
35 ///
36 /// Byte 0x00: Signature ('FSPH') for the FSP Information Header
37 ///
38 UINT32 Signature;
39 ///
40 /// Byte 0x04: Length of the FSP Information Header
41 ///
42 UINT32 HeaderLength;
43 ///
44 /// Byte 0x08: Reserved
45 ///
46 UINT8 Reserved1[3];
47 ///
48 /// Byte 0x0B: Revision of the FSP Information Header
49 ///
50 UINT8 HeaderRevision;
51 ///
52 /// Byte 0x0C: Revision of the FSP binary
53 ///
54 UINT32 ImageRevision;
55
56
57 ///
58 /// Byte 0x10: Signature string that will help match the FSP Binary to a supported
59 /// hardware configuration.
60 ///
61 CHAR8 ImageId[8];
62 ///
63 /// Byte 0x18: Size of the entire FSP binary
64 ///
65 UINT32 ImageSize;
66 ///
67 /// Byte 0x18: FSP binary preferred base address
68 ///
69 UINT32 ImageBase;
70
71
72 ///
73 /// Byte 0x20: Attribute for the FSP binary
74 ///
75 UINT32 ImageAttribute;
76 ///
77 /// Byte 0x24: Offset of the FSP configuration region
78 ///
79 UINT32 CfgRegionOffset;
80 ///
81 /// Byte 0x24: Size of the FSP configuration region
82 ///
83 UINT32 CfgRegionSize;
84 ///
85 /// Byte 0x2C: Number of API entries this FSP supports
86 ///
87 UINT32 ApiEntryNum;
88
89
90 ///
91 /// Byte 0x30: The offset for the API to setup a temporary stack till the memory
92 /// is initialized.
93 ///
94 UINT32 TempRamInitEntryOffset;
95 ///
96 /// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)
97 ///
98 UINT32 FspInitEntryOffset;
99 ///
100 /// Byte 0x38: The offset for the API to inform the FSP about the different stages
101 /// in the boot process
102 ///
103 UINT32 NotifyPhaseEntryOffset;
104
105 ///
106 /// Below field is added in FSP 1.1
107 ///
108
109 ///
110 /// Byte 0x3C: The offset for the API to initialize the memory
111 ///
112 UINT32 FspMemoryInitEntryOffset;
113 ///
114 /// Byte 0x40: The offset for the API to tear down temporary RAM
115 ///
116 UINT32 TempRamExitEntryOffset;
117 ///
118 /// Byte 0x44: The offset for the API to initialize the CPU and chipset
119 ///
120 UINT32 FspSiliconInitEntryOffset;
121
122 } FSP_INFO_HEADER;
123
124 ///
125 /// Below structure is added in FSP 1.1
126 ///
127 typedef struct {
128 ///
129 /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header
130 ///
131 UINT32 Signature;
132 ///
133 /// Byte 0x04: Length of the FSP Extended Header
134 ///
135 UINT32 HeaderLength;
136 ///
137 /// Byte 0x08: Revision of the FSP Extended Header
138 ///
139 UINT8 Revision;
140 ///
141 /// Byte 0x09: Reserved for future use.
142 ///
143 UINT8 Reserved;
144 ///
145 /// Byte 0x0A: An OEM-supplied string that defines the OEM
146 ///
147 CHAR8 OemId[6];
148 ///
149 /// Byte 0x10: An OEM-supplied revision number. Larger numbers are assumed to be newer revisions.
150 ///
151 UINT32 OemRevision;
152
153 } FSP_EXTENTED_HEADER;
154
155 #pragma pack()
156
157 #endif