2 Intel FSP Info Header definition from Intel Firmware Support Package External
3 Architecture Specification, April 2014, revision 001.
5 Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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16 #ifndef _FSP_INFO_HEADER_H_
17 #define _FSP_INFO_HEADER_H_
19 #define FSP_HEADER_REVISION_1 1
20 #define FSP_HEADER_REVISION_2 2
22 #define FSPE_HEADER_REVISION_1 1
23 #define FSPP_HEADER_REVISION_1 1
26 /// Fixed FSP header offset in the FSP image
28 #define FSP_INFO_HEADER_OFF 0x94
30 #define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
36 /// Byte 0x00: Signature ('FSPH') for the FSP Information Header
40 /// Byte 0x04: Length of the FSP Information Header
44 /// Byte 0x08: Reserved
48 /// Byte 0x0B: Revision of the FSP Information Header
52 /// Byte 0x0C: Revision of the FSP binary
58 /// Byte 0x10: Signature string that will help match the FSP Binary to a supported
59 /// hardware configuration.
63 /// Byte 0x18: Size of the entire FSP binary
67 /// Byte 0x1C: FSP binary preferred base address
73 /// Byte 0x20: Attribute for the FSP binary
75 UINT32 ImageAttribute
;
77 /// Byte 0x24: Offset of the FSP configuration region
79 UINT32 CfgRegionOffset
;
81 /// Byte 0x28: Size of the FSP configuration region
85 /// Byte 0x2C: Number of API entries this FSP supports
91 /// Byte 0x30: The offset for the API to setup a temporary stack till the memory
94 UINT32 TempRamInitEntryOffset
;
96 /// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)
98 UINT32 FspInitEntryOffset
;
100 /// Byte 0x38: The offset for the API to inform the FSP about the different stages
101 /// in the boot process
103 UINT32 NotifyPhaseEntryOffset
;
106 /// Below fields are added in FSP Revision 2
110 /// Byte 0x3C: The offset for the API to initialize the memory
112 UINT32 FspMemoryInitEntryOffset
;
114 /// Byte 0x40: The offset for the API to tear down temporary RAM
116 UINT32 TempRamExitEntryOffset
;
118 /// Byte 0x44: The offset for the API to initialize the CPU and chipset
120 UINT32 FspSiliconInitEntryOffset
;
125 /// Below structure is added in FSP version 2
129 /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header
133 /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
137 /// Byte 0x08: FSP producer defined revision of the table.
141 /// Byte 0x09: Reserved for future use.
145 /// Byte 0x0A: FSP producer identification string
147 CHAR8 FspProducerId
[6];
149 /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
151 UINT32 FspProducerRevision
;
153 /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
155 UINT32 FspProducerDataSize
;
157 /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
160 } FSP_INFO_EXTENDED_HEADER
;