IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c

   1 /** @file
   2
   3   Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
   4   This program and the accompanying materials
   5   are licensed and made available under the terms and conditions of the BSD License
   6   which accompanies this distribution.  The full text of the license may be found at
   7   http://opensource.org/licenses/bsd-license.php.
   8
   9   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 **/
  13
  14 #include "DmaProtection.h"
  15
  16 /**
  17   Create extended context entry.
  18
  19   @param[in]  VtdIndex  The index of the VTd engine.
  20
  21   @retval EFI_SUCCESS          The extended context entry is created.
  22   @retval EFI_OUT_OF_RESOURCE  No enough resource to create extended context entry.
  23 **/
  24 EFI_STATUS
  25 CreateExtContextEntry (
  26   IN UINTN  VtdIndex
  27   );
  28
  29 /**
  30   Allocate zero pages.
  31
  32   @param[in]  Pages the number of pages.
  33
  34   @return the page address.
  35   @retval NULL No resource to allocate pages.
  36 **/
  37 VOID *
  38 EFIAPI
  39 AllocateZeroPages (
  40   IN UINTN  Pages
  41   )
  42 {
  43   VOID *Addr;
  44
  45   Addr = AllocatePages (Pages);
  46   if (Addr == NULL) {
  47     return NULL;
  48   }
  49   ZeroMem (Addr, EFI_PAGES_TO_SIZE(Pages));
  50   return Addr;
  51 }
  52
  53 /**
  54   Set second level paging entry attribute based upon IoMmuAccess.
  55
  56   @param[in]  PtEntry      The paging entry.
  57   @param[in]  IoMmuAccess  The IOMMU access.
  58 **/
  59 VOID
  60 SetSecondLevelPagingEntryAttribute (
  61   IN VTD_SECOND_LEVEL_PAGING_ENTRY  *PtEntry,
  62   IN UINT64                         IoMmuAccess
  63   )
  64 {
  65   PtEntry->Bits.Read  = ((IoMmuAccess & EDKII_IOMMU_ACCESS_READ) != 0);
  66   PtEntry->Bits.Write = ((IoMmuAccess & EDKII_IOMMU_ACCESS_WRITE) != 0);
  67 }
  68
  69 /**
  70   Create context entry.
  71
  72   @param[in]  VtdIndex  The index of the VTd engine.
  73
  74   @retval EFI_SUCCESS          The context entry is created.
  75   @retval EFI_OUT_OF_RESOURCE  No enough resource to create context entry.
  76 **/
  77 EFI_STATUS
  78 CreateContextEntry (
  79   IN UINTN  VtdIndex
  80   )
  81 {
  82   UINTN                  Index;
  83   VOID                   *Buffer;
  84   UINTN                  RootPages;
  85   UINTN                  ContextPages;
  86   VTD_ROOT_ENTRY         *RootEntry;
  87   VTD_CONTEXT_ENTRY      *ContextEntryTable;
  88   VTD_CONTEXT_ENTRY      *ContextEntry;
  89   VTD_SOURCE_ID          *PciSourceId;
  90   VTD_SOURCE_ID          SourceId;
  91   UINTN                  MaxBusNumber;
  92   UINTN                  EntryTablePages;
  93
  94   MaxBusNumber = 0;
  95   for (Index = 0; Index < mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceDataNumber; Index++) {
  96     PciSourceId = &mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceData[Index].PciSourceId;
  97     if (PciSourceId->Bits.Bus > MaxBusNumber) {
  98       MaxBusNumber = PciSourceId->Bits.Bus;
  99     }
 100   }
 101   DEBUG ((DEBUG_INFO,"  MaxBusNumber - 0x%x\n", MaxBusNumber));
 102
 103   RootPages = EFI_SIZE_TO_PAGES (sizeof (VTD_ROOT_ENTRY) * VTD_ROOT_ENTRY_NUMBER);
 104   ContextPages = EFI_SIZE_TO_PAGES (sizeof (VTD_CONTEXT_ENTRY) * VTD_CONTEXT_ENTRY_NUMBER);
 105   EntryTablePages = RootPages + ContextPages * (MaxBusNumber + 1);
 106   Buffer = AllocateZeroPages (EntryTablePages);
 107   if (Buffer == NULL) {
 108     DEBUG ((DEBUG_INFO,"Could not Alloc Root Entry Table.. \n"));
 109     return EFI_OUT_OF_RESOURCES;
 110   }
 111   mVtdUnitInformation[VtdIndex].RootEntryTable = (VTD_ROOT_ENTRY *)Buffer;
 112   Buffer = (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (RootPages);
 113
 114   for (Index = 0; Index < mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceDataNumber; Index++) {
 115     PciSourceId = &mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceData[Index].PciSourceId;
 116
 117     SourceId.Bits.Bus = PciSourceId->Bits.Bus;
 118     SourceId.Bits.Device = PciSourceId->Bits.Device;
 119     SourceId.Bits.Function = PciSourceId->Bits.Function;
 120
 121     RootEntry = &mVtdUnitInformation[VtdIndex].RootEntryTable[SourceId.Index.RootIndex];
 122     if (RootEntry->Bits.Present == 0) {
 123       RootEntry->Bits.ContextTablePointerLo  = (UINT32) RShiftU64 ((UINT64)(UINTN)Buffer, 12);
 124       RootEntry->Bits.ContextTablePointerHi  = (UINT32) RShiftU64 ((UINT64)(UINTN)Buffer, 32);
 125       RootEntry->Bits.Present = 1;
 126       Buffer = (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages);
 127     }
 128
 129     ContextEntryTable = (VTD_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(RootEntry->Bits.ContextTablePointerLo, RootEntry->Bits.ContextTablePointerHi) ;
 130     ContextEntry = &ContextEntryTable[SourceId.Index.ContextIndex];
 131     ContextEntry->Bits.TranslationType = 0;
 132     ContextEntry->Bits.FaultProcessingDisable = 0;
 133     ContextEntry->Bits.Present = 0;
 134
 135     DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
 136
 137     switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
 138     case BIT1:
 139       ContextEntry->Bits.AddressWidth = 0x1;
 140       break;
 141     case BIT2:
 142       ContextEntry->Bits.AddressWidth = 0x2;
 143       break;
 144     }
 145   }
 146
 147   FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
 148
 149   return EFI_SUCCESS;
 150 }
 151
 152 /**
 153   Create second level paging entry table.
 154
 155   @param[in]  VtdIndex                    The index of the VTd engine.
 156   @param[in]  SecondLevelPagingEntry      The second level paging entry.
 157   @param[in]  MemoryBase                  The base of the memory.
 158   @param[in]  MemoryLimit                 The limit of the memory.
 159   @param[in]  IoMmuAccess                 The IOMMU access.
 160
 161   @return The second level paging entry.
 162 **/
 163 VTD_SECOND_LEVEL_PAGING_ENTRY *
 164 CreateSecondLevelPagingEntryTable (
 165   IN UINTN                         VtdIndex,
 166   IN VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry,
 167   IN UINT64                        MemoryBase,
 168   IN UINT64                        MemoryLimit,
 169   IN UINT64                        IoMmuAccess
 170   )
 171 {
 172   UINTN                          Index4;
 173   UINTN                          Index3;
 174   UINTN                          Index2;
 175   UINTN                          Lvl4Start;
 176   UINTN                          Lvl4End;
 177   UINTN                          Lvl3Start;
 178   UINTN                          Lvl3End;
 179   VTD_SECOND_LEVEL_PAGING_ENTRY  *Lvl4PtEntry;
 180   VTD_SECOND_LEVEL_PAGING_ENTRY  *Lvl3PtEntry;
 181   VTD_SECOND_LEVEL_PAGING_ENTRY  *Lvl2PtEntry;
 182   UINT64                         BaseAddress;
 183   UINT64                         EndAddress;
 184
 185   if (MemoryLimit == 0) {
 186     return EFI_SUCCESS;
 187   }
 188
 189   BaseAddress = ALIGN_VALUE_LOW(MemoryBase, SIZE_2MB);
 190   EndAddress = ALIGN_VALUE_UP(MemoryLimit, SIZE_2MB);
 191   DEBUG ((DEBUG_INFO,"CreateSecondLevelPagingEntryTable: BaseAddress - 0x%016lx, EndAddress - 0x%016lx\n", BaseAddress, EndAddress));
 192
 193   if (SecondLevelPagingEntry == NULL) {
 194     SecondLevelPagingEntry = AllocateZeroPages (1);
 195     if (SecondLevelPagingEntry == NULL) {
 196       DEBUG ((DEBUG_ERROR,"Could not Alloc LVL4 PT. \n"));
 197       return NULL;
 198     }
 199     FlushPageTableMemory (VtdIndex, (UINTN)SecondLevelPagingEntry, EFI_PAGES_TO_SIZE(1));
 200   }
 201
 202   //
 203   // If no access is needed, just create not present entry.
 204   //
 205   if (IoMmuAccess == 0) {
 206     return SecondLevelPagingEntry;
 207   }
 208
 209   Lvl4Start = RShiftU64 (BaseAddress, 39) & 0x1FF;
 210   Lvl4End = RShiftU64 (EndAddress - 1, 39) & 0x1FF;
 211
 212   DEBUG ((DEBUG_INFO,"  Lvl4Start - 0x%x, Lvl4End - 0x%x\n", Lvl4Start, Lvl4End));
 213
 214   Lvl4PtEntry = (VTD_SECOND_LEVEL_PAGING_ENTRY *)SecondLevelPagingEntry;
 215   for (Index4 = Lvl4Start; Index4 <= Lvl4End; Index4++) {
 216     if (Lvl4PtEntry[Index4].Uint64 == 0) {
 217       Lvl4PtEntry[Index4].Uint64 = (UINT64)(UINTN)AllocateZeroPages (1);
 218       if (Lvl4PtEntry[Index4].Uint64 == 0) {
 219         DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL4 PAGE FAIL (0x%x)!!!!!!\n", Index4));
 220         ASSERT(FALSE);
 221         return NULL;
 222       }
 223       FlushPageTableMemory (VtdIndex, (UINTN)Lvl4PtEntry[Index4].Uint64, SIZE_4KB);
 224       SetSecondLevelPagingEntryAttribute (&Lvl4PtEntry[Index4], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
 225     }
 226
 227     Lvl3Start = RShiftU64 (BaseAddress, 30) & 0x1FF;
 228     if (ALIGN_VALUE_LOW(BaseAddress + SIZE_1GB, SIZE_1GB) <= EndAddress) {
 229       Lvl3End = SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY);
 230     } else {
 231       Lvl3End = RShiftU64 (EndAddress - 1, 30) & 0x1FF;
 232     }
 233     DEBUG ((DEBUG_INFO,"  Lvl4(0x%x): Lvl3Start - 0x%x, Lvl3End - 0x%x\n", Index4, Lvl3Start, Lvl3End));
 234
 235     Lvl3PtEntry = (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(Lvl4PtEntry[Index4].Bits.AddressLo, Lvl4PtEntry[Index4].Bits.AddressHi);
 236     for (Index3 = Lvl3Start; Index3 <= Lvl3End; Index3++) {
 237       if (Lvl3PtEntry[Index3].Uint64 == 0) {
 238         Lvl3PtEntry[Index3].Uint64 = (UINT64)(UINTN)AllocateZeroPages (1);
 239         if (Lvl3PtEntry[Index3].Uint64 == 0) {
 240           DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL3 PAGE FAIL (0x%x, 0x%x)!!!!!!\n", Index4, Index3));
 241           ASSERT(FALSE);
 242           return NULL;
 243         }
 244         FlushPageTableMemory (VtdIndex, (UINTN)Lvl3PtEntry[Index3].Uint64, SIZE_4KB);
 245         SetSecondLevelPagingEntryAttribute (&Lvl3PtEntry[Index3], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
 246       }
 247
 248       Lvl2PtEntry = (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(Lvl3PtEntry[Index3].Bits.AddressLo, Lvl3PtEntry[Index3].Bits.AddressHi);
 249       for (Index2 = 0; Index2 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); Index2++) {
 250         Lvl2PtEntry[Index2].Uint64 = BaseAddress;
 251         SetSecondLevelPagingEntryAttribute (&Lvl2PtEntry[Index2], IoMmuAccess);
 252         Lvl2PtEntry[Index2].Bits.PageSize = 1;
 253         BaseAddress += SIZE_2MB;
 254         if (BaseAddress >= MemoryLimit) {
 255           goto Done;
 256         }
 257       }
 258       FlushPageTableMemory (VtdIndex, (UINTN)Lvl2PtEntry, SIZE_4KB);
 259     }
 260     FlushPageTableMemory (VtdIndex, (UINTN)&Lvl3PtEntry[Lvl3Start], (UINTN)&Lvl3PtEntry[Lvl3End + 1] - (UINTN)&Lvl3PtEntry[Lvl3Start]);
 261   }
 262   FlushPageTableMemory (VtdIndex, (UINTN)&Lvl4PtEntry[Lvl4Start], (UINTN)&Lvl4PtEntry[Lvl4End + 1] - (UINTN)&Lvl4PtEntry[Lvl4Start]);
 263
 264 Done:
 265   return SecondLevelPagingEntry;
 266 }
 267
 268 /**
 269   Create second level paging entry.
 270
 271   @param[in]  VtdIndex                    The index of the VTd engine.
 272   @param[in]  IoMmuAccess                 The IOMMU access.
 273
 274   @return The second level paging entry.
 275 **/
 276 VTD_SECOND_LEVEL_PAGING_ENTRY *
 277 CreateSecondLevelPagingEntry (
 278   IN UINTN   VtdIndex,
 279   IN UINT64  IoMmuAccess
 280   )
 281 {
 282   VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry;
 283
 284   SecondLevelPagingEntry = NULL;
 285   SecondLevelPagingEntry = CreateSecondLevelPagingEntryTable (VtdIndex, SecondLevelPagingEntry, 0, mBelow4GMemoryLimit, IoMmuAccess);
 286   if (SecondLevelPagingEntry == NULL) {
 287     return NULL;
 288   }
 289
 290   if (mAbove4GMemoryLimit != 0) {
 291     ASSERT (mAbove4GMemoryLimit > BASE_4GB);
 292     SecondLevelPagingEntry = CreateSecondLevelPagingEntryTable (VtdIndex, SecondLevelPagingEntry, SIZE_4GB, mAbove4GMemoryLimit, IoMmuAccess);
 293     if (SecondLevelPagingEntry == NULL) {
 294       return NULL;
 295     }
 296   }
 297
 298   return SecondLevelPagingEntry;
 299 }
 300
 301 /**
 302   Setup VTd translation table.
 303
 304   @retval EFI_SUCCESS           Setup translation table successfully.
 305   @retval EFI_OUT_OF_RESOURCE   Setup translation table fail.
 306 **/
 307 EFI_STATUS
 308 SetupTranslationTable (
 309   VOID
 310   )
 311 {
 312   EFI_STATUS      Status;
 313   UINTN           Index;
 314
 315   for (Index = 0; Index < mVtdUnitNumber; Index++) {
 316     DEBUG((DEBUG_INFO, "CreateContextEntry - %d\n", Index));
 317     if (mVtdUnitInformation[Index].ECapReg.Bits.ECS) {
 318       Status = CreateExtContextEntry (Index);
 319     } else {
 320       Status = CreateContextEntry (Index);
 321     }
 322     if (EFI_ERROR (Status)) {
 323       return Status;
 324     }
 325   }
 326
 327   return EFI_SUCCESS;
 328 }
 329
 330 /**
 331   Dump DMAR context entry table.
 332
 333   @param[in]  RootEntry DMAR root entry.
 334 **/
 335 VOID
 336 DumpDmarContextEntryTable (
 337   IN VTD_ROOT_ENTRY *RootEntry
 338   )
 339 {
 340   UINTN                 Index;
 341   UINTN                 Index2;
 342   VTD_CONTEXT_ENTRY     *ContextEntry;
 343
 344   DEBUG ((DEBUG_INFO,"=========================\n"));
 345   DEBUG ((DEBUG_INFO,"DMAR Context Entry Table:\n"));
 346
 347   DEBUG ((DEBUG_INFO,"RootEntry Address - 0x%x\n", RootEntry));
 348
 349   for (Index = 0; Index < VTD_ROOT_ENTRY_NUMBER; Index++) {
 350     if ((RootEntry[Index].Uint128.Uint64Lo != 0) || (RootEntry[Index].Uint128.Uint64Hi != 0)) {
 351       DEBUG ((DEBUG_INFO,"  RootEntry(0x%02x) B%02x - 0x%016lx %016lx\n",
 352         Index, Index, RootEntry[Index].Uint128.Uint64Hi, RootEntry[Index].Uint128.Uint64Lo));
 353     }
 354     if (RootEntry[Index].Bits.Present == 0) {
 355       continue;
 356     }
 357     ContextEntry = (VTD_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(RootEntry[Index].Bits.ContextTablePointerLo, RootEntry[Index].Bits.ContextTablePointerHi);
 358     for (Index2 = 0; Index2 < VTD_CONTEXT_ENTRY_NUMBER; Index2++) {
 359       if ((ContextEntry[Index2].Uint128.Uint64Lo != 0) || (ContextEntry[Index2].Uint128.Uint64Hi != 0)) {
 360         DEBUG ((DEBUG_INFO,"    ContextEntry(0x%02x) D%02xF%02x - 0x%016lx %016lx\n",
 361           Index2, Index2 >> 3, Index2 & 0x7, ContextEntry[Index2].Uint128.Uint64Hi, ContextEntry[Index2].Uint128.Uint64Lo));
 362       }
 363       if (ContextEntry[Index2].Bits.Present == 0) {
 364         continue;
 365       }
 366       DumpSecondLevelPagingEntry ((VOID *)(UINTN)VTD_64BITS_ADDRESS(ContextEntry[Index2].Bits.SecondLevelPageTranslationPointerLo, ContextEntry[Index2].Bits.SecondLevelPageTranslationPointerHi));
 367     }
 368   }
 369   DEBUG ((DEBUG_INFO,"=========================\n"));
 370 }
 371
 372 /**
 373   Dump DMAR second level paging entry.
 374
 375   @param[in]  SecondLevelPagingEntry The second level paging entry.
 376 **/
 377 VOID
 378 DumpSecondLevelPagingEntry (
 379   IN VOID *SecondLevelPagingEntry
 380   )
 381 {
 382   UINTN                          Index4;
 383   UINTN                          Index3;
 384   UINTN                          Index2;
 385   UINTN                          Index1;
 386   VTD_SECOND_LEVEL_PAGING_ENTRY  *Lvl4PtEntry;
 387   VTD_SECOND_LEVEL_PAGING_ENTRY  *Lvl3PtEntry;
 388   VTD_SECOND_LEVEL_PAGING_ENTRY  *Lvl2PtEntry;
 389   VTD_SECOND_LEVEL_PAGING_ENTRY  *Lvl1PtEntry;
 390
 391   DEBUG ((DEBUG_VERBOSE,"================\n"));
 392   DEBUG ((DEBUG_VERBOSE,"DMAR Second Level Page Table:\n"));
 393
 394   DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry Base - 0x%x\n", SecondLevelPagingEntry));
 395   Lvl4PtEntry = (VTD_SECOND_LEVEL_PAGING_ENTRY *)SecondLevelPagingEntry;
 396   for (Index4 = 0; Index4 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); Index4++) {
 397     if (Lvl4PtEntry[Index4].Uint64 != 0) {
 398       DEBUG ((DEBUG_VERBOSE,"  Lvl4Pt Entry(0x%03x) - 0x%016lx\n", Index4, Lvl4PtEntry[Index4].Uint64));
 399     }
 400     if (Lvl4PtEntry[Index4].Uint64 == 0) {
 401       continue;
 402     }
 403     Lvl3PtEntry = (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(Lvl4PtEntry[Index4].Bits.AddressLo, Lvl4PtEntry[Index4].Bits.AddressHi);
 404     for (Index3 = 0; Index3 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); Index3++) {
 405       if (Lvl3PtEntry[Index3].Uint64 != 0) {
 406         DEBUG ((DEBUG_VERBOSE,"    Lvl3Pt Entry(0x%03x) - 0x%016lx\n", Index3, Lvl3PtEntry[Index3].Uint64));
 407       }
 408       if (Lvl3PtEntry[Index3].Uint64 == 0) {
 409         continue;
 410       }
 411
 412       Lvl2PtEntry = (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(Lvl3PtEntry[Index3].Bits.AddressLo, Lvl3PtEntry[Index3].Bits.AddressHi);
 413       for (Index2 = 0; Index2 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); Index2++) {
 414         if (Lvl2PtEntry[Index2].Uint64 != 0) {
 415           DEBUG ((DEBUG_VERBOSE,"      Lvl2Pt Entry(0x%03x) - 0x%016lx\n", Index2, Lvl2PtEntry[Index2].Uint64));
 416         }
 417         if (Lvl2PtEntry[Index2].Uint64 == 0) {
 418           continue;
 419         }
 420         if (Lvl2PtEntry[Index2].Bits.PageSize == 0) {
 421           Lvl1PtEntry = (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(Lvl2PtEntry[Index2].Bits.AddressLo, Lvl2PtEntry[Index2].Bits.AddressHi);
 422           for (Index1 = 0; Index1 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); Index1++) {
 423             if (Lvl1PtEntry[Index1].Uint64 != 0) {
 424               DEBUG ((DEBUG_VERBOSE,"        Lvl1Pt Entry(0x%03x) - 0x%016lx\n", Index1, Lvl1PtEntry[Index1].Uint64));
 425             }
 426           }
 427         }
 428       }
 429     }
 430   }
 431   DEBUG ((DEBUG_VERBOSE,"================\n"));
 432 }
 433
 434 /**
 435   Invalid page entry.
 436
 437   @param VtdIndex  The VTd engine index.
 438 **/
 439 VOID
 440 InvalidatePageEntry (
 441   IN UINTN                 VtdIndex
 442   )
 443 {
 444   if (mVtdUnitInformation[VtdIndex].HasDirtyContext || mVtdUnitInformation[VtdIndex].HasDirtyPages) {
 445     InvalidateVtdIOTLBGlobal (VtdIndex);
 446   }
 447   mVtdUnitInformation[VtdIndex].HasDirtyContext = FALSE;
 448   mVtdUnitInformation[VtdIndex].HasDirtyPages = FALSE;
 449 }
 450
 451 #define VTD_PG_R                   BIT0
 452 #define VTD_PG_W                   BIT1
 453 #define VTD_PG_X                   BIT2
 454 #define VTD_PG_EMT                 (BIT3 | BIT4 | BIT5)
 455 #define VTD_PG_TM                  (BIT62)
 456
 457 #define VTD_PG_PS                  BIT7
 458
 459 #define PAGE_PROGATE_BITS          (VTD_PG_TM | VTD_PG_EMT | VTD_PG_W | VTD_PG_R)
 460
 461 #define PAGING_4K_MASK  0xFFF
 462 #define PAGING_2M_MASK  0x1FFFFF
 463 #define PAGING_1G_MASK  0x3FFFFFFF
 464
 465 #define PAGING_VTD_INDEX_MASK     0x1FF
 466
 467 #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
 468 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
 469 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
 470
 471 typedef enum {
 472   PageNone,
 473   Page4K,
 474   Page2M,
 475   Page1G,
 476 } PAGE_ATTRIBUTE;
 477
 478 typedef struct {
 479   PAGE_ATTRIBUTE   Attribute;
 480   UINT64           Length;
 481   UINT64           AddressMask;
 482 } PAGE_ATTRIBUTE_TABLE;
 483
 484 PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
 485   {Page4K,  SIZE_4KB, PAGING_4K_ADDRESS_MASK_64},
 486   {Page2M,  SIZE_2MB, PAGING_2M_ADDRESS_MASK_64},
 487   {Page1G,  SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},
 488 };
 489
 490 /**
 491   Return length according to page attributes.
 492
 493   @param[in]  PageAttributes   The page attribute of the page entry.
 494
 495   @return The length of page entry.
 496 **/
 497 UINTN
 498 PageAttributeToLength (
 499   IN PAGE_ATTRIBUTE  PageAttribute
 500   )
 501 {
 502   UINTN  Index;
 503   for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {
 504     if (PageAttribute == mPageAttributeTable[Index].Attribute) {
 505       return (UINTN)mPageAttributeTable[Index].Length;
 506     }
 507   }
 508   return 0;
 509 }
 510
 511 /**
 512   Return page table entry to match the address.
 513
 514   @param[in]   VtdIndex                 The index used to identify a VTd engine.
 515   @param[in]   SecondLevelPagingEntry   The second level paging entry in VTd table for the device.
 516   @param[in]   Address                  The address to be checked.
 517   @param[out]  PageAttributes           The page attribute of the page entry.
 518
 519   @return The page entry.
 520 **/
 521 VOID *
 522 GetSecondLevelPageTableEntry (
 523   IN  UINTN                         VtdIndex,
 524   IN  VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry,
 525   IN  PHYSICAL_ADDRESS              Address,
 526   OUT PAGE_ATTRIBUTE                *PageAttribute
 527   )
 528 {
 529   UINTN                 Index1;
 530   UINTN                 Index2;
 531   UINTN                 Index3;
 532   UINTN                 Index4;
 533   UINT64                *L1PageTable;
 534   UINT64                *L2PageTable;
 535   UINT64                *L3PageTable;
 536   UINT64                *L4PageTable;
 537
 538   Index4 = ((UINTN)RShiftU64 (Address, 39)) & PAGING_VTD_INDEX_MASK;
 539   Index3 = ((UINTN)Address >> 30) & PAGING_VTD_INDEX_MASK;
 540   Index2 = ((UINTN)Address >> 21) & PAGING_VTD_INDEX_MASK;
 541   Index1 = ((UINTN)Address >> 12) & PAGING_VTD_INDEX_MASK;
 542
 543   L4PageTable = (UINT64 *)SecondLevelPagingEntry;
 544   if (L4PageTable[Index4] == 0) {
 545     L4PageTable[Index4] = (UINT64)(UINTN)AllocateZeroPages (1);
 546     if (L4PageTable[Index4] == 0) {
 547       DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL4 PAGE FAIL (0x%x)!!!!!!\n", Index4));
 548       ASSERT(FALSE);
 549       *PageAttribute = PageNone;
 550       return NULL;
 551     }
 552     FlushPageTableMemory (VtdIndex, (UINTN)L4PageTable[Index4], SIZE_4KB);
 553     SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&L4PageTable[Index4], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
 554     FlushPageTableMemory (VtdIndex, (UINTN)&L4PageTable[Index4], sizeof(L4PageTable[Index4]));
 555   }
 556
 557   L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_ADDRESS_MASK_64);
 558   if (L3PageTable[Index3] == 0) {
 559     L3PageTable[Index3] = (UINT64)(UINTN)AllocateZeroPages (1);
 560     if (L3PageTable[Index3] == 0) {
 561       DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL3 PAGE FAIL (0x%x, 0x%x)!!!!!!\n", Index4, Index3));
 562       ASSERT(FALSE);
 563       *PageAttribute = PageNone;
 564       return NULL;
 565     }
 566     FlushPageTableMemory (VtdIndex, (UINTN)L3PageTable[Index3], SIZE_4KB);
 567     SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&L3PageTable[Index3], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
 568     FlushPageTableMemory (VtdIndex, (UINTN)&L3PageTable[Index3], sizeof(L3PageTable[Index3]));
 569   }
 570   if ((L3PageTable[Index3] & VTD_PG_PS) != 0) {
 571     // 1G
 572     *PageAttribute = Page1G;
 573     return &L3PageTable[Index3];
 574   }
 575
 576   L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRESS_MASK_64);
 577   if (L2PageTable[Index2] == 0) {
 578     L2PageTable[Index2] = Address & PAGING_2M_ADDRESS_MASK_64;
 579     SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&L2PageTable[Index2], 0);
 580     L2PageTable[Index2] |= VTD_PG_PS;
 581     FlushPageTableMemory (VtdIndex, (UINTN)&L2PageTable[Index2], sizeof(L2PageTable[Index2]));
 582   }
 583   if ((L2PageTable[Index2] & VTD_PG_PS) != 0) {
 584     // 2M
 585     *PageAttribute = Page2M;
 586     return &L2PageTable[Index2];
 587   }
 588
 589   // 4k
 590   L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRESS_MASK_64);
 591   if ((L1PageTable[Index1] == 0) && (Address != 0)) {
 592     *PageAttribute = PageNone;
 593     return NULL;
 594   }
 595   *PageAttribute = Page4K;
 596   return &L1PageTable[Index1];
 597 }
 598
 599 /**
 600   Modify memory attributes of page entry.
 601
 602   @param[in]   VtdIndex         The index used to identify a VTd engine.
 603   @param[in]   PageEntry        The page entry.
 604   @param[in]   IoMmuAccess      The IOMMU access.
 605   @param[out]  IsModified       TRUE means page table modified. FALSE means page table not modified.
 606 **/
 607 VOID
 608 ConvertSecondLevelPageEntryAttribute (
 609   IN  UINTN                             VtdIndex,
 610   IN  VTD_SECOND_LEVEL_PAGING_ENTRY     *PageEntry,
 611   IN  UINT64                            IoMmuAccess,
 612   OUT BOOLEAN                           *IsModified
 613   )
 614 {
 615   UINT64  CurrentPageEntry;
 616   UINT64  NewPageEntry;
 617
 618   CurrentPageEntry = PageEntry->Uint64;
 619   SetSecondLevelPagingEntryAttribute (PageEntry, IoMmuAccess);
 620   FlushPageTableMemory (VtdIndex, (UINTN)PageEntry, sizeof(*PageEntry));
 621   NewPageEntry = PageEntry->Uint64;
 622   if (CurrentPageEntry != NewPageEntry) {
 623     *IsModified = TRUE;
 624     DEBUG ((DEBUG_VERBOSE, "ConvertSecondLevelPageEntryAttribute 0x%lx", CurrentPageEntry));
 625     DEBUG ((DEBUG_VERBOSE, "->0x%lx\n", NewPageEntry));
 626   } else {
 627     *IsModified = FALSE;
 628   }
 629 }
 630
 631 /**
 632   This function returns if there is need to split page entry.
 633
 634   @param[in]  BaseAddress      The base address to be checked.
 635   @param[in]  Length           The length to be checked.
 636   @param[in]  PageAttribute    The page attribute of the page entry.
 637
 638   @retval SplitAttributes on if there is need to split page entry.
 639 **/
 640 PAGE_ATTRIBUTE
 641 NeedSplitPage (
 642   IN  PHYSICAL_ADDRESS                  BaseAddress,
 643   IN  UINT64                            Length,
 644   IN  PAGE_ATTRIBUTE                    PageAttribute
 645   )
 646 {
 647   UINT64                PageEntryLength;
 648
 649   PageEntryLength = PageAttributeToLength (PageAttribute);
 650
 651   if (((BaseAddress & (PageEntryLength - 1)) == 0) && (Length >= PageEntryLength)) {
 652     return PageNone;
 653   }
 654
 655   if (((BaseAddress & PAGING_2M_MASK) != 0) || (Length < SIZE_2MB)) {
 656     return Page4K;
 657   }
 658
 659   return Page2M;
 660 }
 661
 662 /**
 663   This function splits one page entry to small page entries.
 664
 665   @param[in]  VtdIndex         The index used to identify a VTd engine.
 666   @param[in]  PageEntry        The page entry to be splitted.
 667   @param[in]  PageAttribute    The page attribute of the page entry.
 668   @param[in]  SplitAttribute   How to split the page entry.
 669
 670   @retval RETURN_SUCCESS            The page entry is splitted.
 671   @retval RETURN_UNSUPPORTED        The page entry does not support to be splitted.
 672   @retval RETURN_OUT_OF_RESOURCES   No resource to split page entry.
 673 **/
 674 RETURN_STATUS
 675 SplitSecondLevelPage (
 676   IN  UINTN                             VtdIndex,
 677   IN  VTD_SECOND_LEVEL_PAGING_ENTRY     *PageEntry,
 678   IN  PAGE_ATTRIBUTE                    PageAttribute,
 679   IN  PAGE_ATTRIBUTE                    SplitAttribute
 680   )
 681 {
 682   UINT64   BaseAddress;
 683   UINT64   *NewPageEntry;
 684   UINTN    Index;
 685
 686   ASSERT (PageAttribute == Page2M || PageAttribute == Page1G);
 687
 688   if (PageAttribute == Page2M) {
 689     //
 690     // Split 2M to 4K
 691     //
 692     ASSERT (SplitAttribute == Page4K);
 693     if (SplitAttribute == Page4K) {
 694       NewPageEntry = AllocateZeroPages (1);
 695       DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));
 696       if (NewPageEntry == NULL) {
 697         return RETURN_OUT_OF_RESOURCES;
 698       }
 699       BaseAddress = PageEntry->Uint64 & PAGING_2M_ADDRESS_MASK_64;
 700       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
 701         NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | (PageEntry->Uint64 & PAGE_PROGATE_BITS);
 702       }
 703       FlushPageTableMemory (VtdIndex, (UINTN)NewPageEntry, SIZE_4KB);
 704
 705       PageEntry->Uint64 = (UINT64)(UINTN)NewPageEntry;
 706       SetSecondLevelPagingEntryAttribute (PageEntry, EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
 707       FlushPageTableMemory (VtdIndex, (UINTN)PageEntry, sizeof(*PageEntry));
 708       return RETURN_SUCCESS;
 709     } else {
 710       return RETURN_UNSUPPORTED;
 711     }
 712   } else if (PageAttribute == Page1G) {
 713     //
 714     // Split 1G to 2M
 715     // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.
 716     //
 717     ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);
 718     if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) {
 719       NewPageEntry = AllocateZeroPages (1);
 720       DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));
 721       if (NewPageEntry == NULL) {
 722         return RETURN_OUT_OF_RESOURCES;
 723       }
 724       BaseAddress = PageEntry->Uint64 & PAGING_1G_ADDRESS_MASK_64;
 725       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
 726         NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | VTD_PG_PS | (PageEntry->Uint64 & PAGE_PROGATE_BITS);
 727       }
 728       FlushPageTableMemory (VtdIndex, (UINTN)NewPageEntry, SIZE_4KB);
 729
 730       PageEntry->Uint64 = (UINT64)(UINTN)NewPageEntry;
 731       SetSecondLevelPagingEntryAttribute (PageEntry, EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
 732       FlushPageTableMemory (VtdIndex, (UINTN)PageEntry, sizeof(*PageEntry));
 733       return RETURN_SUCCESS;
 734     } else {
 735       return RETURN_UNSUPPORTED;
 736     }
 737   } else {
 738     return RETURN_UNSUPPORTED;
 739   }
 740 }
 741
 742 /**
 743   Set VTd attribute for a system memory on second level page entry
 744
 745   @param[in]  VtdIndex                The index used to identify a VTd engine.
 746   @param[in]  DomainIdentifier        The domain ID of the source.
 747   @param[in]  SecondLevelPagingEntry  The second level paging entry in VTd table for the device.
 748   @param[in]  BaseAddress             The base of device memory address to be used as the DMA memory.
 749   @param[in]  Length                  The length of device memory address to be used as the DMA memory.
 750   @param[in]  IoMmuAccess             The IOMMU access.
 751
 752   @retval EFI_SUCCESS            The IoMmuAccess is set for the memory range specified by BaseAddress and Length.
 753   @retval EFI_INVALID_PARAMETER  BaseAddress is not IoMmu Page size aligned.
 754   @retval EFI_INVALID_PARAMETER  Length is not IoMmu Page size aligned.
 755   @retval EFI_INVALID_PARAMETER  Length is 0.
 756   @retval EFI_INVALID_PARAMETER  IoMmuAccess specified an illegal combination of access.
 757   @retval EFI_UNSUPPORTED        The bit mask of IoMmuAccess is not supported by the IOMMU.
 758   @retval EFI_UNSUPPORTED        The IOMMU does not support the memory range specified by BaseAddress and Length.
 759   @retval EFI_OUT_OF_RESOURCES   There are not enough resources available to modify the IOMMU access.
 760   @retval EFI_DEVICE_ERROR       The IOMMU device reported an error while attempting the operation.
 761 **/
 762 EFI_STATUS
 763 SetSecondLevelPagingAttribute (
 764   IN UINTN                         VtdIndex,
 765   IN UINT16                        DomainIdentifier,
 766   IN VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry,
 767   IN UINT64                        BaseAddress,
 768   IN UINT64                        Length,
 769   IN UINT64                        IoMmuAccess
 770   )
 771 {
 772   VTD_SECOND_LEVEL_PAGING_ENTRY  *PageEntry;
 773   PAGE_ATTRIBUTE                 PageAttribute;
 774   UINTN                          PageEntryLength;
 775   PAGE_ATTRIBUTE                 SplitAttribute;
 776   EFI_STATUS                     Status;
 777   BOOLEAN                        IsEntryModified;
 778
 779   DEBUG ((DEBUG_VERBOSE,"SetSecondLevelPagingAttribute (%d) (0x%016lx - 0x%016lx : %x) \n", VtdIndex, BaseAddress, Length, IoMmuAccess));
 780   DEBUG ((DEBUG_VERBOSE,"  SecondLevelPagingEntry Base - 0x%x\n", SecondLevelPagingEntry));
 781
 782   if (BaseAddress != ALIGN_VALUE(BaseAddress, SIZE_4KB)) {
 783     DEBUG ((DEBUG_ERROR, "SetSecondLevelPagingAttribute - Invalid Alignment\n"));
 784     return EFI_UNSUPPORTED;
 785   }
 786   if (Length != ALIGN_VALUE(Length, SIZE_4KB)) {
 787     DEBUG ((DEBUG_ERROR, "SetSecondLevelPagingAttribute - Invalid Alignment\n"));
 788     return EFI_UNSUPPORTED;
 789   }
 790
 791   while (Length != 0) {
 792     PageEntry = GetSecondLevelPageTableEntry (VtdIndex, SecondLevelPagingEntry, BaseAddress, &PageAttribute);
 793     if (PageEntry == NULL) {
 794       DEBUG ((DEBUG_ERROR, "PageEntry - NULL\n"));
 795       return RETURN_UNSUPPORTED;
 796     }
 797     PageEntryLength = PageAttributeToLength (PageAttribute);
 798     SplitAttribute = NeedSplitPage (BaseAddress, Length, PageAttribute);
 799     if (SplitAttribute == PageNone) {
 800       ConvertSecondLevelPageEntryAttribute (VtdIndex, PageEntry, IoMmuAccess, &IsEntryModified);
 801       if (IsEntryModified) {
 802         mVtdUnitInformation[VtdIndex].HasDirtyPages = TRUE;
 803       }
 804       //
 805       // Convert success, move to next
 806       //
 807       BaseAddress += PageEntryLength;
 808       Length -= PageEntryLength;
 809     } else {
 810       Status = SplitSecondLevelPage (VtdIndex, PageEntry, PageAttribute, SplitAttribute);
 811       if (RETURN_ERROR (Status)) {
 812         DEBUG ((DEBUG_ERROR, "SplitSecondLevelPage - %r\n", Status));
 813         return RETURN_UNSUPPORTED;
 814       }
 815       mVtdUnitInformation[VtdIndex].HasDirtyPages = TRUE;
 816       //
 817       // Just split current page
 818       // Convert success in next around
 819       //
 820     }
 821   }
 822
 823   return EFI_SUCCESS;
 824 }
 825
 826 /**
 827   Set VTd attribute for a system memory.
 828
 829   @param[in]  VtdIndex                The index used to identify a VTd engine.
 830   @param[in]  DomainIdentifier        The domain ID of the source.
 831   @param[in]  SecondLevelPagingEntry  The second level paging entry in VTd table for the device.
 832   @param[in]  BaseAddress             The base of device memory address to be used as the DMA memory.
 833   @param[in]  Length                  The length of device memory address to be used as the DMA memory.
 834   @param[in]  IoMmuAccess             The IOMMU access.
 835
 836   @retval EFI_SUCCESS            The IoMmuAccess is set for the memory range specified by BaseAddress and Length.
 837   @retval EFI_INVALID_PARAMETER  BaseAddress is not IoMmu Page size aligned.
 838   @retval EFI_INVALID_PARAMETER  Length is not IoMmu Page size aligned.
 839   @retval EFI_INVALID_PARAMETER  Length is 0.
 840   @retval EFI_INVALID_PARAMETER  IoMmuAccess specified an illegal combination of access.
 841   @retval EFI_UNSUPPORTED        The bit mask of IoMmuAccess is not supported by the IOMMU.
 842   @retval EFI_UNSUPPORTED        The IOMMU does not support the memory range specified by BaseAddress and Length.
 843   @retval EFI_OUT_OF_RESOURCES   There are not enough resources available to modify the IOMMU access.
 844   @retval EFI_DEVICE_ERROR       The IOMMU device reported an error while attempting the operation.
 845 **/
 846 EFI_STATUS
 847 SetPageAttribute (
 848   IN UINTN                         VtdIndex,
 849   IN UINT16                        DomainIdentifier,
 850   IN VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry,
 851   IN UINT64                        BaseAddress,
 852   IN UINT64                        Length,
 853   IN UINT64                        IoMmuAccess
 854   )
 855 {
 856   EFI_STATUS Status;
 857   Status = EFI_NOT_FOUND;
 858   if (SecondLevelPagingEntry != NULL) {
 859     Status = SetSecondLevelPagingAttribute (VtdIndex, DomainIdentifier, SecondLevelPagingEntry, BaseAddress, Length, IoMmuAccess);
 860   }
 861   return Status;
 862 }
 863
 864 /**
 865   Set VTd attribute for a system memory.
 866
 867   @param[in]  Segment           The Segment used to identify a VTd engine.
 868   @param[in]  SourceId          The SourceId used to identify a VTd engine and table entry.
 869   @param[in]  BaseAddress       The base of device memory address to be used as the DMA memory.
 870   @param[in]  Length            The length of device memory address to be used as the DMA memory.
 871   @param[in]  IoMmuAccess       The IOMMU access.
 872
 873   @retval EFI_SUCCESS            The IoMmuAccess is set for the memory range specified by BaseAddress and Length.
 874   @retval EFI_INVALID_PARAMETER  BaseAddress is not IoMmu Page size aligned.
 875   @retval EFI_INVALID_PARAMETER  Length is not IoMmu Page size aligned.
 876   @retval EFI_INVALID_PARAMETER  Length is 0.
 877   @retval EFI_INVALID_PARAMETER  IoMmuAccess specified an illegal combination of access.
 878   @retval EFI_UNSUPPORTED        The bit mask of IoMmuAccess is not supported by the IOMMU.
 879   @retval EFI_UNSUPPORTED        The IOMMU does not support the memory range specified by BaseAddress and Length.
 880   @retval EFI_OUT_OF_RESOURCES   There are not enough resources available to modify the IOMMU access.
 881   @retval EFI_DEVICE_ERROR       The IOMMU device reported an error while attempting the operation.
 882 **/
 883 EFI_STATUS
 884 SetAccessAttribute (
 885   IN UINT16                Segment,
 886   IN VTD_SOURCE_ID         SourceId,
 887   IN UINT64                BaseAddress,
 888   IN UINT64                Length,
 889   IN UINT64                IoMmuAccess
 890   )
 891 {
 892   UINTN                         VtdIndex;
 893   EFI_STATUS                    Status;
 894   VTD_EXT_CONTEXT_ENTRY         *ExtContextEntry;
 895   VTD_CONTEXT_ENTRY             *ContextEntry;
 896   VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry;
 897   UINT64                        Pt;
 898   UINTN                         PciDataIndex;
 899   UINT16                        DomainIdentifier;
 900
 901   SecondLevelPagingEntry = NULL;
 902
 903   DEBUG ((DEBUG_VERBOSE,"SetAccessAttribute (S%04x B%02x D%02x F%02x) (0x%016lx - 0x%08x, %x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function, BaseAddress, (UINTN)Length, IoMmuAccess));
 904
 905   VtdIndex = FindVtdIndexByPciDevice (Segment, SourceId, &ExtContextEntry, &ContextEntry);
 906   if (VtdIndex == (UINTN)-1) {
 907     DEBUG ((DEBUG_ERROR,"SetAccessAttribute - Pci device (S%04x B%02x D%02x F%02x) not found!\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
 908     return EFI_DEVICE_ERROR;
 909   }
 910
 911   PciDataIndex = GetPciDataIndex (VtdIndex, Segment, SourceId);
 912   mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceData[PciDataIndex].AccessCount++;
 913   //
 914   // DomainId should not be 0.
 915   //
 916   DomainIdentifier = (UINT16)(PciDataIndex + 1);
 917
 918   if (ExtContextEntry != NULL) {
 919     if (ExtContextEntry->Bits.Present == 0) {
 920       SecondLevelPagingEntry = CreateSecondLevelPagingEntry (VtdIndex, 0);
 921       DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%02x F%02x) New\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
 922       Pt = (UINT64)RShiftU64 ((UINT64)(UINTN)SecondLevelPagingEntry, 12);
 923
 924       ExtContextEntry->Bits.SecondLevelPageTranslationPointerLo = (UINT32) Pt;
 925       ExtContextEntry->Bits.SecondLevelPageTranslationPointerHi = (UINT32) RShiftU64(Pt, 20);
 926       ExtContextEntry->Bits.DomainIdentifier = DomainIdentifier;
 927       ExtContextEntry->Bits.Present = 1;
 928       FlushPageTableMemory (VtdIndex, (UINTN)ExtContextEntry, sizeof(*ExtContextEntry));
 929       DumpDmarExtContextEntryTable (mVtdUnitInformation[VtdIndex].ExtRootEntryTable);
 930       mVtdUnitInformation[VtdIndex].HasDirtyContext = TRUE;
 931     } else {
 932       SecondLevelPagingEntry = (VOID *)(UINTN)VTD_64BITS_ADDRESS(ExtContextEntry->Bits.SecondLevelPageTranslationPointerLo, ExtContextEntry->Bits.SecondLevelPageTranslationPointerHi);
 933       DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%02x F%02x)\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
 934     }
 935   } else if (ContextEntry != NULL) {
 936     if (ContextEntry->Bits.Present == 0) {
 937       SecondLevelPagingEntry = CreateSecondLevelPagingEntry (VtdIndex, 0);
 938       DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%02x F%02x) New\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
 939       Pt = (UINT64)RShiftU64 ((UINT64)(UINTN)SecondLevelPagingEntry, 12);
 940
 941       ContextEntry->Bits.SecondLevelPageTranslationPointerLo = (UINT32) Pt;
 942       ContextEntry->Bits.SecondLevelPageTranslationPointerHi = (UINT32) RShiftU64(Pt, 20);
 943       ContextEntry->Bits.DomainIdentifier = DomainIdentifier;
 944       ContextEntry->Bits.Present = 1;
 945       FlushPageTableMemory (VtdIndex, (UINTN)ContextEntry, sizeof(*ContextEntry));
 946       DumpDmarContextEntryTable (mVtdUnitInformation[VtdIndex].RootEntryTable);
 947       mVtdUnitInformation[VtdIndex].HasDirtyContext = TRUE;
 948     } else {
 949       SecondLevelPagingEntry = (VOID *)(UINTN)VTD_64BITS_ADDRESS(ContextEntry->Bits.SecondLevelPageTranslationPointerLo, ContextEntry->Bits.SecondLevelPageTranslationPointerHi);
 950       DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%02x F%02x)\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
 951     }
 952   }
 953
 954   //
 955   // Do not update FixedSecondLevelPagingEntry
 956   //
 957   if (SecondLevelPagingEntry != mVtdUnitInformation[VtdIndex].FixedSecondLevelPagingEntry) {
 958     Status = SetPageAttribute (
 959                VtdIndex,
 960                DomainIdentifier,
 961                SecondLevelPagingEntry,
 962                BaseAddress,
 963                Length,
 964                IoMmuAccess
 965                );
 966     if (EFI_ERROR (Status)) {
 967       DEBUG ((DEBUG_ERROR,"SetPageAttribute - %r\n", Status));
 968       return Status;
 969     }
 970   }
 971
 972   InvalidatePageEntry (VtdIndex);
 973
 974   return EFI_SUCCESS;
 975 }
 976
 977 /**
 978   Always enable the VTd page attribute for the device.
 979
 980   @param[in]  Segment           The Segment used to identify a VTd engine.
 981   @param[in]  SourceId          The SourceId used to identify a VTd engine and table entry.
 982
 983   @retval EFI_SUCCESS           The VTd entry is updated to always enable all DMA access for the specific device.
 984 **/
 985 EFI_STATUS
 986 AlwaysEnablePageAttribute (
 987   IN UINT16                  Segment,
 988   IN VTD_SOURCE_ID           SourceId
 989   )
 990 {
 991   UINTN                         VtdIndex;
 992   VTD_EXT_CONTEXT_ENTRY         *ExtContextEntry;
 993   VTD_CONTEXT_ENTRY             *ContextEntry;
 994   VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry;
 995   UINT64                        Pt;
 996
 997   DEBUG ((DEBUG_INFO,"AlwaysEnablePageAttribute (S%04x B%02x D%02x F%02x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
 998
 999   VtdIndex = FindVtdIndexByPciDevice (Segment, SourceId, &ExtContextEntry, &ContextEntry);
1000   if (VtdIndex == (UINTN)-1) {
1001     DEBUG ((DEBUG_ERROR,"AlwaysEnablePageAttribute - Pci device (S%04x B%02x D%02x F%02x) not found!\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
1002     return EFI_DEVICE_ERROR;
1003   }
1004
1005   if (mVtdUnitInformation[VtdIndex].FixedSecondLevelPagingEntry == 0) {
1006     DEBUG((DEBUG_INFO, "CreateSecondLevelPagingEntry - %d\n", VtdIndex));
1007     mVtdUnitInformation[VtdIndex].FixedSecondLevelPagingEntry = CreateSecondLevelPagingEntry (VtdIndex, EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
1008   }
1009
1010   SecondLevelPagingEntry = mVtdUnitInformation[VtdIndex].FixedSecondLevelPagingEntry;
1011   Pt = (UINT64)RShiftU64 ((UINT64)(UINTN)SecondLevelPagingEntry, 12);
1012   if (ExtContextEntry != NULL) {
1013     ExtContextEntry->Bits.SecondLevelPageTranslationPointerLo = (UINT32) Pt;
1014     ExtContextEntry->Bits.SecondLevelPageTranslationPointerHi = (UINT32) RShiftU64(Pt, 20);
1015     ExtContextEntry->Bits.DomainIdentifier = ((1 << (UINT8)((UINTN)mVtdUnitInformation[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1);
1016     ExtContextEntry->Bits.Present = 1;
1017     FlushPageTableMemory (VtdIndex, (UINTN)ExtContextEntry, sizeof(*ExtContextEntry));
1018   } else if (ContextEntry != NULL) {
1019     ContextEntry->Bits.SecondLevelPageTranslationPointerLo = (UINT32) Pt;
1020     ContextEntry->Bits.SecondLevelPageTranslationPointerHi = (UINT32) RShiftU64(Pt, 20);
1021     ContextEntry->Bits.DomainIdentifier = ((1 << (UINT8)((UINTN)mVtdUnitInformation[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1);
1022     ContextEntry->Bits.Present = 1;
1023     FlushPageTableMemory (VtdIndex, (UINTN)ContextEntry, sizeof(*ContextEntry));
1024   }
1025
1026   return EFI_SUCCESS;
1027 }