8dbc83fa2d6764654209d820f4a98ab9e9c90785
[mirror_edk2.git] / IntelSiliconPkg / Feature / VTd / IntelVTdDxe / VtdReg.c
1 /** @file
2
3 Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php.
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 **/
13
14 #include "DmaProtection.h"
15
16 UINTN mVtdUnitNumber;
17 VTD_UNIT_INFORMATION *mVtdUnitInformation;
18
19 BOOLEAN mVtdEnabled;
20
21 /**
22 Flush VTD page table and context table memory.
23
24 This action is to make sure the IOMMU engine can get final data in memory.
25
26 @param[in] VtdIndex The index used to identify a VTd engine.
27 @param[in] Base The base address of memory to be flushed.
28 @param[in] Size The size of memory in bytes to be flushed.
29 **/
30 VOID
31 FlushPageTableMemory (
32 IN UINTN VtdIndex,
33 IN UINTN Base,
34 IN UINTN Size
35 )
36 {
37 if (mVtdUnitInformation[VtdIndex].ECapReg.Bits.C == 0) {
38 WriteBackDataCacheRange ((VOID *)Base, Size);
39 }
40 }
41
42 /**
43 Flush VTd engine write buffer.
44
45 @param[in] VtdIndex The index used to identify a VTd engine.
46 **/
47 VOID
48 FlushWriteBuffer (
49 IN UINTN VtdIndex
50 )
51 {
52 UINT32 Reg32;
53
54 if (mVtdUnitInformation[VtdIndex].CapReg.Bits.RWBF != 0) {
55 Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
56 MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_WBF);
57 do {
58 Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
59 } while ((Reg32 & B_GSTS_REG_WBF) != 0);
60 }
61 }
62
63 /**
64 Invalidate VTd context cache.
65
66 @param[in] VtdIndex The index used to identify a VTd engine.
67 **/
68 EFI_STATUS
69 InvalidateContextCache (
70 IN UINTN VtdIndex
71 )
72 {
73 UINT64 Reg64;
74
75 Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);
76 if ((Reg64 & B_CCMD_REG_ICC) != 0) {
77 DEBUG ((DEBUG_ERROR,"ERROR: InvalidateContextCache: B_CCMD_REG_ICC is set for VTD(%d)\n",VtdIndex));
78 return EFI_DEVICE_ERROR;
79 }
80
81 Reg64 &= ((~B_CCMD_REG_ICC) & (~B_CCMD_REG_CIRG_MASK));
82 Reg64 |= (B_CCMD_REG_ICC | V_CCMD_REG_CIRG_GLOBAL);
83 MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG, Reg64);
84
85 do {
86 Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);
87 } while ((Reg64 & B_CCMD_REG_ICC) != 0);
88
89 return EFI_SUCCESS;
90 }
91
92 /**
93 Invalidate VTd IOTLB.
94
95 @param[in] VtdIndex The index used to identify a VTd engine.
96 **/
97 EFI_STATUS
98 InvalidateIOTLB (
99 IN UINTN VtdIndex
100 )
101 {
102 UINT64 Reg64;
103
104 Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);
105 if ((Reg64 & B_IOTLB_REG_IVT) != 0) {
106 DEBUG ((DEBUG_ERROR,"ERROR: InvalidateIOTLB: B_IOTLB_REG_IVT is set for VTD(%d)\n", VtdIndex));
107 return EFI_DEVICE_ERROR;
108 }
109
110 Reg64 &= ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK));
111 Reg64 |= (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_GLOBAL);
112 MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG, Reg64);
113
114 do {
115 Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);
116 } while ((Reg64 & B_IOTLB_REG_IVT) != 0);
117
118 return EFI_SUCCESS;
119 }
120
121 /**
122 Invalid VTd global IOTLB.
123
124 @param[in] VtdIndex The index of VTd engine.
125
126 @retval EFI_SUCCESS VTd global IOTLB is invalidated.
127 @retval EFI_DEVICE_ERROR VTd global IOTLB is not invalidated.
128 **/
129 EFI_STATUS
130 InvalidateVtdIOTLBGlobal (
131 IN UINTN VtdIndex
132 )
133 {
134 if (!mVtdEnabled) {
135 return EFI_SUCCESS;
136 }
137
138 DEBUG((DEBUG_VERBOSE, "InvalidateVtdIOTLBGlobal(%d)\n", VtdIndex));
139
140 //
141 // Write Buffer Flush before invalidation
142 //
143 FlushWriteBuffer (VtdIndex);
144
145 //
146 // Invalidate the context cache
147 //
148 if (mVtdUnitInformation[VtdIndex].HasDirtyContext) {
149 InvalidateContextCache (VtdIndex);
150 }
151
152 //
153 // Invalidate the IOTLB cache
154 //
155 if (mVtdUnitInformation[VtdIndex].HasDirtyContext || mVtdUnitInformation[VtdIndex].HasDirtyPages) {
156 InvalidateIOTLB (VtdIndex);
157 }
158
159 return EFI_SUCCESS;
160 }
161
162 /**
163 Prepare VTD configuration.
164 **/
165 VOID
166 PrepareVtdConfig (
167 VOID
168 )
169 {
170 UINTN Index;
171 UINTN DomainNumber;
172
173 for (Index = 0; Index < mVtdUnitNumber; Index++) {
174 DEBUG ((DEBUG_INFO, "Dump VTd Capability (%d)\n", Index));
175 mVtdUnitInformation[Index].CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);
176 DumpVtdCapRegs (&mVtdUnitInformation[Index].CapReg);
177 mVtdUnitInformation[Index].ECapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_ECAP_REG);
178 DumpVtdECapRegs (&mVtdUnitInformation[Index].ECapReg);
179
180 if ((mVtdUnitInformation[Index].CapReg.Bits.SLLPS & BIT0) == 0) {
181 DEBUG((DEBUG_WARN, "!!!! 2MB super page is not supported on VTD %d !!!!\n", Index));
182 }
183 if ((mVtdUnitInformation[Index].CapReg.Bits.SAGAW & BIT2) == 0) {
184 DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", Index));
185 return ;
186 }
187
188 DomainNumber = (UINTN)1 << (UINT8)((UINTN)mVtdUnitInformation[Index].CapReg.Bits.ND * 2 + 4);
189 if (mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber >= DomainNumber) {
190 DEBUG((DEBUG_ERROR, "!!!! Pci device Number(0x%x) >= DomainNumber(0x%x) !!!!\n", mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber, DomainNumber));
191 return ;
192 }
193 }
194 return ;
195 }
196
197 /**
198 Disable PMR in all VTd engine.
199 **/
200 VOID
201 DisablePmr (
202 VOID
203 )
204 {
205 UINT32 Reg32;
206 VTD_CAP_REG CapReg;
207 UINTN Index;
208
209 DEBUG ((DEBUG_INFO,"DisablePmr\n"));
210 for (Index = 0; Index < mVtdUnitNumber; Index++) {
211 CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);
212 if (CapReg.Bits.PLMR == 0 || CapReg.Bits.PHMR == 0) {
213 continue ;
214 }
215
216 Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
217 if ((Reg32 & BIT0) != 0) {
218 MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG, 0x0);
219 do {
220 Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
221 } while((Reg32 & BIT0) != 0);
222 DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index));
223 } else {
224 DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index));
225 }
226 }
227 return ;
228 }
229
230 /**
231 Enable DMAR translation.
232
233 @retval EFI_SUCCESS DMAR translation is enabled.
234 @retval EFI_DEVICE_ERROR DMAR translation is not enabled.
235 **/
236 EFI_STATUS
237 EnableDmar (
238 VOID
239 )
240 {
241 UINTN Index;
242 UINT32 Reg32;
243
244 for (Index = 0; Index < mVtdUnitNumber; Index++) {
245 DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] \n", Index));
246
247 if (mVtdUnitInformation[Index].ExtRootEntryTable != NULL) {
248 DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[Index].ExtRootEntryTable));
249 MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].ExtRootEntryTable | BIT11);
250 } else {
251 DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[Index].RootEntryTable));
252 MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].RootEntryTable);
253 }
254
255 MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);
256
257 DEBUG((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n"));
258 do {
259 Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
260 } while((Reg32 & B_GSTS_REG_RTPS) == 0);
261
262 //
263 // Init DMAr Fault Event and Data registers
264 //
265 Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_FEDATA_REG);
266
267 //
268 // Write Buffer Flush before invalidation
269 //
270 FlushWriteBuffer (Index);
271
272 //
273 // Invalidate the context cache
274 //
275 InvalidateContextCache (Index);
276
277 //
278 // Invalidate the IOTLB cache
279 //
280 InvalidateIOTLB (Index);
281
282 //
283 // Enable VTd
284 //
285 MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_TE);
286 DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n"));
287 do {
288 Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
289 } while ((Reg32 & B_GSTS_REG_TE) == 0);
290
291 DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index));
292 }
293
294 //
295 // Need disable PMR, since we already setup translation table.
296 //
297 DisablePmr ();
298
299 mVtdEnabled = TRUE;
300
301 return EFI_SUCCESS;
302 }
303
304 /**
305 Disable DMAR translation.
306
307 @retval EFI_SUCCESS DMAR translation is disabled.
308 @retval EFI_DEVICE_ERROR DMAR translation is not disabled.
309 **/
310 EFI_STATUS
311 DisableDmar (
312 VOID
313 )
314 {
315 UINTN Index;
316 UINTN SubIndex;
317 UINT32 Reg32;
318
319 for (Index = 0; Index < mVtdUnitNumber; Index++) {
320 DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index));
321
322 //
323 // Write Buffer Flush before invalidation
324 //
325 FlushWriteBuffer (Index);
326
327 //
328 // Disable VTd
329 //
330 MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);
331 do {
332 Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
333 } while((Reg32 & B_GSTS_REG_RTPS) == 0);
334
335 Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
336 DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32));
337
338 DEBUG ((DEBUG_INFO,"VTD (%d) Disabled!<<<<<<\n",Index));
339 }
340
341 mVtdEnabled = FALSE;
342
343 for (Index = 0; Index < mVtdUnitNumber; Index++) {
344 DEBUG((DEBUG_INFO, "engine [%d] access\n", Index));
345 for (SubIndex = 0; SubIndex < mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber; SubIndex++) {
346 DEBUG ((DEBUG_INFO, " PCI S%04X B%02x D%02x F%02x - %d\n",
347 mVtdUnitInformation[Index].Segment,
348 mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciSourceId.Bits.Bus,
349 mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciSourceId.Bits.Device,
350 mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciSourceId.Bits.Function,
351 mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].AccessCount
352 ));
353 }
354 }
355
356 return EFI_SUCCESS;
357 }
358
359 /**
360 Dump VTd capability registers.
361
362 @param[in] CapReg The capability register.
363 **/
364 VOID
365 DumpVtdCapRegs (
366 IN VTD_CAP_REG *CapReg
367 )
368 {
369 DEBUG((DEBUG_INFO, " CapReg:\n", CapReg->Uint64));
370 DEBUG((DEBUG_INFO, " ND - 0x%x\n", CapReg->Bits.ND));
371 DEBUG((DEBUG_INFO, " AFL - 0x%x\n", CapReg->Bits.AFL));
372 DEBUG((DEBUG_INFO, " RWBF - 0x%x\n", CapReg->Bits.RWBF));
373 DEBUG((DEBUG_INFO, " PLMR - 0x%x\n", CapReg->Bits.PLMR));
374 DEBUG((DEBUG_INFO, " PHMR - 0x%x\n", CapReg->Bits.PHMR));
375 DEBUG((DEBUG_INFO, " CM - 0x%x\n", CapReg->Bits.CM));
376 DEBUG((DEBUG_INFO, " SAGAW - 0x%x\n", CapReg->Bits.SAGAW));
377 DEBUG((DEBUG_INFO, " MGAW - 0x%x\n", CapReg->Bits.MGAW));
378 DEBUG((DEBUG_INFO, " ZLR - 0x%x\n", CapReg->Bits.ZLR));
379 DEBUG((DEBUG_INFO, " FRO - 0x%x\n", CapReg->Bits.FRO));
380 DEBUG((DEBUG_INFO, " SLLPS - 0x%x\n", CapReg->Bits.SLLPS));
381 DEBUG((DEBUG_INFO, " PSI - 0x%x\n", CapReg->Bits.PSI));
382 DEBUG((DEBUG_INFO, " NFR - 0x%x\n", CapReg->Bits.NFR));
383 DEBUG((DEBUG_INFO, " MAMV - 0x%x\n", CapReg->Bits.MAMV));
384 DEBUG((DEBUG_INFO, " DWD - 0x%x\n", CapReg->Bits.DWD));
385 DEBUG((DEBUG_INFO, " DRD - 0x%x\n", CapReg->Bits.DRD));
386 DEBUG((DEBUG_INFO, " FL1GP - 0x%x\n", CapReg->Bits.FL1GP));
387 DEBUG((DEBUG_INFO, " PI - 0x%x\n", CapReg->Bits.PI));
388 }
389
390 /**
391 Dump VTd extended capability registers.
392
393 @param[in] ECapReg The extended capability register.
394 **/
395 VOID
396 DumpVtdECapRegs (
397 IN VTD_ECAP_REG *ECapReg
398 )
399 {
400 DEBUG((DEBUG_INFO, " ECapReg:\n", ECapReg->Uint64));
401 DEBUG((DEBUG_INFO, " C - 0x%x\n", ECapReg->Bits.C));
402 DEBUG((DEBUG_INFO, " QI - 0x%x\n", ECapReg->Bits.QI));
403 DEBUG((DEBUG_INFO, " DT - 0x%x\n", ECapReg->Bits.DT));
404 DEBUG((DEBUG_INFO, " IR - 0x%x\n", ECapReg->Bits.IR));
405 DEBUG((DEBUG_INFO, " EIM - 0x%x\n", ECapReg->Bits.EIM));
406 DEBUG((DEBUG_INFO, " PT - 0x%x\n", ECapReg->Bits.PT));
407 DEBUG((DEBUG_INFO, " SC - 0x%x\n", ECapReg->Bits.SC));
408 DEBUG((DEBUG_INFO, " IRO - 0x%x\n", ECapReg->Bits.IRO));
409 DEBUG((DEBUG_INFO, " MHMV - 0x%x\n", ECapReg->Bits.MHMV));
410 DEBUG((DEBUG_INFO, " ECS - 0x%x\n", ECapReg->Bits.ECS));
411 DEBUG((DEBUG_INFO, " MTS - 0x%x\n", ECapReg->Bits.MTS));
412 DEBUG((DEBUG_INFO, " NEST - 0x%x\n", ECapReg->Bits.NEST));
413 DEBUG((DEBUG_INFO, " DIS - 0x%x\n", ECapReg->Bits.DIS));
414 DEBUG((DEBUG_INFO, " PASID - 0x%x\n", ECapReg->Bits.PASID));
415 DEBUG((DEBUG_INFO, " PRS - 0x%x\n", ECapReg->Bits.PRS));
416 DEBUG((DEBUG_INFO, " ERS - 0x%x\n", ECapReg->Bits.ERS));
417 DEBUG((DEBUG_INFO, " SRS - 0x%x\n", ECapReg->Bits.SRS));
418 DEBUG((DEBUG_INFO, " NWFS - 0x%x\n", ECapReg->Bits.NWFS));
419 DEBUG((DEBUG_INFO, " EAFS - 0x%x\n", ECapReg->Bits.EAFS));
420 DEBUG((DEBUG_INFO, " PSS - 0x%x\n", ECapReg->Bits.PSS));
421 }
422
423 /**
424 Dump VTd registers.
425
426 @param[in] VtdIndex The index of VTd engine.
427 **/
428 VOID
429 DumpVtdRegs (
430 IN UINTN VtdIndex
431 )
432 {
433 UINTN Index;
434 UINT64 Reg64;
435 VTD_FRCD_REG FrcdReg;
436 VTD_CAP_REG CapReg;
437 UINT32 Reg32;
438 VTD_SOURCE_ID SourceId;
439
440 DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) Begin ####\n", VtdIndex));
441
442 Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_VER_REG);
443 DEBUG((DEBUG_INFO, " VER_REG - 0x%08x\n", Reg32));
444
445 CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CAP_REG);
446 DEBUG((DEBUG_INFO, " CAP_REG - 0x%016lx\n", CapReg.Uint64));
447
448 Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_ECAP_REG);
449 DEBUG((DEBUG_INFO, " ECAP_REG - 0x%016lx\n", Reg64));
450
451 Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
452 DEBUG((DEBUG_INFO, " GSTS_REG - 0x%08x \n", Reg32));
453
454 Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_RTADDR_REG);
455 DEBUG((DEBUG_INFO, " RTADDR_REG - 0x%016lx\n", Reg64));
456
457 Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);
458 DEBUG((DEBUG_INFO, " CCMD_REG - 0x%016lx\n", Reg64));
459
460 Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FSTS_REG);
461 DEBUG((DEBUG_INFO, " FSTS_REG - 0x%08x\n", Reg32));
462
463 Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FECTL_REG);
464 DEBUG((DEBUG_INFO, " FECTL_REG - 0x%08x\n", Reg32));
465
466 Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEDATA_REG);
467 DEBUG((DEBUG_INFO, " FEDATA_REG - 0x%08x\n", Reg32));
468
469 Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEADDR_REG);
470 DEBUG((DEBUG_INFO, " FEADDR_REG - 0x%08x\n",Reg32));
471
472 Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEUADDR_REG);
473 DEBUG((DEBUG_INFO, " FEUADDR_REG - 0x%08x\n",Reg32));
474
475 for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
476 FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));
477 FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
478 DEBUG((DEBUG_INFO, " FRCD_REG[%d] - 0x%016lx %016lx\n", Index, FrcdReg.Uint64[1], FrcdReg.Uint64[0]));
479 if (FrcdReg.Uint64[1] != 0 || FrcdReg.Uint64[0] != 0) {
480 DEBUG((DEBUG_INFO, " Fault Info - 0x%016lx\n", VTD_64BITS_ADDRESS(FrcdReg.Bits.FILo, FrcdReg.Bits.FIHi)));
481 SourceId.Uint16 = (UINT16)FrcdReg.Bits.SID;
482 DEBUG((DEBUG_INFO, " Source - B%02x D%02x F%02x\n", SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
483 DEBUG((DEBUG_INFO, " Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.Bits.T ? "read" : "write"));
484 DEBUG((DEBUG_INFO, " Reason - %x (Refer to VTd Spec, Appendix A)\n", FrcdReg.Bits.FR));
485 }
486 }
487
488 Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IVA_REG);
489 DEBUG((DEBUG_INFO, " IVA_REG - 0x%016lx\n",Reg64));
490
491 Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);
492 DEBUG((DEBUG_INFO, " IOTLB_REG - 0x%016lx\n",Reg64));
493
494 DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) End ####\n", VtdIndex));
495 }
496
497 /**
498 Dump VTd registers for all VTd engine.
499 **/
500 VOID
501 DumpVtdRegsAll (
502 VOID
503 )
504 {
505 UINTN Num;
506
507 for (Num = 0; Num < mVtdUnitNumber; Num++) {
508 DumpVtdRegs (Num);
509 }
510 }
511
512 /**
513 Dump VTd registers if there is error.
514 **/
515 VOID
516 DumpVtdIfError (
517 VOID
518 )
519 {
520 UINTN Num;
521 UINTN Index;
522 VTD_FRCD_REG FrcdReg;
523 VTD_CAP_REG CapReg;
524 UINT32 Reg32;
525 BOOLEAN HasError;
526
527 for (Num = 0; Num < mVtdUnitNumber; Num++) {
528 HasError = FALSE;
529 Reg32 = MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG);
530 if (Reg32 != 0) {
531 HasError = TRUE;
532 }
533 Reg32 = MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FECTL_REG);
534 if ((Reg32 & BIT30) != 0) {
535 HasError = TRUE;
536 }
537
538 CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_CAP_REG);
539 for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
540 FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));
541 FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
542 if (FrcdReg.Bits.F != 0) {
543 HasError = TRUE;
544 }
545 }
546
547 if (HasError) {
548 DEBUG((DEBUG_INFO, "\n#### ERROR ####\n"));
549 DumpVtdRegs (Num);
550 DEBUG((DEBUG_INFO, "#### ERROR ####\n\n"));
551 //
552 // Clear
553 //
554 for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
555 FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
556 if (FrcdReg.Bits.F != 0) {
557 FrcdReg.Bits.F = 0;
558 MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), FrcdReg.Uint64[1]);
559 }
560 MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG));
561 }
562 }
563 }
564 }