IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h

   1 /** @file
   2   IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
   3   Specification.
   4
   5   https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
   6
   7   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   8   This program and the accompanying materials
   9   are licensed and made available under the terms and conditions of the BSD License
  10   which accompanies this distribution.  The full text of the license may be found at
  11   http://opensource.org/licenses/bsd-license.php
  12
  13   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 **/
  17 #ifndef _IGD_OPREGION_H_
  18 #define _IGD_OPREGION_H_
  19
  20 #define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem"
  21 #define IGD_OPREGION_HEADER_MBOX1 BIT0
  22 #define IGD_OPREGION_HEADER_MBOX2 BIT1
  23 #define IGD_OPREGION_HEADER_MBOX3 BIT2
  24 #define IGD_OPREGION_HEADER_MBOX4 BIT3
  25 #define IGD_OPREGION_HEADER_MBOX5 BIT4
  26
  27 /**
  28   OpRegion structures:
  29   Sub-structures define the different parts of the OpRegion followed by the
  30   main structure representing the entire OpRegion.
  31
  32   @note: These structures are packed to 1 byte offsets because the exact
  33   data location is required by the supporting design specification due to
  34   the fact that the data is used by ASL and Graphics driver code compiled
  35   separately.
  36 **/
  37 #pragma pack(1)
  38 ///
  39 /// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to
  40 /// identify a block of memory as the graphics driver OpRegion.
  41 /// Offset 0x0, Size 0x100
  42 ///
  43 typedef struct {
  44   CHAR8  SIGN[0x10];    ///< Offset 0x00 OpRegion Signature
  45   UINT32 SIZE;          ///< Offset 0x10 OpRegion Size
  46   UINT32 OVER;          ///< Offset 0x14 OpRegion Structure Version
  47   UINT8  SVER[0x20];    ///< Offset 0x18 System BIOS Build Version
  48   UINT8  VVER[0x10];    ///< Offset 0x38 Video BIOS Build Version
  49   UINT8  GVER[0x10];    ///< Offset 0x48 Graphic Driver Build Version
  50   UINT32 MBOX;          ///< Offset 0x58 Supported Mailboxes
  51   UINT32 DMOD;          ///< Offset 0x5C Driver Model
  52   UINT32 PCON;          ///< Offset 0x60 Platform Configuration
  53   CHAR16 DVER[0x10]     ///< Offset 0x64 GOP Version
  54   UINT8  RM01[0x7C];    ///< Offset 0x84 Reserved Must be zero
  55 } IGD_OPREGION_HEADER;
  56
  57 ///
  58 /// OpRegion Mailbox 1 - Public ACPI Methods
  59 /// Offset 0x100, Size 0x100
  60 ///
  61 typedef struct {
  62   UINT32 DRDY;          ///< Offset 0x100 Driver Readiness
  63   UINT32 CSTS;          ///< Offset 0x104 Status
  64   UINT32 CEVT;          ///< Offset 0x108 Current Event
  65   UINT8  RM11[0x14];    ///< Offset 0x10C Reserved Must be Zero
  66   UINT32 DIDL[8];       ///< Offset 0x120 Supported Display Devices ID List
  67   UINT32 CPDL[8];       ///< Offset 0x140 Currently Attached Display Devices List
  68   UINT32 CADL[8];       ///< Offset 0x160 Currently Active Display Devices List
  69   UINT32 NADL[8];       ///< Offset 0x180 Next Active Devices List
  70   UINT32 ASLP;          ///< Offset 0x1A0 ASL Sleep Time Out
  71   UINT32 TIDX;          ///< Offset 0x1A4 Toggle Table Index
  72   UINT32 CHPD;          ///< Offset 0x1A8 Current Hotplug Enable Indicator
  73   UINT32 CLID;          ///< Offset 0x1AC Current Lid State Indicator
  74   UINT32 CDCK;          ///< Offset 0x1B0 Current Docking State Indicator
  75   UINT32 SXSW;          ///< Offset 0x1B4 Display Switch Notification on Sx State Resume
  76   UINT32 EVTS;          ///< Offset 0x1B8 Events supported by ASL
  77   UINT32 CNOT;          ///< Offset 0x1BC Current OS Notification
  78   UINT32 NRDY;          ///< Offset 0x1C0 Driver Status
  79   UINT8  DID2[0x1C];    ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)
  80   UINT8  CPD2[0x1C];    ///< Offset 0x1E0 Extended Attached Display Devices List
  81   UINT8  RM12[4];       ///< Offset 0x1FC - 0x1FF Reserved Must be zero
  82 } IGD_OPREGION_MBOX1;
  83
  84 ///
  85 /// OpRegion Mailbox 2 - Software SCI Interface
  86 /// Offset 0x200, Size 0x100
  87 ///
  88 typedef struct {
  89   UINT32 SCIC;          ///< Offset 0x200 Software SCI Command / Status / Data
  90   UINT32 PARM;          ///< Offset 0x204 Software SCI Parameters
  91   UINT32 DSLP;          ///< Offset 0x208 Driver Sleep Time Out
  92   UINT8  RM21[0xF4];    ///< Offset 0x20C - 0x2FF Reserved Must be zero
  93 } IGD_OPREGION_MBOX2;
  94
  95 ///
  96 /// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support
  97 /// Offset 0x300, Size 0x100
  98 ///
  99 typedef struct {
 100   UINT32 ARDY;          ///< Offset 0x300 Driver Readiness
 101   UINT32 ASLC;          ///< Offset 0x304 ASLE Interrupt Command / Status
 102   UINT32 TCHE;          ///< Offset 0x308 Technology Enabled Indicator
 103   UINT32 ALSI;          ///< Offset 0x30C Current ALS Luminance Reading
 104   UINT32 BCLP;          ///< Offset 0x310 Requested Backlight Brightness
 105   UINT32 PFIT;          ///< Offset 0x314 Panel Fitting State or Request
 106   UINT32 CBLV;          ///< Offset 0x318 Current Brightness Level
 107   UINT16 BCLM[0x14];    ///< Offset 0x31C Backlight Brightness Levels Duty Cycle Mapping Table
 108   UINT32 CPFM;          ///< Offset 0x344 Current Panel Fitting Mode
 109   UINT32 EPFM;          ///< Offset 0x348 Enabled Panel Fitting Modes
 110   UINT8  PLUT[0x4A];    ///< Offset 0x34C Panel Look Up Table & Identifier
 111   UINT32 PFMB;          ///< Offset 0x396 PWM Frequency and Minimum Brightness
 112   UINT32 CCDV;          ///< Offset 0x39A Color Correction Default Values
 113   UINT32 PCFT;          ///< Offset 0x39E Power Conservation Features
 114   UINT32 SROT;          ///< Offset 0x3A2 Supported Rotation Angles
 115   UINT32 IUER;          ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register
 116   UINT64 FDSS;          ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature
 117   UINT32 FDSP;          ///< Offset 0x3B2 Size of DSS buffer
 118   UINT32 STAT;          ///< Offset 0x3B6 State Indicator
 119   UINT8  RM31[0x45];    ///< Offset 0x3BA - 0x3FF  Reserved Must be zero
 120 } IGD_OPREGION_MBOX3;
 121
 122 ///
 123 /// OpRegion Mailbox 4 - VBT Video BIOS Table
 124 /// Offset 0x400, Size 0x1800
 125 ///
 126 typedef struct {
 127   UINT8  RVBT[0x1800];  ///< Offset 0x400 - 0x1BFF Raw VBT Data
 128 } IGD_OPREGION_MBOX4;
 129
 130 ///
 131 /// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync
 132 /// Offset 0x1C00, Size 0x400
 133 ///
 134 typedef struct {
 135   UINT32 PHED;          ///< Offset 0x1C00 Panel Header
 136   UINT8  BDDC[0x100];   ///< Offset 0x1C04 Panel EDID (DDC data)
 137   UINT8  RM51[0x2FC];   ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero
 138 } IGD_OPREGION_MBOX5;
 139
 140 ///
 141 /// IGD OpRegion Structure
 142 ///
 143 typedef struct {
 144   IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)
 145   IGD_OPREGION_MBOX1  MBox1;  ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100)
 146   IGD_OPREGION_MBOX2  MBox2;  ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)
 147   IGD_OPREGION_MBOX3  MBox3;  ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)
 148   IGD_OPREGION_MBOX4  MBox4;  ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)
 149   IGD_OPREGION_MBOX5  MBox5;  ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)
 150 } IGD_OPREGION_STRUCTURE;
 151 #pragma pack()
 152
 153 #endif