IntelSiliconPkg/IntelVTdDxe/VtdReg.c

   1 /** @file
   2
   3   Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
   4   This program and the accompanying materials
   5   are licensed and made available under the terms and conditions of the BSD License
   6   which accompanies this distribution.  The full text of the license may be found at
   7   http://opensource.org/licenses/bsd-license.php.
   8
   9   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 **/
  13
  14 #include "DmaProtection.h"
  15
  16 UINT64                           mVtdHostAddressWidthMask;
  17 UINTN                            mVtdUnitNumber;
  18 VTD_UNIT_INFORMATION             *mVtdUnitInformation;
  19
  20 BOOLEAN  mVtdEnabled;
  21
  22 /**
  23   Flush VTD page table and context table memory.
  24
  25   This action is to make sure the IOMMU engine can get final data in memory.
  26
  27   @param[in]  VtdIndex          The index used to identify a VTd engine.
  28   @param[in]  Base              The base address of memory to be flushed.
  29   @param[in]  Size              The size of memory in bytes to be flushed.
  30 **/
  31 VOID
  32 FlushPageTableMemory (
  33   IN UINTN  VtdIndex,
  34   IN UINTN  Base,
  35   IN UINTN  Size
  36   )
  37 {
  38   if (mVtdUnitInformation[VtdIndex].ECapReg.Bits.C == 0) {
  39     WriteBackDataCacheRange ((VOID *)Base, Size);
  40   }
  41 }
  42
  43 /**
  44   Flush VTd engine write buffer.
  45
  46   @param[in]  VtdIndex          The index used to identify a VTd engine.
  47 **/
  48 VOID
  49 FlushWriteBuffer (
  50   IN UINTN  VtdIndex
  51   )
  52 {
  53   UINT32  Reg32;
  54
  55   if (mVtdUnitInformation[VtdIndex].CapReg.Bits.RWBF != 0) {
  56     Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
  57     MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_WBF);
  58     do {
  59       Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
  60     } while ((Reg32 & B_GSTS_REG_WBF) != 0);
  61   }
  62 }
  63
  64 /**
  65   Invalidate VTd context cache.
  66
  67   @param[in]  VtdIndex          The index used to identify a VTd engine.
  68 **/
  69 EFI_STATUS
  70 InvalidateContextCache (
  71   IN UINTN  VtdIndex
  72   )
  73 {
  74   UINT64  Reg64;
  75
  76   Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);
  77   if ((Reg64 & B_CCMD_REG_ICC) != 0) {
  78     DEBUG ((DEBUG_ERROR,"ERROR: InvalidateContextCache: B_CCMD_REG_ICC is set for VTD(%d)\n",VtdIndex));
  79     return EFI_DEVICE_ERROR;
  80   }
  81
  82   Reg64 &= ((~B_CCMD_REG_ICC) & (~B_CCMD_REG_CIRG_MASK));
  83   Reg64 |= (B_CCMD_REG_ICC | V_CCMD_REG_CIRG_GLOBAL);
  84   MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG, Reg64);
  85
  86   do {
  87     Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);
  88   } while ((Reg64 & B_CCMD_REG_ICC) != 0);
  89
  90   return EFI_SUCCESS;
  91 }
  92
  93 /**
  94   Invalidate VTd IOTLB.
  95
  96   @param[in]  VtdIndex          The index used to identify a VTd engine.
  97 **/
  98 EFI_STATUS
  99 InvalidateIOTLB (
 100   IN UINTN  VtdIndex
 101   )
 102 {
 103   UINT64  Reg64;
 104
 105   Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);
 106   if ((Reg64 & B_IOTLB_REG_IVT) != 0) {
 107     DEBUG ((DEBUG_ERROR,"ERROR: InvalidateIOTLB: B_IOTLB_REG_IVT is set for VTD(%d)\n", VtdIndex));
 108     return EFI_DEVICE_ERROR;
 109   }
 110
 111   Reg64 &= ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK));
 112   Reg64 |= (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_GLOBAL);
 113   MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG, Reg64);
 114
 115   do {
 116     Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);
 117   } while ((Reg64 & B_IOTLB_REG_IVT) != 0);
 118
 119   return EFI_SUCCESS;
 120 }
 121
 122 /**
 123   Invalid VTd global IOTLB.
 124
 125   @param[in]  VtdIndex              The index of VTd engine.
 126
 127   @retval EFI_SUCCESS           VTd global IOTLB is invalidated.
 128   @retval EFI_DEVICE_ERROR      VTd global IOTLB is not invalidated.
 129 **/
 130 EFI_STATUS
 131 InvalidateVtdIOTLBGlobal (
 132   IN UINTN  VtdIndex
 133   )
 134 {
 135   if (!mVtdEnabled) {
 136     return EFI_SUCCESS;
 137   }
 138
 139   DEBUG((DEBUG_VERBOSE, "InvalidateVtdIOTLBGlobal(%d)\n", VtdIndex));
 140
 141   //
 142   // Write Buffer Flush before invalidation
 143   //
 144   FlushWriteBuffer (VtdIndex);
 145
 146   //
 147   // Invalidate the context cache
 148   //
 149   if (mVtdUnitInformation[VtdIndex].HasDirtyContext) {
 150     InvalidateContextCache (VtdIndex);
 151   }
 152
 153   //
 154   // Invalidate the IOTLB cache
 155   //
 156   if (mVtdUnitInformation[VtdIndex].HasDirtyContext || mVtdUnitInformation[VtdIndex].HasDirtyPages) {
 157     InvalidateIOTLB (VtdIndex);
 158   }
 159
 160   return EFI_SUCCESS;
 161 }
 162
 163 /**
 164   Prepare VTD configuration.
 165 **/
 166 VOID
 167 PrepareVtdConfig (
 168   VOID
 169   )
 170 {
 171   UINTN         Index;
 172   UINTN         DomainNumber;
 173
 174   for (Index = 0; Index < mVtdUnitNumber; Index++) {
 175     DEBUG ((DEBUG_INFO, "Dump VTd Capability (%d)\n", Index));
 176     mVtdUnitInformation[Index].CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);
 177     DumpVtdCapRegs (&mVtdUnitInformation[Index].CapReg);
 178     mVtdUnitInformation[Index].ECapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_ECAP_REG);
 179     DumpVtdECapRegs (&mVtdUnitInformation[Index].ECapReg);
 180
 181     if ((mVtdUnitInformation[Index].CapReg.Bits.SLLPS & BIT0) == 0) {
 182       DEBUG((DEBUG_WARN, "!!!! 2MB super page is not supported on VTD %d !!!!\n", Index));
 183     }
 184     if ((mVtdUnitInformation[Index].CapReg.Bits.SAGAW & BIT2) == 0) {
 185       DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", Index));
 186       return ;
 187     }
 188
 189     DomainNumber = (UINTN)1 << (UINT8)((UINTN)mVtdUnitInformation[Index].CapReg.Bits.ND * 2 + 4);
 190     if (mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber >= DomainNumber) {
 191       DEBUG((DEBUG_ERROR, "!!!! Pci device Number(0x%x) >= DomainNumber(0x%x) !!!!\n", mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber, DomainNumber));
 192       return ;
 193     }
 194   }
 195   return ;
 196 }
 197
 198 /**
 199   Disable PMR in all VTd engine.
 200 **/
 201 VOID
 202 DisablePmr (
 203   VOID
 204   )
 205 {
 206   UINT32        Reg32;
 207   VTD_CAP_REG   CapReg;
 208   UINTN         Index;
 209
 210   DEBUG ((DEBUG_INFO,"DisablePmr\n"));
 211   for (Index = 0; Index < mVtdUnitNumber; Index++) {
 212     CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);
 213     if (CapReg.Bits.PLMR == 0 || CapReg.Bits.PHMR == 0) {
 214       continue ;
 215     }
 216
 217     Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
 218     if ((Reg32 & BIT0) != 0) {
 219       MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG, 0x0);
 220       do {
 221         Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
 222       } while((Reg32 & BIT0) != 0);
 223       DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index));
 224     } else {
 225       DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index));
 226     }
 227   }
 228   return ;
 229 }
 230
 231 /**
 232   Enable DMAR translation.
 233
 234   @retval EFI_SUCCESS           DMAR translation is enabled.
 235   @retval EFI_DEVICE_ERROR      DMAR translation is not enabled.
 236 **/
 237 EFI_STATUS
 238 EnableDmar (
 239   VOID
 240   )
 241 {
 242   UINTN     Index;
 243   UINT32    Reg32;
 244
 245   for (Index = 0; Index < mVtdUnitNumber; Index++) {
 246     DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] \n", Index));
 247
 248     if (mVtdUnitInformation[Index].ExtRootEntryTable != NULL) {
 249       DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[Index].ExtRootEntryTable));
 250       MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].ExtRootEntryTable | BIT11);
 251     } else {
 252       DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[Index].RootEntryTable));
 253       MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].RootEntryTable);
 254     }
 255
 256     MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);
 257
 258     DEBUG((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n"));
 259     do {
 260       Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
 261     } while((Reg32 & B_GSTS_REG_RTPS) == 0);
 262
 263     //
 264     // Init DMAr Fault Event and Data registers
 265     //
 266     Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_FEDATA_REG);
 267
 268     //
 269     // Write Buffer Flush before invalidation
 270     //
 271     FlushWriteBuffer (Index);
 272
 273     //
 274     // Invalidate the context cache
 275     //
 276     InvalidateContextCache (Index);
 277
 278     //
 279     // Invalidate the IOTLB cache
 280     //
 281     InvalidateIOTLB (Index);
 282
 283     //
 284     // Enable VTd
 285     //
 286     MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_TE);
 287     DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n"));
 288     do {
 289       Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
 290     } while ((Reg32 & B_GSTS_REG_TE) == 0);
 291
 292     DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index));
 293   }
 294
 295   //
 296   // Need disable PMR, since we already setup translation table.
 297   //
 298   DisablePmr ();
 299
 300   mVtdEnabled = TRUE;
 301
 302   return EFI_SUCCESS;
 303 }
 304
 305 /**
 306   Disable DMAR translation.
 307
 308   @retval EFI_SUCCESS           DMAR translation is disabled.
 309   @retval EFI_DEVICE_ERROR      DMAR translation is not disabled.
 310 **/
 311 EFI_STATUS
 312 DisableDmar (
 313   VOID
 314   )
 315 {
 316   UINTN     Index;
 317   UINTN     SubIndex;
 318   UINT32    Reg32;
 319
 320   for (Index = 0; Index < mVtdUnitNumber; Index++) {
 321     DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index));
 322
 323     //
 324     // Write Buffer Flush before invalidation
 325     //
 326     FlushWriteBuffer (Index);
 327
 328     //
 329     // Disable VTd
 330     //
 331     MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);
 332     do {
 333       Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
 334     } while((Reg32 & B_GSTS_REG_RTPS) == 0);
 335
 336     Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
 337     DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32));
 338
 339     DEBUG ((DEBUG_INFO,"VTD (%d) Disabled!<<<<<<\n",Index));
 340   }
 341
 342   mVtdEnabled = FALSE;
 343
 344   for (Index = 0; Index < mVtdUnitNumber; Index++) {
 345     DEBUG((DEBUG_INFO, "engine [%d] access\n", Index));
 346     for (SubIndex = 0; SubIndex < mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber; SubIndex++) {
 347       DEBUG ((DEBUG_INFO, "  PCI S%04X B%02x D%02x F%02x - %d\n",
 348         mVtdUnitInformation[Index].Segment,
 349         mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciSourceId.Bits.Bus,
 350         mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciSourceId.Bits.Device,
 351         mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciSourceId.Bits.Function,
 352         mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].AccessCount
 353         ));
 354     }
 355   }
 356
 357   return EFI_SUCCESS;
 358 }
 359
 360 /**
 361   Dump VTd capability registers.
 362
 363   @param[in]  CapReg              The capability register.
 364 **/
 365 VOID
 366 DumpVtdCapRegs (
 367   IN VTD_CAP_REG *CapReg
 368   )
 369 {
 370   DEBUG((DEBUG_INFO, "  CapReg:\n", CapReg->Uint64));
 371   DEBUG((DEBUG_INFO, "    ND     - 0x%x\n", CapReg->Bits.ND));
 372   DEBUG((DEBUG_INFO, "    AFL    - 0x%x\n", CapReg->Bits.AFL));
 373   DEBUG((DEBUG_INFO, "    RWBF   - 0x%x\n", CapReg->Bits.RWBF));
 374   DEBUG((DEBUG_INFO, "    PLMR   - 0x%x\n", CapReg->Bits.PLMR));
 375   DEBUG((DEBUG_INFO, "    PHMR   - 0x%x\n", CapReg->Bits.PHMR));
 376   DEBUG((DEBUG_INFO, "    CM     - 0x%x\n", CapReg->Bits.CM));
 377   DEBUG((DEBUG_INFO, "    SAGAW  - 0x%x\n", CapReg->Bits.SAGAW));
 378   DEBUG((DEBUG_INFO, "    MGAW   - 0x%x\n", CapReg->Bits.MGAW));
 379   DEBUG((DEBUG_INFO, "    ZLR    - 0x%x\n", CapReg->Bits.ZLR));
 380   DEBUG((DEBUG_INFO, "    FRO    - 0x%x\n", CapReg->Bits.FRO));
 381   DEBUG((DEBUG_INFO, "    SLLPS  - 0x%x\n", CapReg->Bits.SLLPS));
 382   DEBUG((DEBUG_INFO, "    PSI    - 0x%x\n", CapReg->Bits.PSI));
 383   DEBUG((DEBUG_INFO, "    NFR    - 0x%x\n", CapReg->Bits.NFR));
 384   DEBUG((DEBUG_INFO, "    MAMV   - 0x%x\n", CapReg->Bits.MAMV));
 385   DEBUG((DEBUG_INFO, "    DWD    - 0x%x\n", CapReg->Bits.DWD));
 386   DEBUG((DEBUG_INFO, "    DRD    - 0x%x\n", CapReg->Bits.DRD));
 387   DEBUG((DEBUG_INFO, "    FL1GP  - 0x%x\n", CapReg->Bits.FL1GP));
 388   DEBUG((DEBUG_INFO, "    PI     - 0x%x\n", CapReg->Bits.PI));
 389 }
 390
 391 /**
 392   Dump VTd extended capability registers.
 393
 394   @param[in]  ECapReg              The extended capability register.
 395 **/
 396 VOID
 397 DumpVtdECapRegs (
 398   IN VTD_ECAP_REG *ECapReg
 399   )
 400 {
 401   DEBUG((DEBUG_INFO, "  ECapReg:\n", ECapReg->Uint64));
 402   DEBUG((DEBUG_INFO, "    C      - 0x%x\n", ECapReg->Bits.C));
 403   DEBUG((DEBUG_INFO, "    QI     - 0x%x\n", ECapReg->Bits.QI));
 404   DEBUG((DEBUG_INFO, "    DT     - 0x%x\n", ECapReg->Bits.DT));
 405   DEBUG((DEBUG_INFO, "    IR     - 0x%x\n", ECapReg->Bits.IR));
 406   DEBUG((DEBUG_INFO, "    EIM    - 0x%x\n", ECapReg->Bits.EIM));
 407   DEBUG((DEBUG_INFO, "    PT     - 0x%x\n", ECapReg->Bits.PT));
 408   DEBUG((DEBUG_INFO, "    SC     - 0x%x\n", ECapReg->Bits.SC));
 409   DEBUG((DEBUG_INFO, "    IRO    - 0x%x\n", ECapReg->Bits.IRO));
 410   DEBUG((DEBUG_INFO, "    MHMV   - 0x%x\n", ECapReg->Bits.MHMV));
 411   DEBUG((DEBUG_INFO, "    ECS    - 0x%x\n", ECapReg->Bits.ECS));
 412   DEBUG((DEBUG_INFO, "    MTS    - 0x%x\n", ECapReg->Bits.MTS));
 413   DEBUG((DEBUG_INFO, "    NEST   - 0x%x\n", ECapReg->Bits.NEST));
 414   DEBUG((DEBUG_INFO, "    DIS    - 0x%x\n", ECapReg->Bits.DIS));
 415   DEBUG((DEBUG_INFO, "    PASID  - 0x%x\n", ECapReg->Bits.PASID));
 416   DEBUG((DEBUG_INFO, "    PRS    - 0x%x\n", ECapReg->Bits.PRS));
 417   DEBUG((DEBUG_INFO, "    ERS    - 0x%x\n", ECapReg->Bits.ERS));
 418   DEBUG((DEBUG_INFO, "    SRS    - 0x%x\n", ECapReg->Bits.SRS));
 419   DEBUG((DEBUG_INFO, "    NWFS   - 0x%x\n", ECapReg->Bits.NWFS));
 420   DEBUG((DEBUG_INFO, "    EAFS   - 0x%x\n", ECapReg->Bits.EAFS));
 421   DEBUG((DEBUG_INFO, "    PSS    - 0x%x\n", ECapReg->Bits.PSS));
 422 }
 423
 424 /**
 425   Dump VTd registers.
 426
 427   @param[in]  VtdIndex              The index of VTd engine.
 428 **/
 429 VOID
 430 DumpVtdRegs (
 431   IN UINTN  VtdIndex
 432   )
 433 {
 434   UINTN         Index;
 435   UINT64        Reg64;
 436   VTD_FRCD_REG  FrcdReg;
 437   VTD_CAP_REG   CapReg;
 438   UINT32        Reg32;
 439   VTD_SOURCE_ID SourceId;
 440
 441   DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) Begin ####\n", VtdIndex));
 442
 443   Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_VER_REG);
 444   DEBUG((DEBUG_INFO, "  VER_REG     - 0x%08x\n", Reg32));
 445
 446   CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CAP_REG);
 447   DEBUG((DEBUG_INFO, "  CAP_REG     - 0x%016lx\n", CapReg.Uint64));
 448
 449   Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_ECAP_REG);
 450   DEBUG((DEBUG_INFO, "  ECAP_REG    - 0x%016lx\n", Reg64));
 451
 452   Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
 453   DEBUG((DEBUG_INFO, "  GSTS_REG    - 0x%08x \n", Reg32));
 454
 455   Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_RTADDR_REG);
 456   DEBUG((DEBUG_INFO, "  RTADDR_REG  - 0x%016lx\n", Reg64));
 457
 458   Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);
 459   DEBUG((DEBUG_INFO, "  CCMD_REG    - 0x%016lx\n", Reg64));
 460
 461   Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FSTS_REG);
 462   DEBUG((DEBUG_INFO, "  FSTS_REG    - 0x%08x\n", Reg32));
 463
 464   Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FECTL_REG);
 465   DEBUG((DEBUG_INFO, "  FECTL_REG   - 0x%08x\n", Reg32));
 466
 467   Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEDATA_REG);
 468   DEBUG((DEBUG_INFO, "  FEDATA_REG  - 0x%08x\n", Reg32));
 469
 470   Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEADDR_REG);
 471   DEBUG((DEBUG_INFO, "  FEADDR_REG  - 0x%08x\n",Reg32));
 472
 473   Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEUADDR_REG);
 474   DEBUG((DEBUG_INFO, "  FEUADDR_REG - 0x%08x\n",Reg32));
 475
 476   for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
 477     FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));
 478     FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
 479     DEBUG((DEBUG_INFO, "  FRCD_REG[%d] - 0x%016lx %016lx\n", Index, FrcdReg.Uint64[1], FrcdReg.Uint64[0]));
 480     if (FrcdReg.Uint64[1] != 0 || FrcdReg.Uint64[0] != 0) {
 481       DEBUG((DEBUG_INFO, "    Fault Info - 0x%016lx\n", VTD_64BITS_ADDRESS(FrcdReg.Bits.FILo, FrcdReg.Bits.FIHi)));
 482       SourceId.Uint16 = (UINT16)FrcdReg.Bits.SID;
 483       DEBUG((DEBUG_INFO, "    Source - B%02x D%02x F%02x\n", SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
 484       DEBUG((DEBUG_INFO, "    Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.Bits.T ? "read" : "write"));
 485       DEBUG((DEBUG_INFO, "    Reason - %x\n", FrcdReg.Bits.FR));
 486     }
 487   }
 488
 489   Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IVA_REG);
 490   DEBUG((DEBUG_INFO, "  IVA_REG     - 0x%016lx\n",Reg64));
 491
 492   Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);
 493   DEBUG((DEBUG_INFO, "  IOTLB_REG   - 0x%016lx\n",Reg64));
 494
 495   DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) End ####\n", VtdIndex));
 496 }
 497
 498 /**
 499   Dump VTd registers for all VTd engine.
 500 **/
 501 VOID
 502 DumpVtdRegsAll (
 503   VOID
 504   )
 505 {
 506   UINTN       Num;
 507
 508   for (Num = 0; Num < mVtdUnitNumber; Num++) {
 509     DumpVtdRegs (Num);
 510   }
 511 }
 512
 513 /**
 514   Dump VTd registers if there is error.
 515 **/
 516 VOID
 517 DumpVtdIfError (
 518   VOID
 519   )
 520 {
 521   UINTN         Num;
 522   UINTN         Index;
 523   VTD_FRCD_REG  FrcdReg;
 524   VTD_CAP_REG   CapReg;
 525   UINT32        Reg32;
 526   BOOLEAN       HasError;
 527
 528   for (Num = 0; Num < mVtdUnitNumber; Num++) {
 529     HasError = FALSE;
 530     Reg32 = MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG);
 531     if (Reg32 != 0) {
 532       HasError = TRUE;
 533     }
 534     Reg32 = MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FECTL_REG);
 535     if ((Reg32 & BIT30) != 0) {
 536       HasError = TRUE;
 537     }
 538
 539     CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_CAP_REG);
 540     for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
 541       FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));
 542       FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
 543       if (FrcdReg.Bits.F != 0) {
 544         HasError = TRUE;
 545       }
 546     }
 547
 548     if (HasError) {
 549       DEBUG((DEBUG_INFO, "\n#### ERROR ####\n"));
 550       DumpVtdRegs (Num);
 551       DEBUG((DEBUG_INFO, "#### ERROR ####\n\n"));
 552       //
 553       // Clear
 554       //
 555       for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
 556         FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
 557         if (FrcdReg.Bits.F != 0) {
 558           FrcdReg.Bits.F = 0;
 559           MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), FrcdReg.Uint64[1]);
 560         }
 561         MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG));
 562       }
 563     }
 564   }
 565 }