MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c

   1 /** @file
   2   The file for AHCI mode of ATA host controller.
   3
   4   Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "AtaAtapiPassThru.h"
  16
  17 /**
  18   Read AHCI Operation register.
  19
  20   @param  PciIo        The PCI IO protocol instance.
  21   @param  Offset       The operation register offset.
  22
  23   @return The register content read.
  24
  25 **/
  26 UINT32
  27 EFIAPI
  28 AhciReadReg (
  29   IN EFI_PCI_IO_PROTOCOL  *PciIo,
  30   IN  UINT32              Offset
  31   )
  32 {
  33   UINT32                  Data;
  34
  35   ASSERT (PciIo != NULL);
  36
  37   Data = 0;
  38
  39   PciIo->Mem.Read (
  40                PciIo,
  41                EfiPciIoWidthUint32,
  42                EFI_AHCI_BAR_INDEX,
  43                (UINT64) Offset,
  44                1,
  45                &Data
  46                );
  47
  48   return Data;
  49 }
  50
  51 /**
  52   Write AHCI Operation register.
  53
  54   @param  PciIo        The PCI IO protocol instance.
  55   @param  Offset       The operation register offset.
  56   @param  Data         The data used to write down.
  57
  58 **/
  59 VOID
  60 EFIAPI
  61 AhciWriteReg (
  62   IN EFI_PCI_IO_PROTOCOL  *PciIo,
  63   IN UINT32               Offset,
  64   IN UINT32               Data
  65   )
  66 {
  67   ASSERT (PciIo != NULL);
  68
  69   PciIo->Mem.Write (
  70                PciIo,
  71                EfiPciIoWidthUint32,
  72                EFI_AHCI_BAR_INDEX,
  73                (UINT64) Offset,
  74                1,
  75                &Data
  76                );
  77
  78   return ;
  79 }
  80
  81 /**
  82   Do AND operation with the value of AHCI Operation register.
  83
  84   @param  PciIo        The PCI IO protocol instance.
  85   @param  Offset       The operation register offset.
  86   @param  AndData      The data used to do AND operation.
  87
  88 **/
  89 VOID
  90 EFIAPI
  91 AhciAndReg (
  92   IN EFI_PCI_IO_PROTOCOL  *PciIo,
  93   IN UINT32               Offset,
  94   IN UINT32               AndData
  95   )
  96 {
  97   UINT32 Data;
  98
  99   ASSERT (PciIo != NULL);
 100
 101   Data  = AhciReadReg (PciIo, Offset);
 102
 103   Data &= AndData;
 104
 105   AhciWriteReg (PciIo, Offset, Data);
 106 }
 107
 108 /**
 109   Do OR operation with the value of AHCI Operation register.
 110
 111   @param  PciIo        The PCI IO protocol instance.
 112   @param  Offset       The operation register offset.
 113   @param  OrData       The data used to do OR operation.
 114
 115 **/
 116 VOID
 117 EFIAPI
 118 AhciOrReg (
 119   IN EFI_PCI_IO_PROTOCOL  *PciIo,
 120   IN UINT32               Offset,
 121   IN UINT32               OrData
 122   )
 123 {
 124   UINT32 Data;
 125
 126   ASSERT (PciIo != NULL);
 127
 128   Data  = AhciReadReg (PciIo, Offset);
 129
 130   Data |= OrData;
 131
 132   AhciWriteReg (PciIo, Offset, Data);
 133 }
 134
 135 /**
 136   Wait for the value of the specified MMIO register set to the test value.
 137
 138   @param  PciIo             The PCI IO protocol instance.
 139   @param  Offset            The MMIO address to test.
 140   @param  MaskValue         The mask value of memory.
 141   @param  TestValue         The test value of memory.
 142   @param  Timeout           The time out value for wait memory set, uses 100ns as a unit.
 143
 144   @retval EFI_TIMEOUT       The MMIO setting is time out.
 145   @retval EFI_SUCCESS       The MMIO is correct set.
 146
 147 **/
 148 EFI_STATUS
 149 EFIAPI
 150 AhciWaitMmioSet (
 151   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 152   IN  UINTN                     Offset,
 153   IN  UINT32                    MaskValue,
 154   IN  UINT32                    TestValue,
 155   IN  UINT64                    Timeout
 156   )
 157 {
 158   UINT32     Value;
 159   UINT32     Delay;
 160
 161   Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);
 162
 163   do {
 164     //
 165     // Access PCI MMIO space to see if the value is the tested one.
 166     //
 167     Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;
 168
 169     if (Value == TestValue) {
 170       return EFI_SUCCESS;
 171     }
 172
 173     //
 174     // Stall for 100 microseconds.
 175     //
 176     MicroSecondDelay (100);
 177
 178     Delay--;
 179
 180   } while (Delay > 0);
 181
 182   return EFI_TIMEOUT;
 183 }
 184
 185 /**
 186   Wait for the value of the specified system memory set to the test value.
 187
 188   @param  Address           The system memory address to test.
 189   @param  MaskValue         The mask value of memory.
 190   @param  TestValue         The test value of memory.
 191   @param  Timeout           The time out value for wait memory set, uses 100ns as a unit.
 192
 193   @retval EFI_TIMEOUT       The system memory setting is time out.
 194   @retval EFI_SUCCESS       The system memory is correct set.
 195
 196 **/
 197 EFI_STATUS
 198 EFIAPI
 199 AhciWaitMemSet (
 200   IN  EFI_PHYSICAL_ADDRESS      Address,
 201   IN  UINT32                    MaskValue,
 202   IN  UINT32                    TestValue,
 203   IN  UINT64                    Timeout
 204   )
 205 {
 206   UINT32     Value;
 207   UINT32     Delay;
 208
 209   Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);
 210
 211   do {
 212     //
 213     // Access sytem memory to see if the value is the tested one.
 214     //
 215     // The system memory pointed by Address will be updated by the
 216     // SATA Host Controller, "volatile" is introduced to prevent
 217     // compiler from optimizing the access to the memory address
 218     // to only read once.
 219     //
 220     Value  = *(volatile UINT32 *) (UINTN) Address;
 221     Value &= MaskValue;
 222
 223     if (Value == TestValue) {
 224       return EFI_SUCCESS;
 225     }
 226
 227     //
 228     // Stall for 100 microseconds.
 229     //
 230     MicroSecondDelay (100);
 231
 232     Delay--;
 233
 234   } while (Delay > 0);
 235
 236   return EFI_TIMEOUT;
 237 }
 238
 239 /**
 240   Check the memory status to the test value.
 241
 242   @param[in]       Address           The memory address to test.
 243   @param[in]       MaskValue         The mask value of memory.
 244   @param[in]       TestValue         The test value of memory.
 245   @param[in, out]  RetryTimes        The retry times value for waitting memory set. If 0, then just try once.
 246
 247   @retval EFI_NOTREADY      The memory is not set.
 248   @retval EFI_TIMEOUT       The memory setting retry times out.
 249   @retval EFI_SUCCESS       The memory is correct set.
 250
 251 **/
 252 EFI_STATUS
 253 EFIAPI
 254 AhciCheckMemSet (
 255   IN     UINTN                     Address,
 256   IN     UINT32                    MaskValue,
 257   IN     UINT32                    TestValue,
 258   IN OUT UINTN                     *RetryTimes OPTIONAL
 259   )
 260 {
 261   UINT32     Value;
 262
 263   if (RetryTimes != NULL) {
 264     (*RetryTimes)--;
 265   }
 266
 267   Value  = *(volatile UINT32 *) Address;
 268   Value &= MaskValue;
 269
 270   if (Value == TestValue) {
 271     return EFI_SUCCESS;
 272   }
 273
 274   if ((RetryTimes != NULL) && (*RetryTimes == 0)) {
 275     return EFI_TIMEOUT;
 276   } else {
 277     return EFI_NOT_READY;
 278   }
 279 }
 280
 281 /**
 282   Check if the device is still on port. It also checks if the AHCI controller
 283   supports the address and data count will be transferred.
 284
 285   @param  PciIo            The PCI IO protocol instance.
 286   @param  Port             The number of port.
 287
 288   @retval EFI_SUCCESS      The device is attached to port and the transfer data is
 289                            supported by AHCI controller.
 290   @retval EFI_UNSUPPORTED  The transfer address and count is not supported by AHCI
 291                            controller.
 292   @retval EFI_NOT_READY    The physical communication between AHCI controller and device
 293                            is not ready.
 294
 295 **/
 296 EFI_STATUS
 297 EFIAPI
 298 AhciCheckDeviceStatus (
 299   IN  EFI_PCI_IO_PROTOCOL    *PciIo,
 300   IN  UINT8                  Port
 301   )
 302 {
 303   UINT32      Data;
 304   UINT32      Offset;
 305
 306   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
 307
 308   Data   = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
 309
 310   if (Data == EFI_AHCI_PORT_SSTS_DET_PCE) {
 311     return EFI_SUCCESS;
 312   }
 313
 314   return EFI_NOT_READY;
 315 }
 316
 317 /**
 318
 319   Clear the port interrupt and error status. It will also clear
 320   HBA interrupt status.
 321
 322   @param      PciIo          The PCI IO protocol instance.
 323   @param      Port           The number of port.
 324
 325 **/
 326 VOID
 327 EFIAPI
 328 AhciClearPortStatus (
 329   IN  EFI_PCI_IO_PROTOCOL    *PciIo,
 330   IN  UINT8                  Port
 331   )
 332 {
 333   UINT32 Offset;
 334
 335   //
 336   // Clear any error status
 337   //
 338   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
 339   AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
 340
 341   //
 342   // Clear any port interrupt status
 343   //
 344   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
 345   AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
 346
 347   //
 348   // Clear any HBA interrupt status
 349   //
 350   AhciWriteReg (PciIo, EFI_AHCI_IS_OFFSET, AhciReadReg (PciIo, EFI_AHCI_IS_OFFSET));
 351 }
 352
 353 /**
 354   This function is used to dump the Status Registers and if there is ERR bit set
 355   in the Status Register, the Error Register's value is also be dumped.
 356
 357   @param  PciIo            The PCI IO protocol instance.
 358   @param  Port             The number of port.
 359   @param  AtaStatusBlock   A pointer to EFI_ATA_STATUS_BLOCK data structure.
 360
 361 **/
 362 VOID
 363 EFIAPI
 364 AhciDumpPortStatus (
 365   IN     EFI_PCI_IO_PROTOCOL        *PciIo,
 366   IN     UINT8                      Port,
 367   IN OUT EFI_ATA_STATUS_BLOCK       *AtaStatusBlock
 368   )
 369 {
 370   UINT32               Offset;
 371   UINT32               Data;
 372
 373   ASSERT (PciIo != NULL);
 374
 375   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
 376   Data   = AhciReadReg (PciIo, Offset);
 377
 378   if (AtaStatusBlock != NULL) {
 379     ZeroMem (AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
 380
 381     AtaStatusBlock->AtaStatus  = (UINT8)Data;
 382     if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {
 383       AtaStatusBlock->AtaError = (UINT8)(Data >> 8);
 384     }
 385   }
 386 }
 387
 388
 389 /**
 390   Enable the FIS running for giving port.
 391
 392   @param      PciIo          The PCI IO protocol instance.
 393   @param      Port           The number of port.
 394   @param      Timeout        The timeout value of enabling FIS, uses 100ns as a unit.
 395
 396   @retval EFI_DEVICE_ERROR   The FIS enable setting fails.
 397   @retval EFI_TIMEOUT        The FIS enable setting is time out.
 398   @retval EFI_SUCCESS        The FIS enable successfully.
 399
 400 **/
 401 EFI_STATUS
 402 EFIAPI
 403 AhciEnableFisReceive (
 404   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 405   IN  UINT8                     Port,
 406   IN  UINT64                    Timeout
 407   )
 408 {
 409   UINT32 Offset;
 410
 411   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
 412   AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
 413
 414   return AhciWaitMmioSet (
 415            PciIo,
 416            Offset,
 417            EFI_AHCI_PORT_CMD_FR,
 418            EFI_AHCI_PORT_CMD_FR,
 419            Timeout
 420            );
 421 }
 422
 423 /**
 424   Disable the FIS running for giving port.
 425
 426   @param      PciIo          The PCI IO protocol instance.
 427   @param      Port           The number of port.
 428   @param      Timeout        The timeout value of disabling FIS, uses 100ns as a unit.
 429
 430   @retval EFI_DEVICE_ERROR   The FIS disable setting fails.
 431   @retval EFI_TIMEOUT        The FIS disable setting is time out.
 432   @retval EFI_UNSUPPORTED    The port is in running state.
 433   @retval EFI_SUCCESS        The FIS disable successfully.
 434
 435 **/
 436 EFI_STATUS
 437 EFIAPI
 438 AhciDisableFisReceive (
 439   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 440   IN  UINT8                     Port,
 441   IN  UINT64                    Timeout
 442   )
 443 {
 444   UINT32 Offset;
 445   UINT32 Data;
 446
 447   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
 448   Data   = AhciReadReg (PciIo, Offset);
 449
 450   //
 451   // Before disabling Fis receive, the DMA engine of the port should NOT be in running status.
 452   //
 453   if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) != 0) {
 454     return EFI_UNSUPPORTED;
 455   }
 456
 457   //
 458   // Check if the Fis receive DMA engine for the port is running.
 459   //
 460   if ((Data & EFI_AHCI_PORT_CMD_FR) != EFI_AHCI_PORT_CMD_FR) {
 461     return EFI_SUCCESS;
 462   }
 463
 464   AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));
 465
 466   return AhciWaitMmioSet (
 467            PciIo,
 468            Offset,
 469            EFI_AHCI_PORT_CMD_FR,
 470            0,
 471            Timeout
 472            );
 473 }
 474
 475
 476
 477 /**
 478   Build the command list, command table and prepare the fis receiver.
 479
 480   @param    PciIo                 The PCI IO protocol instance.
 481   @param    AhciRegisters         The pointer to the EFI_AHCI_REGISTERS.
 482   @param    Port                  The number of port.
 483   @param    PortMultiplier        The timeout value of stop.
 484   @param    CommandFis            The control fis will be used for the transfer.
 485   @param    CommandList           The command list will be used for the transfer.
 486   @param    AtapiCommand          The atapi command will be used for the transfer.
 487   @param    AtapiCommandLength    The length of the atapi command.
 488   @param    CommandSlotNumber     The command slot will be used for the transfer.
 489   @param    DataPhysicalAddr      The pointer to the data buffer pci bus master address.
 490   @param    DataLength            The data count to be transferred.
 491
 492 **/
 493 VOID
 494 EFIAPI
 495 AhciBuildCommand (
 496   IN     EFI_PCI_IO_PROTOCOL        *PciIo,
 497   IN     EFI_AHCI_REGISTERS         *AhciRegisters,
 498   IN     UINT8                      Port,
 499   IN     UINT8                      PortMultiplier,
 500   IN     EFI_AHCI_COMMAND_FIS       *CommandFis,
 501   IN     EFI_AHCI_COMMAND_LIST      *CommandList,
 502   IN     EFI_AHCI_ATAPI_COMMAND     *AtapiCommand OPTIONAL,
 503   IN     UINT8                      AtapiCommandLength,
 504   IN     UINT8                      CommandSlotNumber,
 505   IN OUT VOID                       *DataPhysicalAddr,
 506   IN     UINT64                     DataLength
 507   )
 508 {
 509   UINT64     BaseAddr;
 510   UINT64     PrdtNumber;
 511   UINT64     PrdtIndex;
 512   UINTN      RemainedData;
 513   UINTN      MemAddr;
 514   DATA_64    Data64;
 515   UINT32     Offset;
 516
 517   //
 518   // Filling the PRDT
 519   //
 520   PrdtNumber = (DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1) / EFI_AHCI_MAX_DATA_PER_PRDT;
 521
 522   //
 523   // According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.
 524   // It also limits that the maximum amount of the PRDT entry in the command table
 525   // is 65535.
 526   //
 527   ASSERT (PrdtNumber <= 65535);
 528
 529   Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
 530
 531   BaseAddr = Data64.Uint64;
 532
 533   ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));
 534
 535   ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));
 536
 537   CommandFis->AhciCFisPmNum = PortMultiplier;
 538
 539   CopyMem (&AhciRegisters->AhciCommandTable->CommandFis, CommandFis, sizeof (EFI_AHCI_COMMAND_FIS));
 540
 541   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
 542   if (AtapiCommand != NULL) {
 543     CopyMem (
 544       &AhciRegisters->AhciCommandTable->AtapiCmd,
 545       AtapiCommand,
 546       AtapiCommandLength
 547       );
 548
 549     CommandList->AhciCmdA = 1;
 550     CommandList->AhciCmdP = 1;
 551     CommandList->AhciCmdC = (DataLength == 0) ? 1 : 0;
 552
 553     AhciOrReg (PciIo, Offset, (EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
 554   } else {
 555     AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
 556   }
 557
 558   RemainedData = (UINTN) DataLength;
 559   MemAddr      = (UINTN) DataPhysicalAddr;
 560   CommandList->AhciCmdPrdtl = (UINT32)PrdtNumber;
 561
 562   for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {
 563     if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {
 564       AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;
 565     } else {
 566       AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = EFI_AHCI_MAX_DATA_PER_PRDT - 1;
 567     }
 568
 569     Data64.Uint64 = (UINT64)MemAddr;
 570     AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDba  = Data64.Uint32.Lower32;
 571     AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbau = Data64.Uint32.Upper32;
 572     RemainedData -= EFI_AHCI_MAX_DATA_PER_PRDT;
 573     MemAddr      += EFI_AHCI_MAX_DATA_PER_PRDT;
 574   }
 575
 576   //
 577   // Set the last PRDT to Interrupt On Complete
 578   //
 579   if (PrdtNumber > 0) {
 580     AhciRegisters->AhciCommandTable->PrdtTable[PrdtNumber - 1].AhciPrdtIoc = 1;
 581   }
 582
 583   CopyMem (
 584     (VOID *) ((UINTN) AhciRegisters->AhciCmdList + (UINTN) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),
 585     CommandList,
 586     sizeof (EFI_AHCI_COMMAND_LIST)
 587     );
 588
 589   Data64.Uint64 = (UINT64)(UINTN) AhciRegisters->AhciCommandTablePciAddr;
 590   AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba  = Data64.Uint32.Lower32;
 591   AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtbau = Data64.Uint32.Upper32;
 592   AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdPmp   = PortMultiplier;
 593
 594 }
 595
 596 /**
 597   Buid a command FIS.
 598
 599   @param  CmdFis            A pointer to the EFI_AHCI_COMMAND_FIS data structure.
 600   @param  AtaCommandBlock   A pointer to the AhciBuildCommandFis data structure.
 601
 602 **/
 603 VOID
 604 EFIAPI
 605 AhciBuildCommandFis (
 606   IN OUT EFI_AHCI_COMMAND_FIS    *CmdFis,
 607   IN     EFI_ATA_COMMAND_BLOCK   *AtaCommandBlock
 608   )
 609 {
 610   ZeroMem (CmdFis, sizeof (EFI_AHCI_COMMAND_FIS));
 611
 612   CmdFis->AhciCFisType = EFI_AHCI_FIS_REGISTER_H2D;
 613   //
 614   // Indicator it's a command
 615   //
 616   CmdFis->AhciCFisCmdInd      = 0x1;
 617   CmdFis->AhciCFisCmd         = AtaCommandBlock->AtaCommand;
 618
 619   CmdFis->AhciCFisFeature     = AtaCommandBlock->AtaFeatures;
 620   CmdFis->AhciCFisFeatureExp  = AtaCommandBlock->AtaFeaturesExp;
 621
 622   CmdFis->AhciCFisSecNum      = AtaCommandBlock->AtaSectorNumber;
 623   CmdFis->AhciCFisSecNumExp   = AtaCommandBlock->AtaSectorNumberExp;
 624
 625   CmdFis->AhciCFisClyLow      = AtaCommandBlock->AtaCylinderLow;
 626   CmdFis->AhciCFisClyLowExp   = AtaCommandBlock->AtaCylinderLowExp;
 627
 628   CmdFis->AhciCFisClyHigh     = AtaCommandBlock->AtaCylinderHigh;
 629   CmdFis->AhciCFisClyHighExp  = AtaCommandBlock->AtaCylinderHighExp;
 630
 631   CmdFis->AhciCFisSecCount    = AtaCommandBlock->AtaSectorCount;
 632   CmdFis->AhciCFisSecCountExp = AtaCommandBlock->AtaSectorCountExp;
 633
 634   CmdFis->AhciCFisDevHead     = (UINT8) (AtaCommandBlock->AtaDeviceHead | 0xE0);
 635 }
 636
 637 /**
 638   Start a PIO data transfer on specific port.
 639
 640   @param[in]       PciIo               The PCI IO protocol instance.
 641   @param[in]       AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
 642   @param[in]       Port                The number of port.
 643   @param[in]       PortMultiplier      The timeout value of stop.
 644   @param[in]       AtapiCommand        The atapi command will be used for the
 645                                        transfer.
 646   @param[in]       AtapiCommandLength  The length of the atapi command.
 647   @param[in]       Read                The transfer direction.
 648   @param[in]       AtaCommandBlock     The EFI_ATA_COMMAND_BLOCK data.
 649   @param[in, out]  AtaStatusBlock      The EFI_ATA_STATUS_BLOCK data.
 650   @param[in, out]  MemoryAddr          The pointer to the data buffer.
 651   @param[in]       DataCount           The data count to be transferred.
 652   @param[in]       Timeout             The timeout value of non data transfer, uses 100ns as a unit.
 653   @param[in]       Task                Optional. Pointer to the ATA_NONBLOCK_TASK
 654                                        used by non-blocking mode.
 655
 656   @retval EFI_DEVICE_ERROR    The PIO data transfer abort with error occurs.
 657   @retval EFI_TIMEOUT         The operation is time out.
 658   @retval EFI_UNSUPPORTED     The device is not ready for transfer.
 659   @retval EFI_SUCCESS         The PIO data transfer executes successfully.
 660
 661 **/
 662 EFI_STATUS
 663 EFIAPI
 664 AhciPioTransfer (
 665   IN     EFI_PCI_IO_PROTOCOL        *PciIo,
 666   IN     EFI_AHCI_REGISTERS         *AhciRegisters,
 667   IN     UINT8                      Port,
 668   IN     UINT8                      PortMultiplier,
 669   IN     EFI_AHCI_ATAPI_COMMAND     *AtapiCommand OPTIONAL,
 670   IN     UINT8                      AtapiCommandLength,
 671   IN     BOOLEAN                    Read,
 672   IN     EFI_ATA_COMMAND_BLOCK      *AtaCommandBlock,
 673   IN OUT EFI_ATA_STATUS_BLOCK       *AtaStatusBlock,
 674   IN OUT VOID                       *MemoryAddr,
 675   IN     UINT32                     DataCount,
 676   IN     UINT64                     Timeout,
 677   IN     ATA_NONBLOCK_TASK          *Task
 678   )
 679 {
 680   EFI_STATUS                    Status;
 681   UINTN                         FisBaseAddr;
 682   UINTN                         Offset;
 683   EFI_PHYSICAL_ADDRESS          PhyAddr;
 684   VOID                          *Map;
 685   UINTN                         MapLength;
 686   EFI_PCI_IO_PROTOCOL_OPERATION Flag;
 687   UINT32                        Delay;
 688   EFI_AHCI_COMMAND_FIS          CFis;
 689   EFI_AHCI_COMMAND_LIST         CmdList;
 690   UINT32                        PortTfd;
 691   UINT32                        PrdCount;
 692
 693   if (Read) {
 694     Flag = EfiPciIoOperationBusMasterWrite;
 695   } else {
 696     Flag = EfiPciIoOperationBusMasterRead;
 697   }
 698
 699   //
 700   // construct command list and command table with pci bus address
 701   //
 702   MapLength = DataCount;
 703   Status = PciIo->Map (
 704                     PciIo,
 705                     Flag,
 706                     MemoryAddr,
 707                     &MapLength,
 708                     &PhyAddr,
 709                     &Map
 710                     );
 711
 712   if (EFI_ERROR (Status) || (DataCount != MapLength)) {
 713     return EFI_BAD_BUFFER_SIZE;
 714   }
 715
 716   //
 717   // Package read needed
 718   //
 719   AhciBuildCommandFis (&CFis, AtaCommandBlock);
 720
 721   ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
 722
 723   CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
 724   CmdList.AhciCmdW   = Read ? 0 : 1;
 725
 726   AhciBuildCommand (
 727     PciIo,
 728     AhciRegisters,
 729     Port,
 730     PortMultiplier,
 731     &CFis,
 732     &CmdList,
 733     AtapiCommand,
 734     AtapiCommandLength,
 735     0,
 736     (VOID *)(UINTN)PhyAddr,
 737     DataCount
 738     );
 739
 740   Status = AhciStartCommand (
 741              PciIo,
 742              Port,
 743              0,
 744              Timeout
 745              );
 746   if (EFI_ERROR (Status)) {
 747     goto Exit;
 748   }
 749
 750   //
 751   // Check the status and wait the driver sending data
 752   //
 753   FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
 754
 755   if (Read && (AtapiCommand == 0)) {
 756     //
 757     // Wait device sends the PIO setup fis before data transfer
 758     //
 759     Status = EFI_TIMEOUT;
 760     Delay  = (UINT32) (DivU64x32 (Timeout, 1000) + 1);
 761     do {
 762       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
 763       PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
 764
 765       if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
 766         Status = EFI_DEVICE_ERROR;
 767         break;
 768       }
 769       Offset = FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET;
 770
 771       Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, 0);
 772       if (!EFI_ERROR (Status)) {
 773         PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
 774         if (PrdCount == DataCount) {
 775           break;
 776         }
 777       }
 778
 779       Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
 780       Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, 0);
 781       if (!EFI_ERROR (Status)) {
 782         Status = EFI_DEVICE_ERROR;
 783         break;
 784       }
 785
 786       //
 787       // Stall for 100 microseconds.
 788       //
 789       MicroSecondDelay(100);
 790
 791       Delay--;
 792     } while (Delay > 0);
 793   } else {
 794     //
 795     // Wait for D2H Fis is received
 796     //
 797     Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
 798     Status = AhciWaitMemSet (
 799                Offset,
 800                EFI_AHCI_FIS_TYPE_MASK,
 801                EFI_AHCI_FIS_REGISTER_D2H,
 802                Timeout
 803                );
 804
 805     if (EFI_ERROR (Status)) {
 806       goto Exit;
 807     }
 808
 809     Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
 810     PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
 811     if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
 812       Status = EFI_DEVICE_ERROR;
 813     }
 814   }
 815
 816 Exit:
 817   AhciStopCommand (
 818     PciIo,
 819     Port,
 820     Timeout
 821     );
 822
 823   AhciDisableFisReceive (
 824     PciIo,
 825     Port,
 826     Timeout
 827     );
 828
 829   PciIo->Unmap (
 830     PciIo,
 831     Map
 832     );
 833
 834   AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);
 835
 836   return Status;
 837 }
 838
 839 /**
 840   Start a DMA data transfer on specific port
 841
 842   @param[in]       Instance            The ATA_ATAPI_PASS_THRU_INSTANCE protocol instance.
 843   @param[in]       AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
 844   @param[in]       Port                The number of port.
 845   @param[in]       PortMultiplier      The timeout value of stop.
 846   @param[in]       AtapiCommand        The atapi command will be used for the
 847                                        transfer.
 848   @param[in]       AtapiCommandLength  The length of the atapi command.
 849   @param[in]       Read                The transfer direction.
 850   @param[in]       AtaCommandBlock     The EFI_ATA_COMMAND_BLOCK data.
 851   @param[in, out]  AtaStatusBlock      The EFI_ATA_STATUS_BLOCK data.
 852   @param[in, out]  MemoryAddr          The pointer to the data buffer.
 853   @param[in]       DataCount           The data count to be transferred.
 854   @param[in]       Timeout             The timeout value of non data transfer, uses 100ns as a unit.
 855   @param[in]       Task                Optional. Pointer to the ATA_NONBLOCK_TASK
 856                                        used by non-blocking mode.
 857
 858   @retval EFI_DEVICE_ERROR    The DMA data transfer abort with error occurs.
 859   @retval EFI_TIMEOUT         The operation is time out.
 860   @retval EFI_UNSUPPORTED     The device is not ready for transfer.
 861   @retval EFI_SUCCESS         The DMA data transfer executes successfully.
 862
 863 **/
 864 EFI_STATUS
 865 EFIAPI
 866 AhciDmaTransfer (
 867   IN     ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
 868   IN     EFI_AHCI_REGISTERS         *AhciRegisters,
 869   IN     UINT8                      Port,
 870   IN     UINT8                      PortMultiplier,
 871   IN     EFI_AHCI_ATAPI_COMMAND     *AtapiCommand OPTIONAL,
 872   IN     UINT8                      AtapiCommandLength,
 873   IN     BOOLEAN                    Read,
 874   IN     EFI_ATA_COMMAND_BLOCK      *AtaCommandBlock,
 875   IN OUT EFI_ATA_STATUS_BLOCK       *AtaStatusBlock,
 876   IN OUT VOID                       *MemoryAddr,
 877   IN     UINT32                     DataCount,
 878   IN     UINT64                     Timeout,
 879   IN     ATA_NONBLOCK_TASK          *Task
 880   )
 881 {
 882   EFI_STATUS                    Status;
 883   UINTN                         Offset;
 884   EFI_PHYSICAL_ADDRESS          PhyAddr;
 885   VOID                          *Map;
 886   UINTN                         MapLength;
 887   EFI_PCI_IO_PROTOCOL_OPERATION Flag;
 888   EFI_AHCI_COMMAND_FIS          CFis;
 889   EFI_AHCI_COMMAND_LIST         CmdList;
 890   UINTN                         FisBaseAddr;
 891   UINT32                        PortTfd;
 892
 893   EFI_PCI_IO_PROTOCOL           *PciIo;
 894   EFI_TPL                       OldTpl;
 895
 896   Map   = NULL;
 897   PciIo = Instance->PciIo;
 898
 899   if (PciIo == NULL) {
 900     return EFI_INVALID_PARAMETER;
 901   }
 902
 903   //
 904   // Before starting the Blocking BlockIO operation, push to finish all non-blocking
 905   // BlockIO tasks.
 906   // Delay 100us to simulate the blocking time out checking.
 907   //
 908   OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
 909   while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {
 910     AsyncNonBlockingTransferRoutine (NULL, Instance);
 911     //
 912     // Stall for 100us.
 913     //
 914     MicroSecondDelay (100);
 915   }
 916   gBS->RestoreTPL (OldTpl);
 917
 918   if ((Task == NULL) || ((Task != NULL) && (!Task->IsStart))) {
 919     //
 920     // Mark the Task to indicate that it has been started.
 921     //
 922     if (Task != NULL) {
 923       Task->IsStart      = TRUE;
 924       Task->RetryTimes   = (UINT32) (DivU64x32(Timeout, 1000) + 1);
 925     }
 926     if (Read) {
 927       Flag = EfiPciIoOperationBusMasterWrite;
 928     } else {
 929       Flag = EfiPciIoOperationBusMasterRead;
 930     }
 931
 932     //
 933     // Construct command list and command table with pci bus address.
 934     //
 935     MapLength = DataCount;
 936     Status = PciIo->Map (
 937                       PciIo,
 938                       Flag,
 939                       MemoryAddr,
 940                       &MapLength,
 941                       &PhyAddr,
 942                       &Map
 943                       );
 944
 945     if (EFI_ERROR (Status) || (DataCount != MapLength)) {
 946       return EFI_BAD_BUFFER_SIZE;
 947     }
 948
 949     if (Task != NULL) {
 950       Task->Map = Map;
 951     }
 952     //
 953     // Package read needed
 954     //
 955     AhciBuildCommandFis (&CFis, AtaCommandBlock);
 956
 957     ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
 958
 959     CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
 960     CmdList.AhciCmdW   = Read ? 0 : 1;
 961
 962     AhciBuildCommand (
 963       PciIo,
 964       AhciRegisters,
 965       Port,
 966       PortMultiplier,
 967       &CFis,
 968       &CmdList,
 969       AtapiCommand,
 970       AtapiCommandLength,
 971       0,
 972       (VOID *)(UINTN)PhyAddr,
 973       DataCount
 974       );
 975
 976     Status = AhciStartCommand (
 977                PciIo,
 978                Port,
 979                0,
 980                Timeout
 981                );
 982     if (EFI_ERROR (Status)) {
 983       goto Exit;
 984     }
 985   }
 986
 987   //
 988   // Wait for command compelte
 989   //
 990   FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
 991   Offset      = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
 992   if (Task != NULL) {
 993     //
 994     // For Non-blocking
 995     //
 996     Status = AhciCheckMemSet (
 997                Offset,
 998                EFI_AHCI_FIS_TYPE_MASK,
 999                EFI_AHCI_FIS_REGISTER_D2H,
1000                (UINTN *) (&Task->RetryTimes)
1001                );
1002   } else {
1003     Status = AhciWaitMemSet (
1004                Offset,
1005                EFI_AHCI_FIS_TYPE_MASK,
1006                EFI_AHCI_FIS_REGISTER_D2H,
1007                Timeout
1008                );
1009   }
1010
1011   if (EFI_ERROR (Status)) {
1012     goto Exit;
1013   }
1014
1015   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
1016   PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
1017   if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
1018     Status = EFI_DEVICE_ERROR;
1019   }
1020
1021 Exit:
1022   //
1023   // For Blocking mode, the command should be stopped, the Fis should be disabled
1024   // and the PciIo should be unmapped.
1025   // For non-blocking mode, only when a error is happened (if the return status is
1026   // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
1027   // context cleanup, then set the packet's Asb status.
1028   //
1029   if (Task == NULL ||
1030       ((Task != NULL) && (Status != EFI_NOT_READY))
1031      ) {
1032     AhciStopCommand (
1033       PciIo,
1034       Port,
1035       Timeout
1036       );
1037
1038     AhciDisableFisReceive (
1039       PciIo,
1040       Port,
1041       Timeout
1042       );
1043
1044     PciIo->Unmap (
1045              PciIo,
1046              (Task != NULL) ? Task->Map : Map
1047              );
1048
1049     if (Task != NULL) {
1050       Task->Packet->Asb->AtaStatus = 0x01;
1051     }
1052   }
1053
1054   AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);
1055   return Status;
1056 }
1057
1058 /**
1059   Start a non data transfer on specific port.
1060
1061   @param[in]       PciIo               The PCI IO protocol instance.
1062   @param[in]       AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1063   @param[in]       Port                The number of port.
1064   @param[in]       PortMultiplier      The timeout value of stop.
1065   @param[in]       AtapiCommand        The atapi command will be used for the
1066                                        transfer.
1067   @param[in]       AtapiCommandLength  The length of the atapi command.
1068   @param[in]       AtaCommandBlock     The EFI_ATA_COMMAND_BLOCK data.
1069   @param[in, out]  AtaStatusBlock      The EFI_ATA_STATUS_BLOCK data.
1070   @param[in]       Timeout             The timeout value of non data transfer, uses 100ns as a unit.
1071   @param[in]       Task                Optional. Pointer to the ATA_NONBLOCK_TASK
1072                                        used by non-blocking mode.
1073
1074   @retval EFI_DEVICE_ERROR    The non data transfer abort with error occurs.
1075   @retval EFI_TIMEOUT         The operation is time out.
1076   @retval EFI_UNSUPPORTED     The device is not ready for transfer.
1077   @retval EFI_SUCCESS         The non data transfer executes successfully.
1078
1079 **/
1080 EFI_STATUS
1081 EFIAPI
1082 AhciNonDataTransfer (
1083   IN     EFI_PCI_IO_PROTOCOL           *PciIo,
1084   IN     EFI_AHCI_REGISTERS            *AhciRegisters,
1085   IN     UINT8                         Port,
1086   IN     UINT8                         PortMultiplier,
1087   IN     EFI_AHCI_ATAPI_COMMAND        *AtapiCommand OPTIONAL,
1088   IN     UINT8                         AtapiCommandLength,
1089   IN     EFI_ATA_COMMAND_BLOCK         *AtaCommandBlock,
1090   IN OUT EFI_ATA_STATUS_BLOCK          *AtaStatusBlock,
1091   IN     UINT64                        Timeout,
1092   IN     ATA_NONBLOCK_TASK             *Task
1093   )
1094 {
1095   EFI_STATUS                   Status;
1096   UINTN                        FisBaseAddr;
1097   UINTN                        Offset;
1098   UINT32                       PortTfd;
1099   EFI_AHCI_COMMAND_FIS         CFis;
1100   EFI_AHCI_COMMAND_LIST        CmdList;
1101
1102   //
1103   // Package read needed
1104   //
1105   AhciBuildCommandFis (&CFis, AtaCommandBlock);
1106
1107   ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
1108
1109   CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
1110
1111   AhciBuildCommand (
1112     PciIo,
1113     AhciRegisters,
1114     Port,
1115     PortMultiplier,
1116     &CFis,
1117     &CmdList,
1118     AtapiCommand,
1119     AtapiCommandLength,
1120     0,
1121     NULL,
1122     0
1123     );
1124
1125   Status = AhciStartCommand (
1126              PciIo,
1127              Port,
1128              0,
1129              Timeout
1130              );
1131   if (EFI_ERROR (Status)) {
1132     goto Exit;
1133   }
1134
1135   //
1136   // Wait device sends the Response Fis
1137   //
1138   FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
1139   Offset      = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
1140   Status      = AhciWaitMemSet (
1141                   Offset,
1142                   EFI_AHCI_FIS_TYPE_MASK,
1143                   EFI_AHCI_FIS_REGISTER_D2H,
1144                   Timeout
1145                   );
1146
1147   if (EFI_ERROR (Status)) {
1148     goto Exit;
1149   }
1150
1151   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
1152   PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
1153   if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
1154     Status = EFI_DEVICE_ERROR;
1155   }
1156
1157 Exit:
1158   AhciStopCommand (
1159     PciIo,
1160     Port,
1161     Timeout
1162     );
1163
1164   AhciDisableFisReceive (
1165     PciIo,
1166     Port,
1167     Timeout
1168     );
1169
1170   AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);
1171
1172   return Status;
1173 }
1174
1175 /**
1176   Stop command running for giving port
1177
1178   @param  PciIo              The PCI IO protocol instance.
1179   @param  Port               The number of port.
1180   @param  Timeout            The timeout value of stop, uses 100ns as a unit.
1181
1182   @retval EFI_DEVICE_ERROR   The command stop unsuccessfully.
1183   @retval EFI_TIMEOUT        The operation is time out.
1184   @retval EFI_SUCCESS        The command stop successfully.
1185
1186 **/
1187 EFI_STATUS
1188 EFIAPI
1189 AhciStopCommand (
1190   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
1191   IN  UINT8                     Port,
1192   IN  UINT64                    Timeout
1193   )
1194 {
1195   UINT32 Offset;
1196   UINT32 Data;
1197
1198   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1199   Data   = AhciReadReg (PciIo, Offset);
1200
1201   if ((Data & (EFI_AHCI_PORT_CMD_ST |  EFI_AHCI_PORT_CMD_CR)) == 0) {
1202     return EFI_SUCCESS;
1203   }
1204
1205   if ((Data & EFI_AHCI_PORT_CMD_ST) != 0) {
1206     AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));
1207   }
1208
1209   return AhciWaitMmioSet (
1210            PciIo,
1211            Offset,
1212            EFI_AHCI_PORT_CMD_CR,
1213            0,
1214            Timeout
1215            );
1216 }
1217
1218 /**
1219   Start command for give slot on specific port.
1220
1221   @param  PciIo              The PCI IO protocol instance.
1222   @param  Port               The number of port.
1223   @param  CommandSlot        The number of Command Slot.
1224   @param  Timeout            The timeout value of start, uses 100ns as a unit.
1225
1226   @retval EFI_DEVICE_ERROR   The command start unsuccessfully.
1227   @retval EFI_TIMEOUT        The operation is time out.
1228   @retval EFI_SUCCESS        The command start successfully.
1229
1230 **/
1231 EFI_STATUS
1232 EFIAPI
1233 AhciStartCommand (
1234   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
1235   IN  UINT8                     Port,
1236   IN  UINT8                     CommandSlot,
1237   IN  UINT64                    Timeout
1238   )
1239 {
1240   UINT32     CmdSlotBit;
1241   EFI_STATUS Status;
1242   UINT32     PortStatus;
1243   UINT32     StartCmd;
1244   UINT32     PortTfd;
1245   UINT32     Offset;
1246   UINT32     Capability;
1247
1248   //
1249   // Collect AHCI controller information
1250   //
1251   Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
1252
1253   CmdSlotBit = (UINT32) (1 << CommandSlot);
1254
1255   AhciClearPortStatus (
1256     PciIo,
1257     Port
1258     );
1259
1260   Status = AhciEnableFisReceive (
1261              PciIo,
1262              Port,
1263              Timeout
1264              );
1265
1266   if (EFI_ERROR (Status)) {
1267     return Status;
1268   }
1269
1270   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1271   PortStatus = AhciReadReg (PciIo, Offset);
1272
1273   StartCmd = 0;
1274   if ((PortStatus & EFI_AHCI_PORT_CMD_ALPE) != 0) {
1275     StartCmd = AhciReadReg (PciIo, Offset);
1276     StartCmd &= ~EFI_AHCI_PORT_CMD_ICC_MASK;
1277     StartCmd |= EFI_AHCI_PORT_CMD_ACTIVE;
1278   }
1279
1280   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
1281   PortTfd = AhciReadReg (PciIo, Offset);
1282
1283   if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
1284     if ((Capability & BIT24) != 0) {
1285       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1286       AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_CLO);
1287
1288       AhciWaitMmioSet (
1289         PciIo,
1290         Offset,
1291         EFI_AHCI_PORT_CMD_CLO,
1292         0,
1293         Timeout
1294         );
1295     }
1296   }
1297
1298   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1299   AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_ST | StartCmd);
1300
1301   //
1302   // Setting the command
1303   //
1304   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SACT;
1305   AhciAndReg (PciIo, Offset, 0);
1306   AhciOrReg (PciIo, Offset, CmdSlotBit);
1307
1308   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
1309   AhciAndReg (PciIo, Offset, 0);
1310   AhciOrReg (PciIo, Offset, CmdSlotBit);
1311
1312   return EFI_SUCCESS;
1313 }
1314
1315 /**
1316   Do AHCI port reset.
1317
1318   @param  PciIo              The PCI IO protocol instance.
1319   @param  Port               The number of port.
1320   @param  Timeout            The timeout value of reset, uses 100ns as a unit.
1321
1322   @retval EFI_DEVICE_ERROR   The port reset unsuccessfully
1323   @retval EFI_TIMEOUT        The reset operation is time out.
1324   @retval EFI_SUCCESS        The port reset successfully.
1325
1326 **/
1327 EFI_STATUS
1328 EFIAPI
1329 AhciPortReset (
1330   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
1331   IN  UINT8                     Port,
1332   IN  UINT64                    Timeout
1333   )
1334 {
1335   EFI_STATUS      Status;
1336   UINT32          Offset;
1337
1338   AhciClearPortStatus (PciIo, Port);
1339
1340   AhciStopCommand (PciIo, Port, Timeout);
1341
1342   AhciDisableFisReceive (PciIo, Port, Timeout);
1343
1344   AhciEnableFisReceive (PciIo, Port, Timeout);
1345
1346   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
1347
1348   AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_DET_INIT);
1349
1350   //
1351   // wait 5 millisecond before de-assert DET
1352   //
1353   MicroSecondDelay (5000);
1354
1355   AhciAndReg (PciIo, Offset, (UINT32)EFI_AHCI_PORT_SCTL_MASK);
1356
1357   //
1358   // wait 5 millisecond before de-assert DET
1359   //
1360   MicroSecondDelay (5000);
1361
1362   //
1363   // Wait for communication to be re-established
1364   //
1365   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
1366   Status = AhciWaitMmioSet (
1367              PciIo,
1368              Offset,
1369              EFI_AHCI_PORT_SSTS_DET_MASK,
1370              EFI_AHCI_PORT_SSTS_DET_PCE,
1371              Timeout
1372              );
1373
1374   if (EFI_ERROR (Status)) {
1375     return Status;
1376   }
1377
1378   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
1379   AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_ERR_CLEAR);
1380
1381   return EFI_SUCCESS;
1382 }
1383
1384 /**
1385   Do AHCI HBA reset.
1386
1387   @param  PciIo              The PCI IO protocol instance.
1388   @param  Timeout            The timeout value of reset, uses 100ns as a unit.
1389
1390   @retval EFI_DEVICE_ERROR   AHCI controller is failed to complete hardware reset.
1391   @retval EFI_TIMEOUT        The reset operation is time out.
1392   @retval EFI_SUCCESS        AHCI controller is reset successfully.
1393
1394 **/
1395 EFI_STATUS
1396 EFIAPI
1397 AhciReset (
1398   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
1399   IN  UINT64                    Timeout
1400   )
1401 {
1402   UINT32                 Delay;
1403   UINT32                 Value;
1404
1405   AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
1406
1407   AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
1408
1409   Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
1410
1411   do {
1412     Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
1413
1414     if ((Value & EFI_AHCI_GHC_RESET) == 0) {
1415       break;
1416     }
1417
1418     //
1419     // Stall for 100 microseconds.
1420     //
1421     MicroSecondDelay(100);
1422
1423     Delay--;
1424   } while (Delay > 0);
1425
1426   if (Delay == 0) {
1427     return EFI_TIMEOUT;
1428   }
1429
1430   return EFI_SUCCESS;
1431 }
1432
1433 /**
1434   Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
1435
1436   @param  PciIo               The PCI IO protocol instance.
1437   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1438   @param  Port                The number of port.
1439   @param  PortMultiplier      The timeout value of stop.
1440   @param  AtaStatusBlock      A pointer to EFI_ATA_STATUS_BLOCK data structure.
1441
1442   @retval EFI_SUCCESS     Successfully get the return status of S.M.A.R.T command execution.
1443   @retval Others          Fail to get return status data.
1444
1445 **/
1446 EFI_STATUS
1447 EFIAPI
1448 AhciAtaSmartReturnStatusCheck (
1449   IN EFI_PCI_IO_PROTOCOL         *PciIo,
1450   IN EFI_AHCI_REGISTERS          *AhciRegisters,
1451   IN UINT8                       Port,
1452   IN UINT8                       PortMultiplier,
1453   IN OUT EFI_ATA_STATUS_BLOCK    *AtaStatusBlock
1454   )
1455 {
1456   EFI_STATUS              Status;
1457   EFI_ATA_COMMAND_BLOCK   AtaCommandBlock;
1458   UINT8                   LBAMid;
1459   UINT8                   LBAHigh;
1460   UINTN                   FisBaseAddr;
1461   UINT32                  Value;
1462
1463   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1464
1465   AtaCommandBlock.AtaCommand      = ATA_CMD_SMART;
1466   AtaCommandBlock.AtaFeatures     = ATA_SMART_RETURN_STATUS;
1467   AtaCommandBlock.AtaCylinderLow  = ATA_CONSTANT_4F;
1468   AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1469
1470   //
1471   // Send S.M.A.R.T Read Return Status command to device
1472   //
1473   Status = AhciNonDataTransfer (
1474              PciIo,
1475              AhciRegisters,
1476              (UINT8)Port,
1477              (UINT8)PortMultiplier,
1478              NULL,
1479              0,
1480              &AtaCommandBlock,
1481              AtaStatusBlock,
1482              ATA_ATAPI_TIMEOUT,
1483              NULL
1484              );
1485
1486   if (EFI_ERROR (Status)) {
1487     return EFI_DEVICE_ERROR;
1488   }
1489
1490   FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
1491
1492   Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
1493
1494   if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {
1495     LBAMid  = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[5];
1496     LBAHigh = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[6];
1497
1498     if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
1499       //
1500       // The threshold exceeded condition is not detected by the device
1501       //
1502       DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
1503
1504     } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
1505       //
1506       // The threshold exceeded condition is detected by the device
1507       //
1508       DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
1509     }
1510   }
1511
1512   return EFI_SUCCESS;
1513 }
1514
1515 /**
1516   Enable SMART command of the disk if supported.
1517
1518   @param  PciIo               The PCI IO protocol instance.
1519   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1520   @param  Port                The number of port.
1521   @param  PortMultiplier      The timeout value of stop.
1522   @param  IdentifyData        A pointer to data buffer which is used to contain IDENTIFY data.
1523   @param  AtaStatusBlock      A pointer to EFI_ATA_STATUS_BLOCK data structure.
1524
1525 **/
1526 VOID
1527 EFIAPI
1528 AhciAtaSmartSupport (
1529   IN EFI_PCI_IO_PROTOCOL           *PciIo,
1530   IN EFI_AHCI_REGISTERS            *AhciRegisters,
1531   IN UINT8                         Port,
1532   IN UINT8                         PortMultiplier,
1533   IN EFI_IDENTIFY_DATA             *IdentifyData,
1534   IN OUT EFI_ATA_STATUS_BLOCK      *AtaStatusBlock
1535   )
1536 {
1537   EFI_STATUS               Status;
1538   EFI_ATA_COMMAND_BLOCK    AtaCommandBlock;
1539
1540   //
1541   // Detect if the device supports S.M.A.R.T.
1542   //
1543   if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
1544     //
1545     // S.M.A.R.T is not supported by the device
1546     //
1547     DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
1548             Port, PortMultiplier));
1549   } else {
1550     //
1551     // Check if the feature is enabled. If not, then enable S.M.A.R.T.
1552     //
1553     if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
1554       ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1555
1556       AtaCommandBlock.AtaCommand      = ATA_CMD_SMART;
1557       AtaCommandBlock.AtaFeatures     = ATA_SMART_ENABLE_OPERATION;
1558       AtaCommandBlock.AtaCylinderLow  = ATA_CONSTANT_4F;
1559       AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1560
1561       //
1562       // Send S.M.A.R.T Enable command to device
1563       //
1564       Status = AhciNonDataTransfer (
1565                  PciIo,
1566                  AhciRegisters,
1567                  (UINT8)Port,
1568                  (UINT8)PortMultiplier,
1569                  NULL,
1570                  0,
1571                  &AtaCommandBlock,
1572                  AtaStatusBlock,
1573                  ATA_ATAPI_TIMEOUT,
1574                  NULL
1575                  );
1576
1577
1578       if (!EFI_ERROR (Status)) {
1579         //
1580         // Send S.M.A.R.T AutoSave command to device
1581         //
1582         ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1583
1584         AtaCommandBlock.AtaCommand      = ATA_CMD_SMART;
1585         AtaCommandBlock.AtaFeatures     = 0xD2;
1586         AtaCommandBlock.AtaSectorCount  = 0xF1;
1587         AtaCommandBlock.AtaCylinderLow  = ATA_CONSTANT_4F;
1588         AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1589
1590         Status = AhciNonDataTransfer (
1591                    PciIo,
1592                    AhciRegisters,
1593                    (UINT8)Port,
1594                    (UINT8)PortMultiplier,
1595                    NULL,
1596                    0,
1597                    &AtaCommandBlock,
1598                    AtaStatusBlock,
1599                    ATA_ATAPI_TIMEOUT,
1600                    NULL
1601                    );
1602
1603         if (!EFI_ERROR (Status)) {
1604           Status = AhciAtaSmartReturnStatusCheck (
1605                      PciIo,
1606                      AhciRegisters,
1607                      (UINT8)Port,
1608                      (UINT8)PortMultiplier,
1609                      AtaStatusBlock
1610                      );
1611         }
1612       }
1613     }
1614     DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",
1615             Port, PortMultiplier));
1616   }
1617
1618   return ;
1619 }
1620
1621 /**
1622   Send Buffer cmd to specific device.
1623
1624   @param  PciIo               The PCI IO protocol instance.
1625   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1626   @param  Port                The number of port.
1627   @param  PortMultiplier      The timeout value of stop.
1628   @param  Buffer              The data buffer to store IDENTIFY PACKET data.
1629
1630   @retval EFI_DEVICE_ERROR    The cmd abort with error occurs.
1631   @retval EFI_TIMEOUT         The operation is time out.
1632   @retval EFI_UNSUPPORTED     The device is not ready for executing.
1633   @retval EFI_SUCCESS         The cmd executes successfully.
1634
1635 **/
1636 EFI_STATUS
1637 EFIAPI
1638 AhciIdentify (
1639   IN EFI_PCI_IO_PROTOCOL      *PciIo,
1640   IN EFI_AHCI_REGISTERS       *AhciRegisters,
1641   IN UINT8                    Port,
1642   IN UINT8                    PortMultiplier,
1643   IN OUT EFI_IDENTIFY_DATA    *Buffer
1644   )
1645 {
1646   EFI_STATUS                   Status;
1647   EFI_ATA_COMMAND_BLOCK        AtaCommandBlock;
1648   EFI_ATA_STATUS_BLOCK         AtaStatusBlock;
1649
1650   if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
1651     return EFI_INVALID_PARAMETER;
1652   }
1653
1654   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1655   ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1656
1657   AtaCommandBlock.AtaCommand     = ATA_CMD_IDENTIFY_DRIVE;
1658   AtaCommandBlock.AtaSectorCount = 1;
1659
1660   Status = AhciPioTransfer (
1661              PciIo,
1662              AhciRegisters,
1663              Port,
1664              PortMultiplier,
1665              NULL,
1666              0,
1667              TRUE,
1668              &AtaCommandBlock,
1669              &AtaStatusBlock,
1670              Buffer,
1671              sizeof (EFI_IDENTIFY_DATA),
1672              ATA_ATAPI_TIMEOUT,
1673              NULL
1674              );
1675
1676   return Status;
1677 }
1678
1679 /**
1680   Send Buffer cmd to specific device.
1681
1682   @param  PciIo               The PCI IO protocol instance.
1683   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1684   @param  Port                The number of port.
1685   @param  PortMultiplier      The timeout value of stop.
1686   @param  Buffer              The data buffer to store IDENTIFY PACKET data.
1687
1688   @retval EFI_DEVICE_ERROR    The cmd abort with error occurs.
1689   @retval EFI_TIMEOUT         The operation is time out.
1690   @retval EFI_UNSUPPORTED     The device is not ready for executing.
1691   @retval EFI_SUCCESS         The cmd executes successfully.
1692
1693 **/
1694 EFI_STATUS
1695 EFIAPI
1696 AhciIdentifyPacket (
1697   IN EFI_PCI_IO_PROTOCOL      *PciIo,
1698   IN EFI_AHCI_REGISTERS       *AhciRegisters,
1699   IN UINT8                    Port,
1700   IN UINT8                    PortMultiplier,
1701   IN OUT EFI_IDENTIFY_DATA    *Buffer
1702   )
1703 {
1704   EFI_STATUS                   Status;
1705   EFI_ATA_COMMAND_BLOCK        AtaCommandBlock;
1706   EFI_ATA_STATUS_BLOCK         AtaStatusBlock;
1707
1708   if (PciIo == NULL || AhciRegisters == NULL) {
1709     return EFI_INVALID_PARAMETER;
1710   }
1711
1712   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1713   ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1714
1715   AtaCommandBlock.AtaCommand     = ATA_CMD_IDENTIFY_DEVICE;
1716   AtaCommandBlock.AtaSectorCount = 1;
1717
1718   Status = AhciPioTransfer (
1719              PciIo,
1720              AhciRegisters,
1721              Port,
1722              PortMultiplier,
1723              NULL,
1724              0,
1725              TRUE,
1726              &AtaCommandBlock,
1727              &AtaStatusBlock,
1728              Buffer,
1729              sizeof (EFI_IDENTIFY_DATA),
1730              ATA_ATAPI_TIMEOUT,
1731              NULL
1732              );
1733
1734   return Status;
1735 }
1736
1737 /**
1738   Send SET FEATURE cmd on specific device.
1739
1740   @param  PciIo               The PCI IO protocol instance.
1741   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1742   @param  Port                The number of port.
1743   @param  PortMultiplier      The timeout value of stop.
1744   @param  Feature             The data to send Feature register.
1745   @param  FeatureSpecificData The specific data for SET FEATURE cmd.
1746
1747   @retval EFI_DEVICE_ERROR    The cmd abort with error occurs.
1748   @retval EFI_TIMEOUT         The operation is time out.
1749   @retval EFI_UNSUPPORTED     The device is not ready for executing.
1750   @retval EFI_SUCCESS         The cmd executes successfully.
1751
1752 **/
1753 EFI_STATUS
1754 EFIAPI
1755 AhciDeviceSetFeature (
1756   IN EFI_PCI_IO_PROTOCOL    *PciIo,
1757   IN EFI_AHCI_REGISTERS     *AhciRegisters,
1758   IN UINT8                  Port,
1759   IN UINT8                  PortMultiplier,
1760   IN UINT16                 Feature,
1761   IN UINT32                 FeatureSpecificData
1762   )
1763 {
1764   EFI_STATUS               Status;
1765   EFI_ATA_COMMAND_BLOCK    AtaCommandBlock;
1766   EFI_ATA_STATUS_BLOCK     AtaStatusBlock;
1767
1768   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1769   ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1770
1771   AtaCommandBlock.AtaCommand      = ATA_CMD_SET_FEATURES;
1772   AtaCommandBlock.AtaFeatures     = (UINT8) Feature;
1773   AtaCommandBlock.AtaFeaturesExp  = (UINT8) (Feature >> 8);
1774   AtaCommandBlock.AtaSectorCount  = (UINT8) FeatureSpecificData;
1775   AtaCommandBlock.AtaSectorNumber = (UINT8) (FeatureSpecificData >> 8);
1776   AtaCommandBlock.AtaCylinderLow  = (UINT8) (FeatureSpecificData >> 16);
1777   AtaCommandBlock.AtaCylinderHigh = (UINT8) (FeatureSpecificData >> 24);
1778
1779   Status = AhciNonDataTransfer (
1780              PciIo,
1781              AhciRegisters,
1782              (UINT8)Port,
1783              (UINT8)PortMultiplier,
1784              NULL,
1785              0,
1786              &AtaCommandBlock,
1787              &AtaStatusBlock,
1788              ATA_ATAPI_TIMEOUT,
1789              NULL
1790              );
1791
1792   return Status;
1793 }
1794
1795 /**
1796   This function is used to send out ATAPI commands conforms to the Packet Command
1797   with PIO Protocol.
1798
1799   @param PciIo              The PCI IO protocol instance.
1800   @param AhciRegisters      The pointer to the EFI_AHCI_REGISTERS.
1801   @param Port               The number of port.
1802   @param PortMultiplier     The number of port multiplier.
1803   @param Packet             A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
1804
1805   @retval EFI_SUCCESS       send out the ATAPI packet command successfully
1806                             and device sends data successfully.
1807   @retval EFI_DEVICE_ERROR  the device failed to send data.
1808
1809 **/
1810 EFI_STATUS
1811 EFIAPI
1812 AhciPacketCommandExecute (
1813   IN  EFI_PCI_IO_PROTOCOL                           *PciIo,
1814   IN  EFI_AHCI_REGISTERS                            *AhciRegisters,
1815   IN  UINT8                                         Port,
1816   IN  UINT8                                         PortMultiplier,
1817   IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet
1818   )
1819 {
1820   EFI_STATUS                   Status;
1821   VOID                         *Buffer;
1822   UINT32                       Length;
1823   EFI_ATA_COMMAND_BLOCK        AtaCommandBlock;
1824   EFI_ATA_STATUS_BLOCK         AtaStatusBlock;
1825   BOOLEAN                      Read;
1826
1827   if (Packet == NULL || Packet->Cdb == NULL) {
1828     return EFI_INVALID_PARAMETER;
1829   }
1830
1831   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1832   ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1833   AtaCommandBlock.AtaCommand      = ATA_CMD_PACKET;
1834   //
1835   // No OVL; No DMA
1836   //
1837   AtaCommandBlock.AtaFeatures     = 0x00;
1838   //
1839   // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
1840   // determine how many data should be transferred.
1841   //
1842   AtaCommandBlock.AtaCylinderLow  = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
1843   AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
1844
1845   if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
1846     Buffer = Packet->InDataBuffer;
1847     Length = Packet->InTransferLength;
1848     Read = TRUE;
1849   } else {
1850     Buffer = Packet->OutDataBuffer;
1851     Length = Packet->OutTransferLength;
1852     Read = FALSE;
1853   }
1854
1855   if (Length == 0) {
1856     Status = AhciNonDataTransfer (
1857                PciIo,
1858                AhciRegisters,
1859                Port,
1860                PortMultiplier,
1861                Packet->Cdb,
1862                Packet->CdbLength,
1863                &AtaCommandBlock,
1864                &AtaStatusBlock,
1865                Packet->Timeout,
1866                NULL
1867                );
1868   } else {
1869     Status = AhciPioTransfer (
1870                PciIo,
1871                AhciRegisters,
1872                Port,
1873                PortMultiplier,
1874                Packet->Cdb,
1875                Packet->CdbLength,
1876                Read,
1877                &AtaCommandBlock,
1878                &AtaStatusBlock,
1879                Buffer,
1880                Length,
1881                Packet->Timeout,
1882                NULL
1883                );
1884   }
1885   return Status;
1886 }
1887
1888 /**
1889   Allocate transfer-related data struct which is used at AHCI mode.
1890
1891   @param  PciIo                 The PCI IO protocol instance.
1892   @param  AhciRegisters         The pointer to the EFI_AHCI_REGISTERS.
1893
1894 **/
1895 EFI_STATUS
1896 EFIAPI
1897 AhciCreateTransferDescriptor (
1898   IN     EFI_PCI_IO_PROTOCOL    *PciIo,
1899   IN OUT EFI_AHCI_REGISTERS     *AhciRegisters
1900   )
1901 {
1902   EFI_STATUS            Status;
1903   UINTN                 Bytes;
1904   VOID                  *Buffer;
1905
1906   UINT32                Capability;
1907   UINT8                 MaxPortNumber;
1908   UINT8                 MaxCommandSlotNumber;
1909   BOOLEAN               Support64Bit;
1910   UINT64                MaxReceiveFisSize;
1911   UINT64                MaxCommandListSize;
1912   UINT64                MaxCommandTableSize;
1913   EFI_PHYSICAL_ADDRESS  AhciRFisPciAddr;
1914   EFI_PHYSICAL_ADDRESS  AhciCmdListPciAddr;
1915   EFI_PHYSICAL_ADDRESS  AhciCommandTablePciAddr;
1916
1917   Buffer = NULL;
1918   //
1919   // Collect AHCI controller information
1920   //
1921   Capability           = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
1922   MaxPortNumber        = (UINT8) ((Capability & 0x1F) + 1);
1923   //
1924   // Get the number of command slots per port supported by this HBA.
1925   //
1926   MaxCommandSlotNumber = (UINT8) (((Capability & 0x1F00) >> 8) + 1);
1927   Support64Bit         = (BOOLEAN) (((Capability & BIT31) != 0) ? TRUE : FALSE);
1928
1929   MaxReceiveFisSize    = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);
1930   Status = PciIo->AllocateBuffer (
1931                     PciIo,
1932                     AllocateAnyPages,
1933                     EfiBootServicesData,
1934                     EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
1935                     &Buffer,
1936                     0
1937                     );
1938
1939   if (EFI_ERROR (Status)) {
1940     return EFI_OUT_OF_RESOURCES;
1941   }
1942
1943   ZeroMem (Buffer, (UINTN)MaxReceiveFisSize);
1944
1945   AhciRegisters->AhciRFis          = Buffer;
1946   AhciRegisters->MaxReceiveFisSize = MaxReceiveFisSize;
1947   Bytes  = (UINTN)MaxReceiveFisSize;
1948
1949   Status = PciIo->Map (
1950                     PciIo,
1951                     EfiPciIoOperationBusMasterCommonBuffer,
1952                     Buffer,
1953                     &Bytes,
1954                     &AhciRFisPciAddr,
1955                     &AhciRegisters->MapRFis
1956                     );
1957
1958   if (EFI_ERROR (Status) || (Bytes != MaxReceiveFisSize)) {
1959     //
1960     // Map error or unable to map the whole RFis buffer into a contiguous region.
1961     //
1962     Status = EFI_OUT_OF_RESOURCES;
1963     goto Error6;
1964   }
1965
1966   if ((!Support64Bit) && (AhciRFisPciAddr > 0x100000000ULL)) {
1967     //
1968     // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
1969     //
1970     Status = EFI_DEVICE_ERROR;
1971     goto Error5;
1972   }
1973   AhciRegisters->AhciRFisPciAddr = (EFI_AHCI_RECEIVED_FIS *)(UINTN)AhciRFisPciAddr;
1974
1975   //
1976   // Allocate memory for command list
1977   // Note that the implemenation is a single task model which only use a command list for all ports.
1978   //
1979   Buffer = NULL;
1980   MaxCommandListSize = MaxCommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST);
1981   Status = PciIo->AllocateBuffer (
1982                     PciIo,
1983                     AllocateAnyPages,
1984                     EfiBootServicesData,
1985                     EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
1986                     &Buffer,
1987                     0
1988                     );
1989
1990   if (EFI_ERROR (Status)) {
1991     //
1992     // Free mapped resource.
1993     //
1994     Status = EFI_OUT_OF_RESOURCES;
1995     goto Error5;
1996   }
1997
1998   ZeroMem (Buffer, (UINTN)MaxCommandListSize);
1999
2000   AhciRegisters->AhciCmdList        = Buffer;
2001   AhciRegisters->MaxCommandListSize = MaxCommandListSize;
2002   Bytes  = (UINTN)MaxCommandListSize;
2003
2004   Status = PciIo->Map (
2005                     PciIo,
2006                     EfiPciIoOperationBusMasterCommonBuffer,
2007                     Buffer,
2008                     &Bytes,
2009                     &AhciCmdListPciAddr,
2010                     &AhciRegisters->MapCmdList
2011                     );
2012
2013   if (EFI_ERROR (Status) || (Bytes != MaxCommandListSize)) {
2014     //
2015     // Map error or unable to map the whole cmd list buffer into a contiguous region.
2016     //
2017     Status = EFI_OUT_OF_RESOURCES;
2018     goto Error4;
2019   }
2020
2021   if ((!Support64Bit) && (AhciCmdListPciAddr > 0x100000000ULL)) {
2022     //
2023     // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2024     //
2025     Status = EFI_DEVICE_ERROR;
2026     goto Error3;
2027   }
2028   AhciRegisters->AhciCmdListPciAddr = (EFI_AHCI_COMMAND_LIST *)(UINTN)AhciCmdListPciAddr;
2029
2030   //
2031   // Allocate memory for command table
2032   // According to AHCI 1.3 spec, a PRD table can contain maximum 65535 entries.
2033   //
2034   Buffer = NULL;
2035   MaxCommandTableSize = sizeof (EFI_AHCI_COMMAND_TABLE);
2036
2037   Status = PciIo->AllocateBuffer (
2038                     PciIo,
2039                     AllocateAnyPages,
2040                     EfiBootServicesData,
2041                     EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2042                     &Buffer,
2043                     0
2044                     );
2045
2046   if (EFI_ERROR (Status)) {
2047     //
2048     // Free mapped resource.
2049     //
2050     Status = EFI_OUT_OF_RESOURCES;
2051     goto Error3;
2052   }
2053
2054   ZeroMem (Buffer, (UINTN)MaxCommandTableSize);
2055
2056   AhciRegisters->AhciCommandTable    = Buffer;
2057   AhciRegisters->MaxCommandTableSize = MaxCommandTableSize;
2058   Bytes  = (UINTN)MaxCommandTableSize;
2059
2060   Status = PciIo->Map (
2061                     PciIo,
2062                     EfiPciIoOperationBusMasterCommonBuffer,
2063                     Buffer,
2064                     &Bytes,
2065                     &AhciCommandTablePciAddr,
2066                     &AhciRegisters->MapCommandTable
2067                     );
2068
2069   if (EFI_ERROR (Status) || (Bytes != MaxCommandTableSize)) {
2070     //
2071     // Map error or unable to map the whole cmd list buffer into a contiguous region.
2072     //
2073     Status = EFI_OUT_OF_RESOURCES;
2074     goto Error2;
2075   }
2076
2077   if ((!Support64Bit) && (AhciCommandTablePciAddr > 0x100000000ULL)) {
2078     //
2079     // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2080     //
2081     Status = EFI_DEVICE_ERROR;
2082     goto Error1;
2083   }
2084   AhciRegisters->AhciCommandTablePciAddr = (EFI_AHCI_COMMAND_TABLE *)(UINTN)AhciCommandTablePciAddr;
2085
2086   return EFI_SUCCESS;
2087   //
2088   // Map error or unable to map the whole CmdList buffer into a contiguous region.
2089   //
2090 Error1:
2091   PciIo->Unmap (
2092            PciIo,
2093            AhciRegisters->MapCommandTable
2094            );
2095 Error2:
2096   PciIo->FreeBuffer (
2097            PciIo,
2098            EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2099            AhciRegisters->AhciCommandTable
2100            );
2101 Error3:
2102   PciIo->Unmap (
2103            PciIo,
2104            AhciRegisters->MapCmdList
2105            );
2106 Error4:
2107   PciIo->FreeBuffer (
2108            PciIo,
2109            EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
2110            AhciRegisters->AhciCmdList
2111            );
2112 Error5:
2113   PciIo->Unmap (
2114            PciIo,
2115            AhciRegisters->MapRFis
2116            );
2117 Error6:
2118   PciIo->FreeBuffer (
2119            PciIo,
2120            EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
2121            AhciRegisters->AhciRFis
2122            );
2123
2124   return Status;
2125 }
2126
2127 /**
2128   Initialize ATA host controller at AHCI mode.
2129
2130   The function is designed to initialize ATA host controller.
2131
2132   @param[in]  Instance          A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
2133
2134 **/
2135 EFI_STATUS
2136 EFIAPI
2137 AhciModeInitialization (
2138   IN  ATA_ATAPI_PASS_THRU_INSTANCE    *Instance
2139   )
2140 {
2141   EFI_STATUS                       Status;
2142   EFI_PCI_IO_PROTOCOL              *PciIo;
2143   EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2144   UINT32                           Capability;
2145   UINT8                            MaxPortNumber;
2146   UINT32                           PortImplementBitMap;
2147
2148   EFI_AHCI_REGISTERS               *AhciRegisters;
2149
2150   UINT8                            Port;
2151   DATA_64                          Data64;
2152   UINT32                           Offset;
2153   UINT32                           Data;
2154   EFI_IDENTIFY_DATA                Buffer;
2155   EFI_ATA_DEVICE_TYPE              DeviceType;
2156   EFI_ATA_COLLECTIVE_MODE          *SupportedModes;
2157   EFI_ATA_TRANSFER_MODE            TransferMode;
2158   UINT32                           PhyDetectDelay;
2159
2160   if (Instance == NULL) {
2161     return EFI_INVALID_PARAMETER;
2162   }
2163
2164   PciIo   = Instance->PciIo;
2165   IdeInit = Instance->IdeControllerInit;
2166
2167   Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT);
2168
2169   if (EFI_ERROR (Status)) {
2170     return EFI_DEVICE_ERROR;
2171   }
2172
2173   //
2174   // Enable AE before accessing any AHCI registers
2175   //
2176   AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
2177
2178   //
2179   // Collect AHCI controller information
2180   //
2181   Capability           = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
2182
2183   //
2184   // Get the number of command slots per port supported by this HBA.
2185   //
2186   MaxPortNumber        = (UINT8) ((Capability & 0x1F) + 1);
2187
2188   //
2189   // Get the bit map of those ports exposed by this HBA.
2190   // It indicates which ports that the HBA supports are available for software to use.
2191   //
2192   PortImplementBitMap  = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
2193
2194   AhciRegisters = &Instance->AhciRegisters;
2195   Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);
2196
2197   if (EFI_ERROR (Status)) {
2198     return EFI_OUT_OF_RESOURCES;
2199   }
2200
2201   for (Port = 0; Port < MaxPortNumber; Port ++) {
2202     if ((PortImplementBitMap & (BIT0 << Port)) != 0) {
2203       IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, Port);
2204
2205       //
2206       // Initialize FIS Base Address Register and Command List Base Address Register for use.
2207       //
2208       Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFisPciAddr) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
2209       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FB;
2210       AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2211       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FBU;
2212       AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2213
2214       Data64.Uint64 = (UINTN) (AhciRegisters->AhciCmdListPciAddr);
2215       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLB;
2216       AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2217       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLBU;
2218       AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2219
2220       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2221       Data = AhciReadReg (PciIo, Offset);
2222       if ((Data & EFI_AHCI_PORT_CMD_CPD) != 0) {
2223         AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_POD);
2224       }
2225
2226       if ((Capability & EFI_AHCI_CAP_SSS) != 0) {
2227         AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_SUD);
2228       }
2229
2230       //
2231       // Disable aggressive power management.
2232       //
2233       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
2234       AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_IPM_INIT);
2235       //
2236       // Disable the reporting of the corresponding interrupt to system software.
2237       //
2238       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IE;
2239       AhciAndReg (PciIo, Offset, 0);
2240
2241       //
2242       // Now inform the IDE Controller Init Module.
2243       //
2244       IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, Port);
2245
2246       //
2247       // Enable FIS Receive DMA engine for the first D2H FIS.
2248       //
2249       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2250       AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
2251       Status = AhciWaitMmioSet (
2252                  PciIo,
2253                  Offset,
2254                  EFI_AHCI_PORT_CMD_FR,
2255                  EFI_AHCI_PORT_CMD_FR,
2256                  EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT
2257                  );
2258       if (EFI_ERROR (Status)) {
2259         continue;
2260       }
2261
2262       //
2263       // Wait no longer than 10 ms to wait the Phy to detect the presence of a device.
2264       // It's the requirment from SATA1.0a spec section 5.2.
2265       //
2266       PhyDetectDelay = EFI_AHCI_BUS_PHY_DETECT_TIMEOUT;
2267       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
2268       do {
2269         Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
2270         if ((Data == EFI_AHCI_PORT_SSTS_DET_PCE) || (Data == EFI_AHCI_PORT_SSTS_DET)) {
2271           break;
2272         }
2273
2274         MicroSecondDelay (1000);
2275         PhyDetectDelay--;
2276       } while (PhyDetectDelay > 0);
2277
2278       if (PhyDetectDelay == 0) {
2279         //
2280         // No device detected at this port.
2281         //
2282         continue;
2283       }
2284
2285       //
2286       // According to SATA1.0a spec section 5.2, we need to wait for PxTFD.BSY and PxTFD.DRQ
2287       // and PxTFD.ERR to be zero. The maximum wait time is 16s which is defined at ATA spec.
2288       //
2289       PhyDetectDelay = 16 * 1000;
2290       do {
2291         Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
2292         if (AhciReadReg(PciIo, Offset) != 0) {
2293           AhciWriteReg (PciIo, Offset, AhciReadReg(PciIo, Offset));
2294         }
2295         Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
2296
2297         Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_TFD_MASK;
2298         if (Data == 0) {
2299           break;
2300         }
2301
2302         MicroSecondDelay (1000);
2303         PhyDetectDelay--;
2304       } while (PhyDetectDelay > 0);
2305
2306       if (PhyDetectDelay == 0) {
2307         continue;
2308       }
2309
2310       //
2311       // When the first D2H register FIS is received, the content of PxSIG register is updated.
2312       //
2313       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;
2314       Status = AhciWaitMmioSet (
2315                  PciIo,
2316                  Offset,
2317                  0x0000FFFF,
2318                  0x00000101,
2319                  EFI_TIMER_PERIOD_SECONDS(16)
2320                  );
2321       if (EFI_ERROR (Status)) {
2322         continue;
2323       }
2324
2325       Data = AhciReadReg (PciIo, Offset);
2326       if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATAPI_DEVICE_SIG) {
2327         Status = AhciIdentifyPacket (PciIo, AhciRegisters, Port, 0, &Buffer);
2328
2329         if (EFI_ERROR (Status)) {
2330           continue;
2331         }
2332
2333         DeviceType = EfiIdeCdrom;
2334       } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATA_DEVICE_SIG) {
2335         Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer);
2336
2337         if (EFI_ERROR (Status)) {
2338           REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
2339           continue;
2340         }
2341
2342         DeviceType = EfiIdeHarddisk;
2343       } else {
2344         continue;
2345       }
2346       DEBUG ((EFI_D_INFO, "port [%d] port mulitplier [%d] has a [%a]\n",
2347               Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));
2348
2349       //
2350       // If the device is a hard disk, then try to enable S.M.A.R.T feature
2351       //
2352       if (DeviceType == EfiIdeHarddisk) {
2353         AhciAtaSmartSupport (
2354           PciIo,
2355           AhciRegisters,
2356           Port,
2357           0,
2358           &Buffer,
2359           NULL
2360           );
2361       }
2362
2363       //
2364       // Submit identify data to IDE controller init driver
2365       //
2366       IdeInit->SubmitData (IdeInit, Port, 0, &Buffer);
2367
2368       //
2369       // Now start to config ide device parameter and transfer mode.
2370       //
2371       Status = IdeInit->CalculateMode (
2372                           IdeInit,
2373                           Port,
2374                           0,
2375                           &SupportedModes
2376                           );
2377       if (EFI_ERROR (Status)) {
2378         DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
2379         continue;
2380       }
2381
2382       //
2383       // Set best supported PIO mode on this IDE device
2384       //
2385       if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
2386         TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
2387       } else {
2388         TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
2389       }
2390
2391       TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
2392
2393       //
2394       // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't
2395       // be set together. Only one DMA mode can be set to a device. If setting
2396       // DMA mode operation fails, we can continue moving on because we only use
2397       // PIO mode at boot time. DMA modes are used by certain kind of OS booting
2398       //
2399       if (SupportedModes->UdmaMode.Valid) {
2400         TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
2401         TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
2402       } else if (SupportedModes->MultiWordDmaMode.Valid) {
2403         TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
2404         TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
2405       }
2406
2407       Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode));
2408       if (EFI_ERROR (Status)) {
2409         DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2410         continue;
2411       }
2412
2413       //
2414       // Found a ATA or ATAPI device, add it into the device list.
2415       //
2416       CreateNewDeviceInfo (Instance, Port, 0, DeviceType, &Buffer);
2417       if (DeviceType == EfiIdeHarddisk) {
2418         REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
2419       }
2420     }
2421   }
2422
2423   return EFI_SUCCESS;
2424 }
2425