MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h

   1 /** @file
   2   Header file for AHCI mode of ATA host controller.
   3
   4   Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14 #ifndef __ATA_HC_AHCI_MODE_H__
  15 #define __ATA_HC_AHCI_MODE_H__
  16
  17 #define EFI_AHCI_BAR_INDEX                     0x05
  18
  19 #define EFI_AHCI_CAPABILITY_OFFSET             0x0000
  20 #define   EFI_AHCI_CAP_SAM                     BIT18
  21 #define   EFI_AHCI_CAP_SSS                     BIT27
  22 #define   EFI_AHCI_CAP_S64A                    BIT31
  23 #define EFI_AHCI_GHC_OFFSET                    0x0004
  24 #define   EFI_AHCI_GHC_RESET                   BIT0
  25 #define   EFI_AHCI_GHC_IE                      BIT1
  26 #define   EFI_AHCI_GHC_ENABLE                  BIT31
  27 #define EFI_AHCI_IS_OFFSET                     0x0008
  28 #define EFI_AHCI_PI_OFFSET                     0x000C
  29
  30 #define EFI_AHCI_MAX_PORTS                     32
  31
  32 #define AHCI_CAPABILITY2_OFFSET                0x0024
  33 #define   AHCI_CAP2_SDS                        BIT3
  34 #define   AHCI_CAP2_SADM                       BIT4
  35
  36 typedef struct {
  37   UINT32  Lower32;
  38   UINT32  Upper32;
  39 } DATA_32;
  40
  41 typedef union {
  42   DATA_32   Uint32;
  43   UINT64    Uint64;
  44 } DATA_64;
  45
  46 //
  47 // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
  48 // Add a bit of margin for robustness.
  49 //
  50 #define  EFI_AHCI_BUS_PHY_DETECT_TIMEOUT       15
  51 //
  52 // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
  53 //
  54 #define  EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT    EFI_TIMER_PERIOD_MILLISECONDS(500)
  55 //
  56 // Refer SATA1.0a spec, the bus reset time should be less than 1s.
  57 //
  58 #define  EFI_AHCI_BUS_RESET_TIMEOUT            EFI_TIMER_PERIOD_SECONDS(1)
  59
  60 #define  EFI_AHCI_ATAPI_DEVICE_SIG             0xEB140000
  61 #define  EFI_AHCI_ATA_DEVICE_SIG               0x00000000
  62 #define  EFI_AHCI_PORT_MULTIPLIER_SIG          0x96690000
  63 #define  EFI_AHCI_ATAPI_SIG_MASK               0xFFFF0000
  64
  65 //
  66 // Each PRDT entry can point to a memory block up to 4M byte
  67 //
  68 #define EFI_AHCI_MAX_DATA_PER_PRDT             0x400000
  69
  70 #define EFI_AHCI_FIS_REGISTER_H2D              0x27      //Register FIS - Host to Device
  71 #define   EFI_AHCI_FIS_REGISTER_H2D_LENGTH     20
  72 #define EFI_AHCI_FIS_REGISTER_D2H              0x34      //Register FIS - Device to Host
  73 #define   EFI_AHCI_FIS_REGISTER_D2H_LENGTH     20
  74 #define EFI_AHCI_FIS_DMA_ACTIVATE              0x39      //DMA Activate FIS - Device to Host
  75 #define   EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH     4
  76 #define EFI_AHCI_FIS_DMA_SETUP                 0x41      //DMA Setup FIS - Bi-directional
  77 #define   EFI_AHCI_FIS_DMA_SETUP_LENGTH        28
  78 #define EFI_AHCI_FIS_DATA                      0x46      //Data FIS - Bi-directional
  79 #define EFI_AHCI_FIS_BIST                      0x58      //BIST Activate FIS - Bi-directional
  80 #define   EFI_AHCI_FIS_BIST_LENGTH             12
  81 #define EFI_AHCI_FIS_PIO_SETUP                 0x5F      //PIO Setup FIS - Device to Host
  82 #define   EFI_AHCI_FIS_PIO_SETUP_LENGTH        20
  83 #define EFI_AHCI_FIS_SET_DEVICE                0xA1      //Set Device Bits FIS - Device to Host
  84 #define   EFI_AHCI_FIS_SET_DEVICE_LENGTH       8
  85
  86 #define EFI_AHCI_D2H_FIS_OFFSET                0x40
  87 #define EFI_AHCI_DMA_FIS_OFFSET                0x00
  88 #define EFI_AHCI_PIO_FIS_OFFSET                0x20
  89 #define EFI_AHCI_SDB_FIS_OFFSET                0x58
  90 #define EFI_AHCI_FIS_TYPE_MASK                 0xFF
  91 #define EFI_AHCI_U_FIS_OFFSET                  0x60
  92
  93 //
  94 // Port register
  95 //
  96 #define EFI_AHCI_PORT_START                    0x0100
  97 #define EFI_AHCI_PORT_REG_WIDTH                0x0080
  98 #define EFI_AHCI_PORT_CLB                      0x0000
  99 #define EFI_AHCI_PORT_CLBU                     0x0004
 100 #define EFI_AHCI_PORT_FB                       0x0008
 101 #define EFI_AHCI_PORT_FBU                      0x000C
 102 #define EFI_AHCI_PORT_IS                       0x0010
 103 #define   EFI_AHCI_PORT_IS_DHRS                BIT0
 104 #define   EFI_AHCI_PORT_IS_PSS                 BIT1
 105 #define   EFI_AHCI_PORT_IS_SSS                 BIT2
 106 #define   EFI_AHCI_PORT_IS_SDBS                BIT3
 107 #define   EFI_AHCI_PORT_IS_UFS                 BIT4
 108 #define   EFI_AHCI_PORT_IS_DPS                 BIT5
 109 #define   EFI_AHCI_PORT_IS_PCS                 BIT6
 110 #define   EFI_AHCI_PORT_IS_DIS                 BIT7
 111 #define   EFI_AHCI_PORT_IS_PRCS                BIT22
 112 #define   EFI_AHCI_PORT_IS_IPMS                BIT23
 113 #define   EFI_AHCI_PORT_IS_OFS                 BIT24
 114 #define   EFI_AHCI_PORT_IS_INFS                BIT26
 115 #define   EFI_AHCI_PORT_IS_IFS                 BIT27
 116 #define   EFI_AHCI_PORT_IS_HBDS                BIT28
 117 #define   EFI_AHCI_PORT_IS_HBFS                BIT29
 118 #define   EFI_AHCI_PORT_IS_TFES                BIT30
 119 #define   EFI_AHCI_PORT_IS_CPDS                BIT31
 120 #define   EFI_AHCI_PORT_IS_CLEAR               0xFFFFFFFF
 121 #define   EFI_AHCI_PORT_IS_FIS_CLEAR           0x0000000F
 122
 123 #define EFI_AHCI_PORT_IE                       0x0014
 124 #define EFI_AHCI_PORT_CMD                      0x0018
 125 #define   EFI_AHCI_PORT_CMD_ST_MASK            0xFFFFFFFE
 126 #define   EFI_AHCI_PORT_CMD_ST                 BIT0
 127 #define   EFI_AHCI_PORT_CMD_SUD                BIT1
 128 #define   EFI_AHCI_PORT_CMD_POD                BIT2
 129 #define   EFI_AHCI_PORT_CMD_CLO                BIT3
 130 #define   EFI_AHCI_PORT_CMD_CR                 BIT15
 131 #define   EFI_AHCI_PORT_CMD_FRE                BIT4
 132 #define   EFI_AHCI_PORT_CMD_FR                 BIT14
 133 #define   EFI_AHCI_PORT_CMD_MASK               ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
 134 #define   EFI_AHCI_PORT_CMD_PMA                BIT17
 135 #define   EFI_AHCI_PORT_CMD_HPCP               BIT18
 136 #define   EFI_AHCI_PORT_CMD_MPSP               BIT19
 137 #define   EFI_AHCI_PORT_CMD_CPD                BIT20
 138 #define   EFI_AHCI_PORT_CMD_ESP                BIT21
 139 #define   EFI_AHCI_PORT_CMD_ATAPI              BIT24
 140 #define   EFI_AHCI_PORT_CMD_DLAE               BIT25
 141 #define   EFI_AHCI_PORT_CMD_ALPE               BIT26
 142 #define   EFI_AHCI_PORT_CMD_ASP                BIT27
 143 #define   EFI_AHCI_PORT_CMD_ICC_MASK           (BIT28 | BIT29 | BIT30 | BIT31)
 144 #define   EFI_AHCI_PORT_CMD_ACTIVE             (1 << 28 )
 145 #define EFI_AHCI_PORT_TFD                      0x0020
 146 #define   EFI_AHCI_PORT_TFD_MASK               (BIT7 | BIT3 | BIT0)
 147 #define   EFI_AHCI_PORT_TFD_BSY                BIT7
 148 #define   EFI_AHCI_PORT_TFD_DRQ                BIT3
 149 #define   EFI_AHCI_PORT_TFD_ERR                BIT0
 150 #define   EFI_AHCI_PORT_TFD_ERR_MASK           0x00FF00
 151 #define EFI_AHCI_PORT_SIG                      0x0024
 152 #define EFI_AHCI_PORT_SSTS                     0x0028
 153 #define   EFI_AHCI_PORT_SSTS_DET_MASK          0x000F
 154 #define   EFI_AHCI_PORT_SSTS_DET               0x0001
 155 #define   EFI_AHCI_PORT_SSTS_DET_PCE           0x0003
 156 #define   EFI_AHCI_PORT_SSTS_SPD_MASK          0x00F0
 157 #define EFI_AHCI_PORT_SCTL                     0x002C
 158 #define   EFI_AHCI_PORT_SCTL_DET_MASK          0x000F
 159 #define   EFI_AHCI_PORT_SCTL_MASK              (~EFI_AHCI_PORT_SCTL_DET_MASK)
 160 #define   EFI_AHCI_PORT_SCTL_DET_INIT          0x0001
 161 #define   EFI_AHCI_PORT_SCTL_DET_PHYCOMM       0x0003
 162 #define   EFI_AHCI_PORT_SCTL_SPD_MASK          0x00F0
 163 #define   EFI_AHCI_PORT_SCTL_IPM_MASK          0x0F00
 164 #define   EFI_AHCI_PORT_SCTL_IPM_INIT          0x0300
 165 #define   EFI_AHCI_PORT_SCTL_IPM_PSD           0x0100
 166 #define   EFI_AHCI_PORT_SCTL_IPM_SSD           0x0200
 167 #define EFI_AHCI_PORT_SERR                     0x0030
 168 #define   EFI_AHCI_PORT_SERR_RDIE              BIT0
 169 #define   EFI_AHCI_PORT_SERR_RCE               BIT1
 170 #define   EFI_AHCI_PORT_SERR_TDIE              BIT8
 171 #define   EFI_AHCI_PORT_SERR_PCDIE             BIT9
 172 #define   EFI_AHCI_PORT_SERR_PE                BIT10
 173 #define   EFI_AHCI_PORT_SERR_IE                BIT11
 174 #define   EFI_AHCI_PORT_SERR_PRC               BIT16
 175 #define   EFI_AHCI_PORT_SERR_PIE               BIT17
 176 #define   EFI_AHCI_PORT_SERR_CW                BIT18
 177 #define   EFI_AHCI_PORT_SERR_BDE               BIT19
 178 #define   EFI_AHCI_PORT_SERR_DE                BIT20
 179 #define   EFI_AHCI_PORT_SERR_CRCE              BIT21
 180 #define   EFI_AHCI_PORT_SERR_HE                BIT22
 181 #define   EFI_AHCI_PORT_SERR_LSE               BIT23
 182 #define   EFI_AHCI_PORT_SERR_TSTE              BIT24
 183 #define   EFI_AHCI_PORT_SERR_UFT               BIT25
 184 #define   EFI_AHCI_PORT_SERR_EX                BIT26
 185 #define   EFI_AHCI_PORT_ERR_CLEAR              0xFFFFFFFF
 186 #define EFI_AHCI_PORT_SACT                     0x0034
 187 #define EFI_AHCI_PORT_CI                       0x0038
 188 #define EFI_AHCI_PORT_SNTF                     0x003C
 189 #define AHCI_PORT_DEVSLP                       0x0044
 190 #define   AHCI_PORT_DEVSLP_ADSE                BIT0
 191 #define   AHCI_PORT_DEVSLP_DSP                 BIT1
 192 #define   AHCI_PORT_DEVSLP_DETO_MASK           0x000003FC
 193 #define   AHCI_PORT_DEVSLP_MDAT_MASK           0x00007C00
 194 #define   AHCI_PORT_DEVSLP_DITO_MASK           0x01FF8000
 195 #define   AHCI_PORT_DEVSLP_DM_MASK             0x1E000000
 196
 197 #pragma pack(1)
 198 //
 199 // Command List structure includes total 32 entries.
 200 // The entry data structure is listed at the following.
 201 //
 202 typedef struct {
 203   UINT32   AhciCmdCfl:5;      //Command FIS Length
 204   UINT32   AhciCmdA:1;        //ATAPI
 205   UINT32   AhciCmdW:1;        //Write
 206   UINT32   AhciCmdP:1;        //Prefetchable
 207   UINT32   AhciCmdR:1;        //Reset
 208   UINT32   AhciCmdB:1;        //BIST
 209   UINT32   AhciCmdC:1;        //Clear Busy upon R_OK
 210   UINT32   AhciCmdRsvd:1;
 211   UINT32   AhciCmdPmp:4;      //Port Multiplier Port
 212   UINT32   AhciCmdPrdtl:16;   //Physical Region Descriptor Table Length
 213   UINT32   AhciCmdPrdbc;      //Physical Region Descriptor Byte Count
 214   UINT32   AhciCmdCtba;       //Command Table Descriptor Base Address
 215   UINT32   AhciCmdCtbau;      //Command Table Descriptor Base Address Upper 32-BITs
 216   UINT32   AhciCmdRsvd1[4];
 217 } EFI_AHCI_COMMAND_LIST;
 218
 219 //
 220 // This is a software constructed FIS.
 221 // For data transfer operations, this is the H2D Register FIS format as
 222 // specified in the Serial ATA Revision 2.6 specification.
 223 //
 224 typedef struct {
 225   UINT8    AhciCFisType;
 226   UINT8    AhciCFisPmNum:4;
 227   UINT8    AhciCFisRsvd:1;
 228   UINT8    AhciCFisRsvd1:1;
 229   UINT8    AhciCFisRsvd2:1;
 230   UINT8    AhciCFisCmdInd:1;
 231   UINT8    AhciCFisCmd;
 232   UINT8    AhciCFisFeature;
 233   UINT8    AhciCFisSecNum;
 234   UINT8    AhciCFisClyLow;
 235   UINT8    AhciCFisClyHigh;
 236   UINT8    AhciCFisDevHead;
 237   UINT8    AhciCFisSecNumExp;
 238   UINT8    AhciCFisClyLowExp;
 239   UINT8    AhciCFisClyHighExp;
 240   UINT8    AhciCFisFeatureExp;
 241   UINT8    AhciCFisSecCount;
 242   UINT8    AhciCFisSecCountExp;
 243   UINT8    AhciCFisRsvd3;
 244   UINT8    AhciCFisControl;
 245   UINT8    AhciCFisRsvd4[4];
 246   UINT8    AhciCFisRsvd5[44];
 247 } EFI_AHCI_COMMAND_FIS;
 248
 249 //
 250 // ACMD: ATAPI command (12 or 16 bytes)
 251 //
 252 typedef struct {
 253   UINT8    AtapiCmd[0x10];
 254 } EFI_AHCI_ATAPI_COMMAND;
 255
 256 //
 257 // Physical Region Descriptor Table includes up to 65535 entries
 258 // The entry data structure is listed at the following.
 259 // the actual entry number comes from the PRDTL field in the command
 260 // list entry for this command slot.
 261 //
 262 typedef struct {
 263   UINT32   AhciPrdtDba;       //Data Base Address
 264   UINT32   AhciPrdtDbau;      //Data Base Address Upper 32-BITs
 265   UINT32   AhciPrdtRsvd;
 266   UINT32   AhciPrdtDbc:22;    //Data Byte Count
 267   UINT32   AhciPrdtRsvd1:9;
 268   UINT32   AhciPrdtIoc:1;     //Interrupt on Completion
 269 } EFI_AHCI_COMMAND_PRDT;
 270
 271 //
 272 // Command table data strucute which is pointed to by the entry in the command list
 273 //
 274 typedef struct {
 275   EFI_AHCI_COMMAND_FIS      CommandFis;       // A software constructed FIS.
 276   EFI_AHCI_ATAPI_COMMAND    AtapiCmd;         // 12 or 16 bytes ATAPI cmd.
 277   UINT8                     Reserved[0x30];
 278   EFI_AHCI_COMMAND_PRDT     PrdtTable[65535];     // The scatter/gather list for data transfer
 279 } EFI_AHCI_COMMAND_TABLE;
 280
 281 //
 282 // Received FIS structure
 283 //
 284 typedef struct {
 285   UINT8    AhciDmaSetupFis[0x1C];         // Dma Setup Fis: offset 0x00
 286   UINT8    AhciDmaSetupFisRsvd[0x04];
 287   UINT8    AhciPioSetupFis[0x14];         // Pio Setup Fis: offset 0x20
 288   UINT8    AhciPioSetupFisRsvd[0x0C];
 289   UINT8    AhciD2HRegisterFis[0x14];      // D2H Register Fis: offset 0x40
 290   UINT8    AhciD2HRegisterFisRsvd[0x04];
 291   UINT64   AhciSetDeviceBitsFis;          // Set Device Bits Fix: offset 0x58
 292   UINT8    AhciUnknownFis[0x40];          // Unkonwn Fis: offset 0x60
 293   UINT8    AhciUnknownFisRsvd[0x60];
 294 } EFI_AHCI_RECEIVED_FIS;
 295
 296 typedef struct {
 297   UINT8  Madt : 5;
 298   UINT8  Reserved_5 : 3;
 299   UINT8  Deto;
 300   UINT16 Reserved_16;
 301   UINT32 Reserved_32 : 31;
 302   UINT32 Supported : 1;
 303 } DEVSLP_TIMING_VARIABLES;
 304
 305 #pragma pack()
 306
 307 typedef struct {
 308   EFI_AHCI_RECEIVED_FIS     *AhciRFis;
 309   EFI_AHCI_COMMAND_LIST     *AhciCmdList;
 310   EFI_AHCI_COMMAND_TABLE    *AhciCommandTable;
 311   EFI_AHCI_RECEIVED_FIS     *AhciRFisPciAddr;
 312   EFI_AHCI_COMMAND_LIST     *AhciCmdListPciAddr;
 313   EFI_AHCI_COMMAND_TABLE    *AhciCommandTablePciAddr;
 314   UINT64                    MaxCommandListSize;
 315   UINT64                    MaxCommandTableSize;
 316   UINT64                    MaxReceiveFisSize;
 317   VOID                      *MapRFis;
 318   VOID                      *MapCmdList;
 319   VOID                      *MapCommandTable;
 320 } EFI_AHCI_REGISTERS;
 321
 322 /**
 323   This function is used to send out ATAPI commands conforms to the Packet Command
 324   with PIO Protocol.
 325
 326   @param PciIo              The PCI IO protocol instance.
 327   @param AhciRegisters      The pointer to the EFI_AHCI_REGISTERS.
 328   @param Port               The number of port.
 329   @param PortMultiplier     The number of port multiplier.
 330   @param Packet             A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
 331
 332   @retval EFI_SUCCESS       send out the ATAPI packet command successfully
 333                             and device sends data successfully.
 334   @retval EFI_DEVICE_ERROR  the device failed to send data.
 335
 336 **/
 337 EFI_STATUS
 338 EFIAPI
 339 AhciPacketCommandExecute (
 340   IN  EFI_PCI_IO_PROTOCOL                           *PciIo,
 341   IN  EFI_AHCI_REGISTERS                            *AhciRegisters,
 342   IN  UINT8                                         Port,
 343   IN  UINT8                                         PortMultiplier,
 344   IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet
 345   );
 346
 347 /**
 348   Start command for give slot on specific port.
 349
 350   @param  PciIo              The PCI IO protocol instance.
 351   @param  Port               The number of port.
 352   @param  CommandSlot        The number of CommandSlot.
 353   @param  Timeout            The timeout value of start, uses 100ns as a unit.
 354
 355   @retval EFI_DEVICE_ERROR   The command start unsuccessfully.
 356   @retval EFI_TIMEOUT        The operation is time out.
 357   @retval EFI_SUCCESS        The command start successfully.
 358
 359 **/
 360 EFI_STATUS
 361 EFIAPI
 362 AhciStartCommand (
 363   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 364   IN  UINT8                     Port,
 365   IN  UINT8                     CommandSlot,
 366   IN  UINT64                    Timeout
 367   );
 368
 369 /**
 370   Stop command running for giving port
 371
 372   @param  PciIo              The PCI IO protocol instance.
 373   @param  Port               The number of port.
 374   @param  Timeout            The timeout value of stop, uses 100ns as a unit.
 375
 376   @retval EFI_DEVICE_ERROR   The command stop unsuccessfully.
 377   @retval EFI_TIMEOUT        The operation is time out.
 378   @retval EFI_SUCCESS        The command stop successfully.
 379
 380 **/
 381 EFI_STATUS
 382 EFIAPI
 383 AhciStopCommand (
 384   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 385   IN  UINT8                     Port,
 386   IN  UINT64                    Timeout
 387   );
 388
 389 #endif
 390